root / hw / ppc4xx_pci.c @ df182043
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1 | 825bb581 | aurel32 | /*
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2 | 825bb581 | aurel32 | * This program is free software; you can redistribute it and/or modify
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3 | 825bb581 | aurel32 | * it under the terms of the GNU General Public License, version 2, as
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4 | 825bb581 | aurel32 | * published by the Free Software Foundation.
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5 | 825bb581 | aurel32 | *
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6 | 825bb581 | aurel32 | * This program is distributed in the hope that it will be useful,
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7 | 825bb581 | aurel32 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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8 | 825bb581 | aurel32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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9 | 825bb581 | aurel32 | * GNU General Public License for more details.
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10 | 825bb581 | aurel32 | *
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11 | 825bb581 | aurel32 | * You should have received a copy of the GNU General Public License
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12 | 8167ee88 | Blue Swirl | * along with this program; if not, see <http://www.gnu.org/licenses/>.
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13 | 825bb581 | aurel32 | *
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14 | 825bb581 | aurel32 | * Copyright IBM Corp. 2008
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15 | 825bb581 | aurel32 | *
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16 | 825bb581 | aurel32 | * Authors: Hollis Blanchard <hollisb@us.ibm.com>
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17 | 825bb581 | aurel32 | */
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18 | 825bb581 | aurel32 | |
19 | 825bb581 | aurel32 | /* This file implements emulation of the 32-bit PCI controller found in some
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20 | 825bb581 | aurel32 | * 4xx SoCs, such as the 440EP. */
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21 | 825bb581 | aurel32 | |
22 | 825bb581 | aurel32 | #include "hw.h" |
23 | 0c34a5d7 | aurel32 | #include "ppc.h" |
24 | 0c34a5d7 | aurel32 | #include "ppc4xx.h" |
25 | 825bb581 | aurel32 | #include "pci.h" |
26 | 825bb581 | aurel32 | #include "pci_host.h" |
27 | 1e39101c | Avi Kivity | #include "exec-memory.h" |
28 | 825bb581 | aurel32 | |
29 | 825bb581 | aurel32 | #undef DEBUG
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30 | 825bb581 | aurel32 | #ifdef DEBUG
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31 | 825bb581 | aurel32 | #define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0) |
32 | 825bb581 | aurel32 | #else
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33 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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34 | 825bb581 | aurel32 | #endif /* DEBUG */ |
35 | 825bb581 | aurel32 | |
36 | 825bb581 | aurel32 | struct PCIMasterMap {
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37 | 825bb581 | aurel32 | uint32_t la; |
38 | 825bb581 | aurel32 | uint32_t ma; |
39 | 825bb581 | aurel32 | uint32_t pcila; |
40 | 825bb581 | aurel32 | uint32_t pciha; |
41 | 825bb581 | aurel32 | }; |
42 | 825bb581 | aurel32 | |
43 | 825bb581 | aurel32 | struct PCITargetMap {
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44 | 825bb581 | aurel32 | uint32_t ms; |
45 | 825bb581 | aurel32 | uint32_t la; |
46 | 825bb581 | aurel32 | }; |
47 | 825bb581 | aurel32 | |
48 | 825bb581 | aurel32 | #define PPC4xx_PCI_NR_PMMS 3 |
49 | 825bb581 | aurel32 | #define PPC4xx_PCI_NR_PTMS 2 |
50 | 825bb581 | aurel32 | |
51 | 825bb581 | aurel32 | struct PPC4xxPCIState {
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52 | 825bb581 | aurel32 | struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
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53 | 825bb581 | aurel32 | struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
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54 | 825bb581 | aurel32 | |
55 | 825bb581 | aurel32 | PCIHostState pci_state; |
56 | 825bb581 | aurel32 | PCIDevice *pci_dev; |
57 | 825bb581 | aurel32 | }; |
58 | 825bb581 | aurel32 | typedef struct PPC4xxPCIState PPC4xxPCIState; |
59 | 825bb581 | aurel32 | |
60 | 825bb581 | aurel32 | #define PCIC0_CFGADDR 0x0 |
61 | 825bb581 | aurel32 | #define PCIC0_CFGDATA 0x4 |
62 | 825bb581 | aurel32 | |
63 | 825bb581 | aurel32 | /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
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64 | 825bb581 | aurel32 | * PCI accesses. */
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65 | 825bb581 | aurel32 | #define PCIL0_PMM0LA 0x0 |
66 | 825bb581 | aurel32 | #define PCIL0_PMM0MA 0x4 |
67 | 825bb581 | aurel32 | #define PCIL0_PMM0PCILA 0x8 |
68 | 825bb581 | aurel32 | #define PCIL0_PMM0PCIHA 0xc |
69 | 825bb581 | aurel32 | #define PCIL0_PMM1LA 0x10 |
70 | 825bb581 | aurel32 | #define PCIL0_PMM1MA 0x14 |
71 | 825bb581 | aurel32 | #define PCIL0_PMM1PCILA 0x18 |
72 | 825bb581 | aurel32 | #define PCIL0_PMM1PCIHA 0x1c |
73 | 825bb581 | aurel32 | #define PCIL0_PMM2LA 0x20 |
74 | 825bb581 | aurel32 | #define PCIL0_PMM2MA 0x24 |
75 | 825bb581 | aurel32 | #define PCIL0_PMM2PCILA 0x28 |
76 | 825bb581 | aurel32 | #define PCIL0_PMM2PCIHA 0x2c |
77 | 825bb581 | aurel32 | |
78 | 825bb581 | aurel32 | /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
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79 | 825bb581 | aurel32 | * PLB accesses. */
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80 | 825bb581 | aurel32 | #define PCIL0_PTM1MS 0x30 |
81 | 825bb581 | aurel32 | #define PCIL0_PTM1LA 0x34 |
82 | 825bb581 | aurel32 | #define PCIL0_PTM2MS 0x38 |
83 | 825bb581 | aurel32 | #define PCIL0_PTM2LA 0x3c |
84 | 825bb581 | aurel32 | #define PCI_REG_SIZE 0x40 |
85 | 825bb581 | aurel32 | |
86 | 825bb581 | aurel32 | |
87 | c227f099 | Anthony Liguori | static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr) |
88 | 825bb581 | aurel32 | { |
89 | 825bb581 | aurel32 | PPC4xxPCIState *ppc4xx_pci = opaque; |
90 | 825bb581 | aurel32 | |
91 | 825bb581 | aurel32 | return ppc4xx_pci->pci_state.config_reg;
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92 | 825bb581 | aurel32 | } |
93 | 825bb581 | aurel32 | |
94 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = { |
95 | 825bb581 | aurel32 | &pci4xx_cfgaddr_readl, |
96 | 825bb581 | aurel32 | &pci4xx_cfgaddr_readl, |
97 | 825bb581 | aurel32 | &pci4xx_cfgaddr_readl, |
98 | 825bb581 | aurel32 | }; |
99 | 825bb581 | aurel32 | |
100 | c227f099 | Anthony Liguori | static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr, |
101 | 825bb581 | aurel32 | uint32_t value) |
102 | 825bb581 | aurel32 | { |
103 | 825bb581 | aurel32 | PPC4xxPCIState *ppc4xx_pci = opaque; |
104 | 825bb581 | aurel32 | |
105 | 825bb581 | aurel32 | ppc4xx_pci->pci_state.config_reg = value & ~0x3;
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106 | 825bb581 | aurel32 | } |
107 | 825bb581 | aurel32 | |
108 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = { |
109 | 825bb581 | aurel32 | &pci4xx_cfgaddr_writel, |
110 | 825bb581 | aurel32 | &pci4xx_cfgaddr_writel, |
111 | 825bb581 | aurel32 | &pci4xx_cfgaddr_writel, |
112 | 825bb581 | aurel32 | }; |
113 | 825bb581 | aurel32 | |
114 | c227f099 | Anthony Liguori | static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, |
115 | 825bb581 | aurel32 | uint32_t value) |
116 | 825bb581 | aurel32 | { |
117 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
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118 | 825bb581 | aurel32 | |
119 | 825bb581 | aurel32 | /* We ignore all target attempts at PCI configuration, effectively
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120 | 825bb581 | aurel32 | * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
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121 | 825bb581 | aurel32 | |
122 | 825bb581 | aurel32 | switch (offset) {
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123 | 825bb581 | aurel32 | case PCIL0_PMM0LA:
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124 | 825bb581 | aurel32 | pci->pmm[0].la = value;
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125 | 825bb581 | aurel32 | break;
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126 | 825bb581 | aurel32 | case PCIL0_PMM0MA:
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127 | 825bb581 | aurel32 | pci->pmm[0].ma = value;
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128 | 825bb581 | aurel32 | break;
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129 | 825bb581 | aurel32 | case PCIL0_PMM0PCIHA:
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130 | 825bb581 | aurel32 | pci->pmm[0].pciha = value;
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131 | 825bb581 | aurel32 | break;
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132 | 825bb581 | aurel32 | case PCIL0_PMM0PCILA:
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133 | 825bb581 | aurel32 | pci->pmm[0].pcila = value;
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134 | 825bb581 | aurel32 | break;
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135 | 825bb581 | aurel32 | |
136 | 825bb581 | aurel32 | case PCIL0_PMM1LA:
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137 | 825bb581 | aurel32 | pci->pmm[1].la = value;
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138 | 825bb581 | aurel32 | break;
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139 | 825bb581 | aurel32 | case PCIL0_PMM1MA:
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140 | 825bb581 | aurel32 | pci->pmm[1].ma = value;
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141 | 825bb581 | aurel32 | break;
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142 | 825bb581 | aurel32 | case PCIL0_PMM1PCIHA:
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143 | 825bb581 | aurel32 | pci->pmm[1].pciha = value;
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144 | 825bb581 | aurel32 | break;
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145 | 825bb581 | aurel32 | case PCIL0_PMM1PCILA:
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146 | 825bb581 | aurel32 | pci->pmm[1].pcila = value;
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147 | 825bb581 | aurel32 | break;
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148 | 825bb581 | aurel32 | |
149 | 825bb581 | aurel32 | case PCIL0_PMM2LA:
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150 | 825bb581 | aurel32 | pci->pmm[2].la = value;
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151 | 825bb581 | aurel32 | break;
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152 | 825bb581 | aurel32 | case PCIL0_PMM2MA:
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153 | 825bb581 | aurel32 | pci->pmm[2].ma = value;
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154 | 825bb581 | aurel32 | break;
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155 | 825bb581 | aurel32 | case PCIL0_PMM2PCIHA:
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156 | 825bb581 | aurel32 | pci->pmm[2].pciha = value;
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157 | 825bb581 | aurel32 | break;
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158 | 825bb581 | aurel32 | case PCIL0_PMM2PCILA:
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159 | 825bb581 | aurel32 | pci->pmm[2].pcila = value;
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160 | 825bb581 | aurel32 | break;
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161 | 825bb581 | aurel32 | |
162 | 825bb581 | aurel32 | case PCIL0_PTM1MS:
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163 | 825bb581 | aurel32 | pci->ptm[0].ms = value;
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164 | 825bb581 | aurel32 | break;
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165 | 825bb581 | aurel32 | case PCIL0_PTM1LA:
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166 | 825bb581 | aurel32 | pci->ptm[0].la = value;
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167 | 825bb581 | aurel32 | break;
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168 | 825bb581 | aurel32 | case PCIL0_PTM2MS:
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169 | 825bb581 | aurel32 | pci->ptm[1].ms = value;
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170 | 825bb581 | aurel32 | break;
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171 | 825bb581 | aurel32 | case PCIL0_PTM2LA:
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172 | 825bb581 | aurel32 | pci->ptm[1].la = value;
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173 | 825bb581 | aurel32 | break;
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174 | 825bb581 | aurel32 | |
175 | 825bb581 | aurel32 | default:
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176 | 825bb581 | aurel32 | printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
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177 | 825bb581 | aurel32 | (unsigned long)offset); |
178 | 825bb581 | aurel32 | break;
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179 | 825bb581 | aurel32 | } |
180 | 825bb581 | aurel32 | } |
181 | 825bb581 | aurel32 | |
182 | c227f099 | Anthony Liguori | static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset) |
183 | 825bb581 | aurel32 | { |
184 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
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185 | 825bb581 | aurel32 | uint32_t value; |
186 | 825bb581 | aurel32 | |
187 | 825bb581 | aurel32 | switch (offset) {
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188 | 825bb581 | aurel32 | case PCIL0_PMM0LA:
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189 | 825bb581 | aurel32 | value = pci->pmm[0].la;
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190 | 825bb581 | aurel32 | break;
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191 | 825bb581 | aurel32 | case PCIL0_PMM0MA:
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192 | 825bb581 | aurel32 | value = pci->pmm[0].ma;
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193 | 825bb581 | aurel32 | break;
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194 | 825bb581 | aurel32 | case PCIL0_PMM0PCIHA:
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195 | 825bb581 | aurel32 | value = pci->pmm[0].pciha;
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196 | 825bb581 | aurel32 | break;
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197 | 825bb581 | aurel32 | case PCIL0_PMM0PCILA:
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198 | 825bb581 | aurel32 | value = pci->pmm[0].pcila;
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199 | 825bb581 | aurel32 | break;
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200 | 825bb581 | aurel32 | |
201 | 825bb581 | aurel32 | case PCIL0_PMM1LA:
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202 | 825bb581 | aurel32 | value = pci->pmm[1].la;
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203 | 825bb581 | aurel32 | break;
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204 | 825bb581 | aurel32 | case PCIL0_PMM1MA:
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205 | 825bb581 | aurel32 | value = pci->pmm[1].ma;
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206 | 825bb581 | aurel32 | break;
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207 | 825bb581 | aurel32 | case PCIL0_PMM1PCIHA:
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208 | 825bb581 | aurel32 | value = pci->pmm[1].pciha;
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209 | 825bb581 | aurel32 | break;
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210 | 825bb581 | aurel32 | case PCIL0_PMM1PCILA:
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211 | 825bb581 | aurel32 | value = pci->pmm[1].pcila;
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212 | 825bb581 | aurel32 | break;
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213 | 825bb581 | aurel32 | |
214 | 825bb581 | aurel32 | case PCIL0_PMM2LA:
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215 | 825bb581 | aurel32 | value = pci->pmm[2].la;
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216 | 825bb581 | aurel32 | break;
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217 | 825bb581 | aurel32 | case PCIL0_PMM2MA:
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218 | 825bb581 | aurel32 | value = pci->pmm[2].ma;
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219 | 825bb581 | aurel32 | break;
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220 | 825bb581 | aurel32 | case PCIL0_PMM2PCIHA:
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221 | 825bb581 | aurel32 | value = pci->pmm[2].pciha;
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222 | 825bb581 | aurel32 | break;
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223 | 825bb581 | aurel32 | case PCIL0_PMM2PCILA:
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224 | 825bb581 | aurel32 | value = pci->pmm[2].pcila;
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225 | 825bb581 | aurel32 | break;
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226 | 825bb581 | aurel32 | |
227 | 825bb581 | aurel32 | case PCIL0_PTM1MS:
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228 | 825bb581 | aurel32 | value = pci->ptm[0].ms;
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229 | 825bb581 | aurel32 | break;
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230 | 825bb581 | aurel32 | case PCIL0_PTM1LA:
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231 | 825bb581 | aurel32 | value = pci->ptm[0].la;
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232 | 825bb581 | aurel32 | break;
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233 | 825bb581 | aurel32 | case PCIL0_PTM2MS:
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234 | 825bb581 | aurel32 | value = pci->ptm[1].ms;
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235 | 825bb581 | aurel32 | break;
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236 | 825bb581 | aurel32 | case PCIL0_PTM2LA:
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237 | 825bb581 | aurel32 | value = pci->ptm[1].la;
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238 | 825bb581 | aurel32 | break;
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239 | 825bb581 | aurel32 | |
240 | 825bb581 | aurel32 | default:
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241 | 825bb581 | aurel32 | printf("%s: invalid PCI internal register 0x%lx\n", __func__,
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242 | 825bb581 | aurel32 | (unsigned long)offset); |
243 | 825bb581 | aurel32 | value = 0;
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244 | 825bb581 | aurel32 | } |
245 | 825bb581 | aurel32 | |
246 | 825bb581 | aurel32 | return value;
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247 | 825bb581 | aurel32 | } |
248 | 825bb581 | aurel32 | |
249 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pci_reg_read[] = { |
250 | 825bb581 | aurel32 | &ppc4xx_pci_reg_read4, |
251 | 825bb581 | aurel32 | &ppc4xx_pci_reg_read4, |
252 | 825bb581 | aurel32 | &ppc4xx_pci_reg_read4, |
253 | 825bb581 | aurel32 | }; |
254 | 825bb581 | aurel32 | |
255 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pci_reg_write[] = { |
256 | 825bb581 | aurel32 | &ppc4xx_pci_reg_write4, |
257 | 825bb581 | aurel32 | &ppc4xx_pci_reg_write4, |
258 | 825bb581 | aurel32 | &ppc4xx_pci_reg_write4, |
259 | 825bb581 | aurel32 | }; |
260 | 825bb581 | aurel32 | |
261 | 825bb581 | aurel32 | static void ppc4xx_pci_reset(void *opaque) |
262 | 825bb581 | aurel32 | { |
263 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
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264 | 825bb581 | aurel32 | |
265 | 825bb581 | aurel32 | memset(pci->pmm, 0, sizeof(pci->pmm)); |
266 | 825bb581 | aurel32 | memset(pci->ptm, 0, sizeof(pci->ptm)); |
267 | 825bb581 | aurel32 | } |
268 | 825bb581 | aurel32 | |
269 | 825bb581 | aurel32 | /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
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270 | 825bb581 | aurel32 | * may need further refactoring for other boards. */
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271 | 825bb581 | aurel32 | static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
272 | 825bb581 | aurel32 | { |
273 | 825bb581 | aurel32 | int slot = pci_dev->devfn >> 3; |
274 | 825bb581 | aurel32 | |
275 | 825bb581 | aurel32 | DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
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276 | 825bb581 | aurel32 | pci_dev->devfn, irq_num, slot); |
277 | 825bb581 | aurel32 | |
278 | 825bb581 | aurel32 | return slot - 1; |
279 | 825bb581 | aurel32 | } |
280 | 825bb581 | aurel32 | |
281 | 5d4e84c8 | Juan Quintela | static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) |
282 | 825bb581 | aurel32 | { |
283 | 5d4e84c8 | Juan Quintela | qemu_irq *pci_irqs = opaque; |
284 | 5d4e84c8 | Juan Quintela | |
285 | 825bb581 | aurel32 | DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
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286 | 825bb581 | aurel32 | qemu_set_irq(pci_irqs[irq_num], level); |
287 | 825bb581 | aurel32 | } |
288 | 825bb581 | aurel32 | |
289 | b605f222 | Juan Quintela | static const VMStateDescription vmstate_pci_master_map = { |
290 | b605f222 | Juan Quintela | .name = "pci_master_map",
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291 | b605f222 | Juan Quintela | .version_id = 0,
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292 | b605f222 | Juan Quintela | .minimum_version_id = 0,
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293 | b605f222 | Juan Quintela | .minimum_version_id_old = 0,
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294 | b605f222 | Juan Quintela | .fields = (VMStateField[]) { |
295 | b605f222 | Juan Quintela | VMSTATE_UINT32(la, struct PCIMasterMap),
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296 | b605f222 | Juan Quintela | VMSTATE_UINT32(ma, struct PCIMasterMap),
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297 | b605f222 | Juan Quintela | VMSTATE_UINT32(pcila, struct PCIMasterMap),
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298 | b605f222 | Juan Quintela | VMSTATE_UINT32(pciha, struct PCIMasterMap),
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299 | b605f222 | Juan Quintela | VMSTATE_END_OF_LIST() |
300 | 825bb581 | aurel32 | } |
301 | b605f222 | Juan Quintela | }; |
302 | 825bb581 | aurel32 | |
303 | b605f222 | Juan Quintela | static const VMStateDescription vmstate_pci_target_map = { |
304 | b605f222 | Juan Quintela | .name = "pci_target_map",
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305 | b605f222 | Juan Quintela | .version_id = 0,
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306 | b605f222 | Juan Quintela | .minimum_version_id = 0,
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307 | b605f222 | Juan Quintela | .minimum_version_id_old = 0,
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308 | b605f222 | Juan Quintela | .fields = (VMStateField[]) { |
309 | b605f222 | Juan Quintela | VMSTATE_UINT32(ms, struct PCITargetMap),
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310 | b605f222 | Juan Quintela | VMSTATE_UINT32(la, struct PCITargetMap),
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311 | b605f222 | Juan Quintela | VMSTATE_END_OF_LIST() |
312 | 825bb581 | aurel32 | } |
313 | b605f222 | Juan Quintela | }; |
314 | 825bb581 | aurel32 | |
315 | b605f222 | Juan Quintela | static const VMStateDescription vmstate_ppc4xx_pci = { |
316 | b605f222 | Juan Quintela | .name = "ppc4xx_pci",
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317 | b605f222 | Juan Quintela | .version_id = 1,
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318 | b605f222 | Juan Quintela | .minimum_version_id = 1,
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319 | b605f222 | Juan Quintela | .minimum_version_id_old = 1,
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320 | b605f222 | Juan Quintela | .fields = (VMStateField[]) { |
321 | b605f222 | Juan Quintela | VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPC4xxPCIState), |
322 | b605f222 | Juan Quintela | VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
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323 | b605f222 | Juan Quintela | vmstate_pci_master_map, |
324 | b605f222 | Juan Quintela | struct PCIMasterMap),
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325 | b605f222 | Juan Quintela | VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
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326 | b605f222 | Juan Quintela | vmstate_pci_target_map, |
327 | b605f222 | Juan Quintela | struct PCITargetMap),
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328 | b605f222 | Juan Quintela | VMSTATE_END_OF_LIST() |
329 | 825bb581 | aurel32 | } |
330 | b605f222 | Juan Quintela | }; |
331 | 825bb581 | aurel32 | |
332 | 825bb581 | aurel32 | /* XXX Interrupt acknowledge cycles not supported. */
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333 | 825bb581 | aurel32 | PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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334 | c227f099 | Anthony Liguori | target_phys_addr_t config_space, |
335 | c227f099 | Anthony Liguori | target_phys_addr_t int_ack, |
336 | c227f099 | Anthony Liguori | target_phys_addr_t special_cycle, |
337 | c227f099 | Anthony Liguori | target_phys_addr_t registers) |
338 | 825bb581 | aurel32 | { |
339 | 825bb581 | aurel32 | PPC4xxPCIState *controller; |
340 | 825bb581 | aurel32 | int index;
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341 | 825bb581 | aurel32 | static int ppc4xx_pci_id; |
342 | deb54399 | aliguori | uint8_t *pci_conf; |
343 | 825bb581 | aurel32 | |
344 | 7267c094 | Anthony Liguori | controller = g_malloc0(sizeof(PPC4xxPCIState));
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345 | 825bb581 | aurel32 | |
346 | 02e2da45 | Paul Brook | controller->pci_state.bus = pci_register_bus(NULL, "pci", |
347 | 02e2da45 | Paul Brook | ppc4xx_pci_set_irq, |
348 | 825bb581 | aurel32 | ppc4xx_pci_map_irq, |
349 | 1e39101c | Avi Kivity | pci_irqs, |
350 | 1e39101c | Avi Kivity | get_system_memory(), |
351 | aee97b84 | Avi Kivity | get_system_io(), |
352 | 1e39101c | Avi Kivity | 0, 4); |
353 | 825bb581 | aurel32 | |
354 | 825bb581 | aurel32 | controller->pci_dev = pci_register_device(controller->pci_state.bus, |
355 | 825bb581 | aurel32 | "host bridge", sizeof(PCIDevice), |
356 | 825bb581 | aurel32 | 0, NULL, NULL); |
357 | deb54399 | aliguori | pci_conf = controller->pci_dev->config; |
358 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); |
359 | a770dc7e | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX); |
360 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); |
361 | 825bb581 | aurel32 | |
362 | 825bb581 | aurel32 | /* CFGADDR */
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363 | 1eed09cb | Avi Kivity | index = cpu_register_io_memory(pci4xx_cfgaddr_read, |
364 | 2507c12a | Alexander Graf | pci4xx_cfgaddr_write, controller, |
365 | 0d2a73b3 | Alexander Graf | DEVICE_LITTLE_ENDIAN); |
366 | 825bb581 | aurel32 | if (index < 0) |
367 | 825bb581 | aurel32 | goto free;
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368 | 825bb581 | aurel32 | cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
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369 | 825bb581 | aurel32 | |
370 | 825bb581 | aurel32 | /* CFGDATA */
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371 | d0ed8076 | Avi Kivity | memory_region_init_io(&controller->pci_state.data_mem, |
372 | d0ed8076 | Avi Kivity | &pci_host_data_be_ops, |
373 | d0ed8076 | Avi Kivity | &controller->pci_state, "pci-conf-data", 4); |
374 | d0ed8076 | Avi Kivity | memory_region_add_subregion(get_system_memory(), |
375 | d0ed8076 | Avi Kivity | config_space + PCIC0_CFGDATA, |
376 | d0ed8076 | Avi Kivity | &controller->pci_state.data_mem); |
377 | 825bb581 | aurel32 | |
378 | 825bb581 | aurel32 | /* Internal registers */
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379 | 2507c12a | Alexander Graf | index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller, |
380 | 0d2a73b3 | Alexander Graf | DEVICE_LITTLE_ENDIAN); |
381 | 825bb581 | aurel32 | if (index < 0) |
382 | 825bb581 | aurel32 | goto free;
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383 | 825bb581 | aurel32 | cpu_register_physical_memory(registers, PCI_REG_SIZE, index); |
384 | 825bb581 | aurel32 | |
385 | a08d4367 | Jan Kiszka | qemu_register_reset(ppc4xx_pci_reset, controller); |
386 | 825bb581 | aurel32 | |
387 | 825bb581 | aurel32 | /* XXX load/save code not tested. */
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388 | b605f222 | Juan Quintela | vmstate_register(&controller->pci_dev->qdev, ppc4xx_pci_id++, |
389 | b605f222 | Juan Quintela | &vmstate_ppc4xx_pci, controller); |
390 | 825bb581 | aurel32 | |
391 | 825bb581 | aurel32 | return controller->pci_state.bus;
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392 | 825bb581 | aurel32 | |
393 | 825bb581 | aurel32 | free:
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394 | 825bb581 | aurel32 | printf("%s error\n", __func__);
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395 | 7267c094 | Anthony Liguori | g_free(controller); |
396 | 825bb581 | aurel32 | return NULL; |
397 | 825bb581 | aurel32 | } |