Revision df182043

b/hw/cs4231.c
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typedef struct CSState {
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    SysBusDevice busdev;
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    MemoryRegion iomem;
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    qemu_irq irq;
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    uint32_t regs[CS_REGS];
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    uint8_t dregs[CS_DREGS];
......
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    s->dregs[25] = CS_VER;
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}
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static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
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static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
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                            unsigned size)
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{
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    CSState *s = opaque;
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    uint32_t saddr, ret;
......
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    return ret;
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}
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static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void cs_mem_write(void *opaque, target_phys_addr_t addr,
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                         uint64_t val, unsigned size)
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{
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    CSState *s = opaque;
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    uint32_t saddr;
......
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    }
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}
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static CPUReadMemoryFunc * const cs_mem_read[3] = {
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    cs_mem_readl,
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    cs_mem_readl,
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    cs_mem_readl,
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};
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static CPUWriteMemoryFunc * const cs_mem_write[3] = {
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    cs_mem_writel,
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    cs_mem_writel,
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    cs_mem_writel,
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static const MemoryRegionOps cs_mem_ops = {
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    .read = cs_mem_read,
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    .write = cs_mem_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_cs4231 = {
......
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static int cs4231_init1(SysBusDevice *dev)
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{
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    int io;
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    CSState *s = FROM_SYSBUS(CSState, dev);
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    io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s,
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                                DEVICE_NATIVE_ENDIAN);
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    sysbus_init_mmio(dev, CS_SIZE, io);
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    memory_region_init_io(&s->iomem, &cs_mem_ops, s, "cs4321", CS_SIZE);
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    sysbus_init_mmio_region(dev, &s->iomem);
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    sysbus_init_irq(dev, &s->irq);
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    return 0;

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