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/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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/* MIPS32 4K MMU emulation */
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#ifdef MIPS_USES_R4K_TLB
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static int map_address (CPUState *env, target_ulong *physical, int *prot, |
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target_ulong address, int rw, int access_type) |
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{ |
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tlb_t *tlb; |
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target_ulong tag; |
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uint8_t ASID; |
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int i, n;
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int ret;
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ret = -2;
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tag = (address & 0xFFFFE000);
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ASID = env->CP0_EntryHi & 0x000000FF;
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for (i = 0; i < 16; i++) { |
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tlb = &env->tlb[i]; |
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/* Check ASID, virtual page number & size */
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if ((tlb->G == 1 || tlb->ASID == ASID) && |
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tlb->VPN == tag && address < tlb->end) { |
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/* TLB match */
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n = (address >> 12) & 1; |
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/* Check access rights */
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if ((tlb->V[n] & 2) && (rw == 0 || (tlb->D[n] & 4))) { |
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*physical = tlb->PFN[n] | (address & 0xFFF);
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*prot = PAGE_READ; |
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if (tlb->D[n])
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*prot |= PAGE_WRITE; |
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return 0; |
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} else if (!(tlb->V[n] & 2)) { |
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return -3; |
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} else {
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return -4; |
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} |
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} |
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} |
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return ret;
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} |
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#endif
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int get_physical_address (CPUState *env, target_ulong *physical, int *prot, |
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target_ulong address, int rw, int access_type) |
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{ |
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int user_mode;
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int ret;
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/* User mode can only access useg */
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user_mode = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM) ? 1 : 0; |
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#if 0
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if (logfile) {
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fprintf(logfile, "user mode %d h %08x\n",
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user_mode, env->hflags);
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}
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#endif
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if (user_mode && address > 0x7FFFFFFFUL) |
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return -1; |
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ret = 0;
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if (address < 0x80000000UL) { |
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if (!(env->hflags & MIPS_HFLAG_ERL)) {
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#ifdef MIPS_USES_R4K_TLB
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ret = map_address(env, physical, prot, address, rw, access_type); |
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#else
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*physical = address + 0x40000000UL;
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*prot = PAGE_READ | PAGE_WRITE; |
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#endif
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} else {
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE; |
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} |
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} else if (address < 0xA0000000UL) { |
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/* kseg0 */
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/* XXX: check supervisor mode */
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*physical = address - 0x80000000UL;
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*prot = PAGE_READ | PAGE_WRITE; |
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} else if (address < 0xC0000000UL) { |
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/* kseg1 */
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/* XXX: check supervisor mode */
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*physical = address - 0xA0000000UL;
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*prot = PAGE_READ | PAGE_WRITE; |
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} else if (address < 0xE0000000UL) { |
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/* kseg2 */
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#ifdef MIPS_USES_R4K_TLB
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ret = map_address(env, physical, prot, address, rw, access_type); |
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#else
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE; |
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#endif
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} else {
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/* kseg3 */
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/* XXX: check supervisor mode */
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/* XXX: debug segment is not emulated */
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#ifdef MIPS_USES_R4K_TLB
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ret = map_address(env, physical, prot, address, rw, access_type); |
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#else
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE; |
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#endif
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} |
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#if 0
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if (logfile) {
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fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,
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access_type, *physical, *prot, ret);
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}
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#endif
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return ret;
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} |
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#if defined(CONFIG_USER_ONLY)
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target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
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{ |
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return addr;
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} |
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#else
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target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
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{ |
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target_ulong phys_addr; |
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int prot;
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if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
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return -1; |
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return phys_addr;
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} |
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#endif
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#if !defined(CONFIG_USER_ONLY)
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#define MMUSUFFIX _mmu
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#define GETPC() (__builtin_return_address(0)) |
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#define SHIFT 0 |
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#include "softmmu_template.h" |
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#define SHIFT 1 |
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#include "softmmu_template.h" |
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#define SHIFT 2 |
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#include "softmmu_template.h" |
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#define SHIFT 3 |
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#include "softmmu_template.h" |
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void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) |
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{ |
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TranslationBlock *tb; |
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CPUState *saved_env; |
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unsigned long pc; |
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int ret;
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/* XXX: hack to restore env in all cases, even if not called from
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generated code */
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saved_env = env; |
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env = cpu_single_env; |
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ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
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if (ret) {
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if (retaddr) {
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/* now we have a real cpu fault */
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pc = (unsigned long)retaddr; |
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tb = tb_find_pc(pc); |
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc, NULL);
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} |
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} |
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do_raise_exception_err(env->exception_index, env->error_code); |
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} |
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env = saved_env; |
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} |
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void cpu_mips_init_mmu (CPUState *env)
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{ |
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} |
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int is_user, int is_softmmu) |
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{ |
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target_ulong physical; |
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int prot;
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int exception = 0, error_code = 0; |
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int access_type;
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int ret = 0; |
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if (logfile) {
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cpu_dump_state(env, logfile, fprintf, 0);
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fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
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__func__, env->PC, address, rw, is_user, is_softmmu); |
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} |
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/* data access */
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/* XXX: put correct access by using cpu_restore_state()
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correctly */
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access_type = ACCESS_INT; |
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if (env->user_mode_only) {
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/* user mode only emulation */
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ret = -2;
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goto do_fault;
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} |
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ret = get_physical_address(env, &physical, &prot, |
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address, rw, access_type); |
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if (logfile) {
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fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n",
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__func__, address, ret, physical, prot); |
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} |
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if (ret == 0) { |
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ret = tlb_set_page(env, address & ~0xFFF, physical & ~0xFFF, prot, |
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is_user, is_softmmu); |
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} else if (ret < 0) { |
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do_fault:
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switch (ret) {
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default:
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case -1: |
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/* Reference to kernel address from user mode or supervisor mode */
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/* Reference to supervisor address from user mode */
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if (rw)
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exception = EXCP_AdES; |
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else
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exception = EXCP_AdEL; |
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break;
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case -2: |
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/* No TLB match for a mapped address */
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if (rw)
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exception = EXCP_TLBS; |
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else
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exception = EXCP_TLBL; |
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error_code = 1;
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break;
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case -3: |
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/* TLB match with no valid bit */
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if (rw)
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exception = EXCP_TLBS; |
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else
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exception = EXCP_TLBL; |
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error_code = 0;
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break;
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case -4: |
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/* TLB match but 'D' bit is cleared */
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exception = EXCP_LTLBL; |
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break;
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} |
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/* Raise exception */
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env->CP0_BadVAddr = address; |
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env->CP0_Context = |
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(env->CP0_Context & 0x00000FFF) | (address & 0xFFFFF000); |
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env->CP0_EntryHi = |
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(env->CP0_EntryHi & 0x00000FFF) | (address & 0xFFFFF000); |
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env->exception_index = exception; |
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env->error_code = error_code; |
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ret = 1;
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} |
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return ret;
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} |
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void do_interrupt (CPUState *env)
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{ |
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target_ulong pc, offset; |
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int cause = -1; |
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if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
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fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n",
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__func__, env->PC, env->CP0_EPC, cause, env->exception_index); |
286 |
} |
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if (env->exception_index == EXCP_EXT_INTERRUPT &&
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(env->hflags & MIPS_HFLAG_DM)) |
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env->exception_index = EXCP_DINT; |
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offset = 0x180;
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switch (env->exception_index) {
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case EXCP_DSS:
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env->CP0_Debug |= 1 << CP0DB_DSS;
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/* Debug single step cannot be raised inside a delay slot and
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* resume will always occur on the next instruction
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* (but we assume the pc has always been updated during
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* code translation).
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*/
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env->CP0_DEPC = env->PC; |
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goto enter_debug_mode;
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case EXCP_DINT:
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env->CP0_Debug |= 1 << CP0DB_DINT;
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goto set_DEPC;
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case EXCP_DIB:
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env->CP0_Debug |= 1 << CP0DB_DIB;
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goto set_DEPC;
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case EXCP_DBp:
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env->CP0_Debug |= 1 << CP0DB_DBp;
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goto set_DEPC;
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case EXCP_DDBS:
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env->CP0_Debug |= 1 << CP0DB_DDBS;
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goto set_DEPC;
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case EXCP_DDBL:
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env->CP0_Debug |= 1 << CP0DB_DDBL;
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goto set_DEPC;
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set_DEPC:
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if (env->hflags & MIPS_HFLAG_DS) {
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/* If the exception was raised from a delay slot,
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* come back to the jump
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*/
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env->CP0_DEPC = env->PC - 4;
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} else {
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env->CP0_DEPC = env->PC; |
324 |
} |
325 |
enter_debug_mode:
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env->hflags |= MIPS_HFLAG_DM; |
327 |
/* EJTAG probe trap enable is not implemented... */
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pc = 0xBFC00480;
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break;
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330 |
case EXCP_RESET:
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331 |
#ifdef MIPS_USES_R4K_TLB
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env->CP0_random = MIPS_TLB_NB - 1;
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#endif
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334 |
env->CP0_Wired = 0;
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335 |
env->CP0_Config0 = MIPS_CONFIG0; |
336 |
#if defined (MIPS_CONFIG1)
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env->CP0_Config1 = MIPS_CONFIG1; |
338 |
#endif
|
339 |
#if defined (MIPS_CONFIG2)
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340 |
env->CP0_Config2 = MIPS_CONFIG2; |
341 |
#endif
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342 |
#if defined (MIPS_CONFIG3)
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343 |
env->CP0_Config3 = MIPS_CONFIG3; |
344 |
#endif
|
345 |
env->CP0_WatchLo = 0;
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346 |
env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV); |
347 |
goto set_error_EPC;
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348 |
case EXCP_SRESET:
|
349 |
env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) | |
350 |
(1 << CP0St_SR);
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351 |
env->CP0_WatchLo = 0;
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352 |
goto set_error_EPC;
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353 |
case EXCP_NMI:
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354 |
env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) | |
355 |
(1 << CP0St_NMI);
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356 |
set_error_EPC:
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357 |
env->hflags = MIPS_HFLAG_ERL; |
358 |
if (env->hflags & MIPS_HFLAG_DS) {
|
359 |
/* If the exception was raised from a delay slot,
|
360 |
* come back to the jump
|
361 |
*/
|
362 |
env->CP0_ErrorEPC = env->PC - 4;
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363 |
} else {
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364 |
env->CP0_ErrorEPC = env->PC; |
365 |
} |
366 |
pc = 0xBFC00000;
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367 |
break;
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368 |
case EXCP_MCHECK:
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369 |
cause = 24;
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370 |
goto set_EPC;
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371 |
case EXCP_EXT_INTERRUPT:
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372 |
cause = 0;
|
373 |
if (env->CP0_Cause & (1 << CP0Ca_IV)) |
374 |
offset = 0x200;
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375 |
goto set_EPC;
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376 |
case EXCP_DWATCH:
|
377 |
cause = 23;
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378 |
/* XXX: TODO: manage defered watch exceptions */
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379 |
goto set_EPC;
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380 |
case EXCP_AdEL:
|
381 |
case EXCP_AdES:
|
382 |
cause = 4;
|
383 |
goto set_EPC;
|
384 |
case EXCP_TLBL:
|
385 |
case EXCP_TLBF:
|
386 |
cause = 2;
|
387 |
if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL)) |
388 |
offset = 0x000;
|
389 |
goto set_EPC;
|
390 |
case EXCP_IBE:
|
391 |
cause = 6;
|
392 |
goto set_EPC;
|
393 |
case EXCP_DBE:
|
394 |
cause = 7;
|
395 |
goto set_EPC;
|
396 |
case EXCP_SYSCALL:
|
397 |
cause = 8;
|
398 |
goto set_EPC;
|
399 |
case EXCP_BREAK:
|
400 |
cause = 9;
|
401 |
goto set_EPC;
|
402 |
case EXCP_RI:
|
403 |
cause = 10;
|
404 |
goto set_EPC;
|
405 |
case EXCP_CpU:
|
406 |
cause = 11;
|
407 |
/* XXX: fill in the faulty unit number */
|
408 |
goto set_EPC;
|
409 |
case EXCP_OVERFLOW:
|
410 |
cause = 12;
|
411 |
goto set_EPC;
|
412 |
case EXCP_TRAP:
|
413 |
cause = 13;
|
414 |
goto set_EPC;
|
415 |
case EXCP_LTLBL:
|
416 |
cause = 1;
|
417 |
goto set_EPC;
|
418 |
case EXCP_TLBS:
|
419 |
cause = 3;
|
420 |
set_EPC:
|
421 |
if (env->CP0_Status & (1 << CP0St_BEV)) { |
422 |
pc = 0xBFC00200;
|
423 |
} else {
|
424 |
pc = 0x80000000;
|
425 |
} |
426 |
env->hflags |= MIPS_HFLAG_EXL; |
427 |
pc += offset; |
428 |
env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2); |
429 |
if (env->hflags & MIPS_HFLAG_DS) {
|
430 |
/* If the exception was raised from a delay slot,
|
431 |
* come back to the jump
|
432 |
*/
|
433 |
env->CP0_EPC = env->PC - 4;
|
434 |
env->CP0_Cause |= 0x80000000;
|
435 |
} else {
|
436 |
env->CP0_EPC = env->PC; |
437 |
env->CP0_Cause &= ~0x80000000;
|
438 |
} |
439 |
break;
|
440 |
default:
|
441 |
if (logfile) {
|
442 |
fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
|
443 |
env->exception_index); |
444 |
} |
445 |
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
446 |
exit(1);
|
447 |
} |
448 |
env->PC = pc; |
449 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
450 |
fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
|
451 |
" S %08x C %08x A %08x D %08x\n",
|
452 |
__func__, env->PC, env->CP0_EPC, cause, env->exception_index, |
453 |
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
454 |
env->CP0_DEPC); |
455 |
} |
456 |
env->exception_index = EXCP_NONE; |
457 |
} |