root / hw / openpic.c @ dfb021bc
History | View | Annotate | Download (31.2 kB)
1 | dbda808a | bellard | /*
|
---|---|---|---|
2 | dbda808a | bellard | * OpenPIC emulation
|
3 | 5fafdf24 | ths | *
|
4 | dbda808a | bellard | * Copyright (c) 2004 Jocelyn Mayer
|
5 | 5fafdf24 | ths | *
|
6 | dbda808a | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | dbda808a | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | dbda808a | bellard | * in the Software without restriction, including without limitation the rights
|
9 | dbda808a | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | dbda808a | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | dbda808a | bellard | * furnished to do so, subject to the following conditions:
|
12 | dbda808a | bellard | *
|
13 | dbda808a | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | dbda808a | bellard | * all copies or substantial portions of the Software.
|
15 | dbda808a | bellard | *
|
16 | dbda808a | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | dbda808a | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | dbda808a | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | dbda808a | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | dbda808a | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | dbda808a | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | dbda808a | bellard | * THE SOFTWARE.
|
23 | dbda808a | bellard | */
|
24 | dbda808a | bellard | /*
|
25 | dbda808a | bellard | *
|
26 | dbda808a | bellard | * Based on OpenPic implementations:
|
27 | 67b55785 | blueswir1 | * - Intel GW80314 I/O companion chip developer's manual
|
28 | dbda808a | bellard | * - Motorola MPC8245 & MPC8540 user manuals.
|
29 | dbda808a | bellard | * - Motorola MCP750 (aka Raven) programmer manual.
|
30 | dbda808a | bellard | * - Motorola Harrier programmer manuel
|
31 | dbda808a | bellard | *
|
32 | dbda808a | bellard | * Serial interrupts, as implemented in Raven chipset are not supported yet.
|
33 | 5fafdf24 | ths | *
|
34 | dbda808a | bellard | */
|
35 | 87ecb68b | pbrook | #include "hw.h" |
36 | 87ecb68b | pbrook | #include "ppc_mac.h" |
37 | 87ecb68b | pbrook | #include "pci.h" |
38 | dbda808a | bellard | |
39 | 611493d9 | bellard | //#define DEBUG_OPENPIC
|
40 | dbda808a | bellard | |
41 | dbda808a | bellard | #ifdef DEBUG_OPENPIC
|
42 | dbda808a | bellard | #define DPRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
43 | dbda808a | bellard | #else
|
44 | dbda808a | bellard | #define DPRINTF(fmt, args...) do { } while (0) |
45 | dbda808a | bellard | #endif
|
46 | dbda808a | bellard | #define ERROR(fmr, args...) do { printf("ERROR: " fmr , ##args); } while (0) |
47 | dbda808a | bellard | |
48 | dbda808a | bellard | #define USE_MPCxxx /* Intel model is broken, for now */ |
49 | dbda808a | bellard | |
50 | dbda808a | bellard | #if defined (USE_INTEL_GW80314)
|
51 | dbda808a | bellard | /* Intel GW80314 I/O Companion chip */
|
52 | dbda808a | bellard | |
53 | dbda808a | bellard | #define MAX_CPU 4 |
54 | dbda808a | bellard | #define MAX_IRQ 32 |
55 | dbda808a | bellard | #define MAX_DBL 4 |
56 | dbda808a | bellard | #define MAX_MBX 4 |
57 | dbda808a | bellard | #define MAX_TMR 4 |
58 | dbda808a | bellard | #define VECTOR_BITS 8 |
59 | dbda808a | bellard | #define MAX_IPI 0 |
60 | dbda808a | bellard | |
61 | dbda808a | bellard | #define VID (0x00000000) |
62 | dbda808a | bellard | |
63 | dbda808a | bellard | #define OPENPIC_LITTLE_ENDIAN 1 |
64 | dbda808a | bellard | #define OPENPIC_BIG_ENDIAN 0 |
65 | dbda808a | bellard | |
66 | dbda808a | bellard | #elif defined(USE_MPCxxx)
|
67 | dbda808a | bellard | |
68 | dbda808a | bellard | #define MAX_CPU 2 |
69 | dbda808a | bellard | #define MAX_IRQ 64 |
70 | 611493d9 | bellard | #define EXT_IRQ 48 |
71 | dbda808a | bellard | #define MAX_DBL 0 |
72 | dbda808a | bellard | #define MAX_MBX 0 |
73 | dbda808a | bellard | #define MAX_TMR 4 |
74 | dbda808a | bellard | #define VECTOR_BITS 8 |
75 | dbda808a | bellard | #define MAX_IPI 4 |
76 | dbda808a | bellard | #define VID 0x03 /* MPIC version ID */ |
77 | dbda808a | bellard | #define VENI 0x00000000 /* Vendor ID */ |
78 | dbda808a | bellard | |
79 | dbda808a | bellard | enum {
|
80 | dbda808a | bellard | IRQ_IPVP = 0,
|
81 | dbda808a | bellard | IRQ_IDE, |
82 | dbda808a | bellard | }; |
83 | dbda808a | bellard | |
84 | dbda808a | bellard | #define OPENPIC_LITTLE_ENDIAN 1 |
85 | dbda808a | bellard | #define OPENPIC_BIG_ENDIAN 0 |
86 | dbda808a | bellard | |
87 | dbda808a | bellard | #else
|
88 | dbda808a | bellard | #error "Please select which OpenPic implementation is to be emulated" |
89 | dbda808a | bellard | #endif
|
90 | dbda808a | bellard | |
91 | dbda808a | bellard | #if (OPENPIC_BIG_ENDIAN && !TARGET_WORDS_BIGENDIAN) || \
|
92 | dbda808a | bellard | (OPENPIC_LITTLE_ENDIAN && TARGET_WORDS_BIGENDIAN) |
93 | dbda808a | bellard | #define OPENPIC_SWAP
|
94 | dbda808a | bellard | #endif
|
95 | dbda808a | bellard | |
96 | dbda808a | bellard | /* Interrupt definitions */
|
97 | dbda808a | bellard | #define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */ |
98 | dbda808a | bellard | #define IRQ_ERR (EXT_IRQ + 1) /* Error IRQ */ |
99 | dbda808a | bellard | #define IRQ_TIM0 (EXT_IRQ + 2) /* First timer IRQ */ |
100 | dbda808a | bellard | #if MAX_IPI > 0 |
101 | dbda808a | bellard | #define IRQ_IPI0 (IRQ_TIM0 + MAX_TMR) /* First IPI IRQ */ |
102 | dbda808a | bellard | #define IRQ_DBL0 (IRQ_IPI0 + (MAX_CPU * MAX_IPI)) /* First doorbell IRQ */ |
103 | dbda808a | bellard | #else
|
104 | dbda808a | bellard | #define IRQ_DBL0 (IRQ_TIM0 + MAX_TMR) /* First doorbell IRQ */ |
105 | dbda808a | bellard | #define IRQ_MBX0 (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */ |
106 | dbda808a | bellard | #endif
|
107 | dbda808a | bellard | |
108 | dbda808a | bellard | #define BF_WIDTH(_bits_) \
|
109 | dbda808a | bellard | (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8)) |
110 | dbda808a | bellard | |
111 | dbda808a | bellard | static inline void set_bit (uint32_t *field, int bit) |
112 | dbda808a | bellard | { |
113 | dbda808a | bellard | field[bit >> 5] |= 1 << (bit & 0x1F); |
114 | dbda808a | bellard | } |
115 | dbda808a | bellard | |
116 | dbda808a | bellard | static inline void reset_bit (uint32_t *field, int bit) |
117 | dbda808a | bellard | { |
118 | dbda808a | bellard | field[bit >> 5] &= ~(1 << (bit & 0x1F)); |
119 | dbda808a | bellard | } |
120 | dbda808a | bellard | |
121 | dbda808a | bellard | static inline int test_bit (uint32_t *field, int bit) |
122 | dbda808a | bellard | { |
123 | dbda808a | bellard | return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0; |
124 | dbda808a | bellard | } |
125 | dbda808a | bellard | |
126 | dbda808a | bellard | enum {
|
127 | dbda808a | bellard | IRQ_EXTERNAL = 0x01,
|
128 | dbda808a | bellard | IRQ_INTERNAL = 0x02,
|
129 | dbda808a | bellard | IRQ_TIMER = 0x04,
|
130 | dbda808a | bellard | IRQ_SPECIAL = 0x08,
|
131 | b1d8e52e | blueswir1 | }; |
132 | dbda808a | bellard | |
133 | dbda808a | bellard | typedef struct IRQ_queue_t { |
134 | dbda808a | bellard | uint32_t queue[BF_WIDTH(MAX_IRQ)]; |
135 | dbda808a | bellard | int next;
|
136 | dbda808a | bellard | int priority;
|
137 | dbda808a | bellard | } IRQ_queue_t; |
138 | dbda808a | bellard | |
139 | dbda808a | bellard | typedef struct IRQ_src_t { |
140 | dbda808a | bellard | uint32_t ipvp; /* IRQ vector/priority register */
|
141 | dbda808a | bellard | uint32_t ide; /* IRQ destination register */
|
142 | dbda808a | bellard | int type;
|
143 | dbda808a | bellard | int last_cpu;
|
144 | 611493d9 | bellard | int pending; /* TRUE if IRQ is pending */ |
145 | dbda808a | bellard | } IRQ_src_t; |
146 | dbda808a | bellard | |
147 | dbda808a | bellard | enum IPVP_bits {
|
148 | dbda808a | bellard | IPVP_MASK = 31,
|
149 | dbda808a | bellard | IPVP_ACTIVITY = 30,
|
150 | dbda808a | bellard | IPVP_MODE = 29,
|
151 | dbda808a | bellard | IPVP_POLARITY = 23,
|
152 | dbda808a | bellard | IPVP_SENSE = 22,
|
153 | dbda808a | bellard | }; |
154 | dbda808a | bellard | #define IPVP_PRIORITY_MASK (0x1F << 16) |
155 | 611493d9 | bellard | #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)) |
156 | dbda808a | bellard | #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) |
157 | dbda808a | bellard | #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
|
158 | dbda808a | bellard | |
159 | dbda808a | bellard | typedef struct IRQ_dst_t { |
160 | dbda808a | bellard | uint32_t pctp; /* CPU current task priority */
|
161 | dbda808a | bellard | uint32_t pcsr; /* CPU sensitivity register */
|
162 | dbda808a | bellard | IRQ_queue_t raised; |
163 | dbda808a | bellard | IRQ_queue_t servicing; |
164 | e9df014c | j_mayer | qemu_irq *irqs; |
165 | dbda808a | bellard | } IRQ_dst_t; |
166 | dbda808a | bellard | |
167 | d537cf6c | pbrook | typedef struct openpic_t { |
168 | dbda808a | bellard | PCIDevice pci_dev; |
169 | 91d848eb | bellard | int mem_index;
|
170 | dbda808a | bellard | /* Global registers */
|
171 | dbda808a | bellard | uint32_t frep; /* Feature reporting register */
|
172 | dbda808a | bellard | uint32_t glbc; /* Global configuration register */
|
173 | dbda808a | bellard | uint32_t micr; /* MPIC interrupt configuration register */
|
174 | dbda808a | bellard | uint32_t veni; /* Vendor identification register */
|
175 | e9df014c | j_mayer | uint32_t pint; /* Processor initialization register */
|
176 | dbda808a | bellard | uint32_t spve; /* Spurious vector register */
|
177 | dbda808a | bellard | uint32_t tifr; /* Timer frequency reporting register */
|
178 | dbda808a | bellard | /* Source registers */
|
179 | dbda808a | bellard | IRQ_src_t src[MAX_IRQ]; |
180 | dbda808a | bellard | /* Local registers per output pin */
|
181 | dbda808a | bellard | IRQ_dst_t dst[MAX_CPU]; |
182 | dbda808a | bellard | int nb_cpus;
|
183 | dbda808a | bellard | /* Timer registers */
|
184 | dbda808a | bellard | struct {
|
185 | dbda808a | bellard | uint32_t ticc; /* Global timer current count register */
|
186 | dbda808a | bellard | uint32_t tibc; /* Global timer base count register */
|
187 | dbda808a | bellard | } timers[MAX_TMR]; |
188 | dbda808a | bellard | #if MAX_DBL > 0 |
189 | dbda808a | bellard | /* Doorbell registers */
|
190 | dbda808a | bellard | uint32_t dar; /* Doorbell activate register */
|
191 | dbda808a | bellard | struct {
|
192 | dbda808a | bellard | uint32_t dmr; /* Doorbell messaging register */
|
193 | dbda808a | bellard | } doorbells[MAX_DBL]; |
194 | dbda808a | bellard | #endif
|
195 | dbda808a | bellard | #if MAX_MBX > 0 |
196 | dbda808a | bellard | /* Mailbox registers */
|
197 | dbda808a | bellard | struct {
|
198 | dbda808a | bellard | uint32_t mbr; /* Mailbox register */
|
199 | dbda808a | bellard | } mailboxes[MAX_MAILBOXES]; |
200 | dbda808a | bellard | #endif
|
201 | e9df014c | j_mayer | /* IRQ out is used when in bypass mode (not implemented) */
|
202 | e9df014c | j_mayer | qemu_irq irq_out; |
203 | d537cf6c | pbrook | } openpic_t; |
204 | dbda808a | bellard | |
205 | dbda808a | bellard | static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ) |
206 | dbda808a | bellard | { |
207 | dbda808a | bellard | set_bit(q->queue, n_IRQ); |
208 | dbda808a | bellard | } |
209 | dbda808a | bellard | |
210 | dbda808a | bellard | static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ) |
211 | dbda808a | bellard | { |
212 | dbda808a | bellard | reset_bit(q->queue, n_IRQ); |
213 | dbda808a | bellard | } |
214 | dbda808a | bellard | |
215 | dbda808a | bellard | static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ) |
216 | dbda808a | bellard | { |
217 | dbda808a | bellard | return test_bit(q->queue, n_IRQ);
|
218 | dbda808a | bellard | } |
219 | dbda808a | bellard | |
220 | dbda808a | bellard | static void IRQ_check (openpic_t *opp, IRQ_queue_t *q) |
221 | dbda808a | bellard | { |
222 | dbda808a | bellard | int next, i;
|
223 | dbda808a | bellard | int priority;
|
224 | dbda808a | bellard | |
225 | dbda808a | bellard | next = -1;
|
226 | dbda808a | bellard | priority = -1;
|
227 | dbda808a | bellard | for (i = 0; i < MAX_IRQ; i++) { |
228 | dbda808a | bellard | if (IRQ_testbit(q, i)) {
|
229 | 5fafdf24 | ths | DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
|
230 | 611493d9 | bellard | i, IPVP_PRIORITY(opp->src[i].ipvp), priority); |
231 | dbda808a | bellard | if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
|
232 | dbda808a | bellard | next = i; |
233 | dbda808a | bellard | priority = IPVP_PRIORITY(opp->src[i].ipvp); |
234 | dbda808a | bellard | } |
235 | dbda808a | bellard | } |
236 | dbda808a | bellard | } |
237 | dbda808a | bellard | q->next = next; |
238 | dbda808a | bellard | q->priority = priority; |
239 | dbda808a | bellard | } |
240 | dbda808a | bellard | |
241 | dbda808a | bellard | static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q) |
242 | dbda808a | bellard | { |
243 | dbda808a | bellard | if (q->next == -1) { |
244 | 611493d9 | bellard | /* XXX: optimize */
|
245 | dbda808a | bellard | IRQ_check(opp, q); |
246 | dbda808a | bellard | } |
247 | dbda808a | bellard | |
248 | dbda808a | bellard | return q->next;
|
249 | dbda808a | bellard | } |
250 | dbda808a | bellard | |
251 | dbda808a | bellard | static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ) |
252 | dbda808a | bellard | { |
253 | dbda808a | bellard | IRQ_dst_t *dst; |
254 | dbda808a | bellard | IRQ_src_t *src; |
255 | dbda808a | bellard | int priority;
|
256 | dbda808a | bellard | |
257 | dbda808a | bellard | dst = &opp->dst[n_CPU]; |
258 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
259 | dbda808a | bellard | priority = IPVP_PRIORITY(src->ipvp); |
260 | dbda808a | bellard | if (priority <= dst->pctp) {
|
261 | dbda808a | bellard | /* Too low priority */
|
262 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
|
263 | e9df014c | j_mayer | __func__, n_IRQ, n_CPU); |
264 | dbda808a | bellard | return;
|
265 | dbda808a | bellard | } |
266 | dbda808a | bellard | if (IRQ_testbit(&dst->raised, n_IRQ)) {
|
267 | dbda808a | bellard | /* Interrupt miss */
|
268 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d was missed on CPU %d\n",
|
269 | e9df014c | j_mayer | __func__, n_IRQ, n_CPU); |
270 | dbda808a | bellard | return;
|
271 | dbda808a | bellard | } |
272 | dbda808a | bellard | set_bit(&src->ipvp, IPVP_ACTIVITY); |
273 | dbda808a | bellard | IRQ_setbit(&dst->raised, n_IRQ); |
274 | e9df014c | j_mayer | if (priority < dst->raised.priority) {
|
275 | e9df014c | j_mayer | /* An higher priority IRQ is already raised */
|
276 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
|
277 | e9df014c | j_mayer | __func__, n_IRQ, dst->raised.next, n_CPU); |
278 | e9df014c | j_mayer | return;
|
279 | e9df014c | j_mayer | } |
280 | e9df014c | j_mayer | IRQ_get_next(opp, &dst->raised); |
281 | e9df014c | j_mayer | if (IRQ_get_next(opp, &dst->servicing) != -1 && |
282 | 24865167 | aliguori | priority <= dst->servicing.priority) { |
283 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
|
284 | e9df014c | j_mayer | __func__, n_IRQ, dst->servicing.next, n_CPU); |
285 | e9df014c | j_mayer | /* Already servicing a higher priority IRQ */
|
286 | e9df014c | j_mayer | return;
|
287 | dbda808a | bellard | } |
288 | e9df014c | j_mayer | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ);
|
289 | e9df014c | j_mayer | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]); |
290 | dbda808a | bellard | } |
291 | dbda808a | bellard | |
292 | 611493d9 | bellard | /* update pic state because registers for n_IRQ have changed value */
|
293 | 611493d9 | bellard | static void openpic_update_irq(openpic_t *opp, int n_IRQ) |
294 | dbda808a | bellard | { |
295 | dbda808a | bellard | IRQ_src_t *src; |
296 | dbda808a | bellard | int i;
|
297 | dbda808a | bellard | |
298 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
299 | 611493d9 | bellard | |
300 | 611493d9 | bellard | if (!src->pending) {
|
301 | 611493d9 | bellard | /* no irq pending */
|
302 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
|
303 | 611493d9 | bellard | return;
|
304 | 611493d9 | bellard | } |
305 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_MASK)) {
|
306 | dbda808a | bellard | /* Interrupt source is disabled */
|
307 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
|
308 | dbda808a | bellard | return;
|
309 | dbda808a | bellard | } |
310 | dbda808a | bellard | if (IPVP_PRIORITY(src->ipvp) == 0) { |
311 | dbda808a | bellard | /* Priority set to zero */
|
312 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ);
|
313 | dbda808a | bellard | return;
|
314 | dbda808a | bellard | } |
315 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
|
316 | 611493d9 | bellard | /* IRQ already active */
|
317 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ);
|
318 | 611493d9 | bellard | return;
|
319 | 611493d9 | bellard | } |
320 | dbda808a | bellard | if (src->ide == 0x00000000) { |
321 | dbda808a | bellard | /* No target */
|
322 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
|
323 | dbda808a | bellard | return;
|
324 | dbda808a | bellard | } |
325 | 611493d9 | bellard | |
326 | e9df014c | j_mayer | if (src->ide == (1 << src->last_cpu)) { |
327 | e9df014c | j_mayer | /* Only one CPU is allowed to receive this IRQ */
|
328 | e9df014c | j_mayer | IRQ_local_pipe(opp, src->last_cpu, n_IRQ); |
329 | e9df014c | j_mayer | } else if (!test_bit(&src->ipvp, IPVP_MODE)) { |
330 | 611493d9 | bellard | /* Directed delivery mode */
|
331 | 611493d9 | bellard | for (i = 0; i < opp->nb_cpus; i++) { |
332 | 611493d9 | bellard | if (test_bit(&src->ide, i))
|
333 | 611493d9 | bellard | IRQ_local_pipe(opp, i, n_IRQ); |
334 | 611493d9 | bellard | } |
335 | dbda808a | bellard | } else {
|
336 | 611493d9 | bellard | /* Distributed delivery mode */
|
337 | e9df014c | j_mayer | for (i = src->last_cpu + 1; i != src->last_cpu; i++) { |
338 | e9df014c | j_mayer | if (i == opp->nb_cpus)
|
339 | 611493d9 | bellard | i = 0;
|
340 | 611493d9 | bellard | if (test_bit(&src->ide, i)) {
|
341 | 611493d9 | bellard | IRQ_local_pipe(opp, i, n_IRQ); |
342 | 611493d9 | bellard | src->last_cpu = i; |
343 | 611493d9 | bellard | break;
|
344 | 611493d9 | bellard | } |
345 | 611493d9 | bellard | } |
346 | 611493d9 | bellard | } |
347 | 611493d9 | bellard | } |
348 | 611493d9 | bellard | |
349 | d537cf6c | pbrook | static void openpic_set_irq(void *opaque, int n_IRQ, int level) |
350 | 611493d9 | bellard | { |
351 | 54fa5af5 | bellard | openpic_t *opp = opaque; |
352 | 611493d9 | bellard | IRQ_src_t *src; |
353 | 611493d9 | bellard | |
354 | 611493d9 | bellard | src = &opp->src[n_IRQ]; |
355 | 5fafdf24 | ths | DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
|
356 | 611493d9 | bellard | n_IRQ, level, src->ipvp); |
357 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_SENSE)) {
|
358 | 611493d9 | bellard | /* level-sensitive irq */
|
359 | 611493d9 | bellard | src->pending = level; |
360 | 611493d9 | bellard | if (!level)
|
361 | 611493d9 | bellard | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
362 | 611493d9 | bellard | } else {
|
363 | 611493d9 | bellard | /* edge-sensitive irq */
|
364 | 611493d9 | bellard | if (level)
|
365 | 611493d9 | bellard | src->pending = 1;
|
366 | dbda808a | bellard | } |
367 | 611493d9 | bellard | openpic_update_irq(opp, n_IRQ); |
368 | dbda808a | bellard | } |
369 | dbda808a | bellard | |
370 | 67b55785 | blueswir1 | static void openpic_reset (void *opaque) |
371 | dbda808a | bellard | { |
372 | 67b55785 | blueswir1 | openpic_t *opp = (openpic_t *)opaque; |
373 | dbda808a | bellard | int i;
|
374 | dbda808a | bellard | |
375 | dbda808a | bellard | opp->glbc = 0x80000000;
|
376 | f8407028 | bellard | /* Initialise controller registers */
|
377 | dbda808a | bellard | opp->frep = ((EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID; |
378 | dbda808a | bellard | opp->veni = VENI; |
379 | e9df014c | j_mayer | opp->pint = 0x00000000;
|
380 | dbda808a | bellard | opp->spve = 0x000000FF;
|
381 | dbda808a | bellard | opp->tifr = 0x003F7A00;
|
382 | dbda808a | bellard | /* ? */
|
383 | dbda808a | bellard | opp->micr = 0x00000000;
|
384 | dbda808a | bellard | /* Initialise IRQ sources */
|
385 | dbda808a | bellard | for (i = 0; i < MAX_IRQ; i++) { |
386 | dbda808a | bellard | opp->src[i].ipvp = 0xA0000000;
|
387 | dbda808a | bellard | opp->src[i].ide = 0x00000000;
|
388 | dbda808a | bellard | } |
389 | dbda808a | bellard | /* Initialise IRQ destinations */
|
390 | e9df014c | j_mayer | for (i = 0; i < MAX_CPU; i++) { |
391 | dbda808a | bellard | opp->dst[i].pctp = 0x0000000F;
|
392 | dbda808a | bellard | opp->dst[i].pcsr = 0x00000000;
|
393 | dbda808a | bellard | memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
394 | dbda808a | bellard | memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
395 | dbda808a | bellard | } |
396 | dbda808a | bellard | /* Initialise timers */
|
397 | dbda808a | bellard | for (i = 0; i < MAX_TMR; i++) { |
398 | dbda808a | bellard | opp->timers[i].ticc = 0x00000000;
|
399 | dbda808a | bellard | opp->timers[i].tibc = 0x80000000;
|
400 | dbda808a | bellard | } |
401 | dbda808a | bellard | /* Initialise doorbells */
|
402 | dbda808a | bellard | #if MAX_DBL > 0 |
403 | dbda808a | bellard | opp->dar = 0x00000000;
|
404 | dbda808a | bellard | for (i = 0; i < MAX_DBL; i++) { |
405 | dbda808a | bellard | opp->doorbells[i].dmr = 0x00000000;
|
406 | dbda808a | bellard | } |
407 | dbda808a | bellard | #endif
|
408 | dbda808a | bellard | /* Initialise mailboxes */
|
409 | dbda808a | bellard | #if MAX_MBX > 0 |
410 | dbda808a | bellard | for (i = 0; i < MAX_MBX; i++) { /* ? */ |
411 | dbda808a | bellard | opp->mailboxes[i].mbr = 0x00000000;
|
412 | dbda808a | bellard | } |
413 | dbda808a | bellard | #endif
|
414 | dbda808a | bellard | /* Go out of RESET state */
|
415 | dbda808a | bellard | opp->glbc = 0x00000000;
|
416 | dbda808a | bellard | } |
417 | dbda808a | bellard | |
418 | dbda808a | bellard | static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg) |
419 | dbda808a | bellard | { |
420 | dbda808a | bellard | uint32_t retval; |
421 | dbda808a | bellard | |
422 | dbda808a | bellard | switch (reg) {
|
423 | dbda808a | bellard | case IRQ_IPVP:
|
424 | dbda808a | bellard | retval = opp->src[n_IRQ].ipvp; |
425 | dbda808a | bellard | break;
|
426 | dbda808a | bellard | case IRQ_IDE:
|
427 | dbda808a | bellard | retval = opp->src[n_IRQ].ide; |
428 | dbda808a | bellard | break;
|
429 | dbda808a | bellard | } |
430 | dbda808a | bellard | |
431 | dbda808a | bellard | return retval;
|
432 | dbda808a | bellard | } |
433 | dbda808a | bellard | |
434 | dbda808a | bellard | static inline void write_IRQreg (openpic_t *opp, int n_IRQ, |
435 | dbda808a | bellard | uint32_t reg, uint32_t val) |
436 | dbda808a | bellard | { |
437 | dbda808a | bellard | uint32_t tmp; |
438 | dbda808a | bellard | |
439 | dbda808a | bellard | switch (reg) {
|
440 | dbda808a | bellard | case IRQ_IPVP:
|
441 | 611493d9 | bellard | /* NOTE: not fully accurate for special IRQs, but simple and
|
442 | 611493d9 | bellard | sufficient */
|
443 | 611493d9 | bellard | /* ACTIVITY bit is read-only */
|
444 | 5fafdf24 | ths | opp->src[n_IRQ].ipvp = |
445 | 611493d9 | bellard | (opp->src[n_IRQ].ipvp & 0x40000000) |
|
446 | 611493d9 | bellard | (val & 0x800F00FF);
|
447 | 611493d9 | bellard | openpic_update_irq(opp, n_IRQ); |
448 | 5fafdf24 | ths | DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
|
449 | 611493d9 | bellard | n_IRQ, val, opp->src[n_IRQ].ipvp); |
450 | dbda808a | bellard | break;
|
451 | dbda808a | bellard | case IRQ_IDE:
|
452 | dbda808a | bellard | tmp = val & 0xC0000000;
|
453 | dbda808a | bellard | tmp |= val & ((1 << MAX_CPU) - 1); |
454 | dbda808a | bellard | opp->src[n_IRQ].ide = tmp; |
455 | dbda808a | bellard | DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
|
456 | dbda808a | bellard | break;
|
457 | dbda808a | bellard | } |
458 | dbda808a | bellard | } |
459 | dbda808a | bellard | |
460 | dbda808a | bellard | #if 0 // Code provision for Intel model
|
461 | dbda808a | bellard | #if MAX_DBL > 0
|
462 | dbda808a | bellard | static uint32_t read_doorbell_register (openpic_t *opp,
|
463 | dbda808a | bellard | int n_dbl, uint32_t offset)
|
464 | dbda808a | bellard | {
|
465 | dbda808a | bellard | uint32_t retval;
|
466 | dbda808a | bellard | |
467 | dbda808a | bellard | switch (offset) {
|
468 | dbda808a | bellard | case DBL_IPVP_OFFSET:
|
469 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
|
470 | dbda808a | bellard | break;
|
471 | dbda808a | bellard | case DBL_IDE_OFFSET:
|
472 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
|
473 | dbda808a | bellard | break;
|
474 | dbda808a | bellard | case DBL_DMR_OFFSET:
|
475 | dbda808a | bellard | retval = opp->doorbells[n_dbl].dmr;
|
476 | dbda808a | bellard | break;
|
477 | dbda808a | bellard | }
|
478 | dbda808a | bellard | |
479 | dbda808a | bellard | return retval;
|
480 | dbda808a | bellard | }
|
481 | 3b46e624 | ths | |
482 | dbda808a | bellard | static void write_doorbell_register (penpic_t *opp, int n_dbl,
|
483 | dbda808a | bellard | uint32_t offset, uint32_t value)
|
484 | dbda808a | bellard | {
|
485 | dbda808a | bellard | switch (offset) {
|
486 | dbda808a | bellard | case DBL_IVPR_OFFSET:
|
487 | dbda808a | bellard | write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
|
488 | dbda808a | bellard | break;
|
489 | dbda808a | bellard | case DBL_IDE_OFFSET:
|
490 | dbda808a | bellard | write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
|
491 | dbda808a | bellard | break;
|
492 | dbda808a | bellard | case DBL_DMR_OFFSET:
|
493 | dbda808a | bellard | opp->doorbells[n_dbl].dmr = value;
|
494 | dbda808a | bellard | break;
|
495 | dbda808a | bellard | }
|
496 | dbda808a | bellard | }
|
497 | dbda808a | bellard | #endif
|
498 | dbda808a | bellard | |
499 | dbda808a | bellard | #if MAX_MBX > 0 |
500 | dbda808a | bellard | static uint32_t read_mailbox_register (openpic_t *opp,
|
501 | dbda808a | bellard | int n_mbx, uint32_t offset)
|
502 | dbda808a | bellard | { |
503 | dbda808a | bellard | uint32_t retval; |
504 | dbda808a | bellard | |
505 | dbda808a | bellard | switch (offset) {
|
506 | dbda808a | bellard | case MBX_MBR_OFFSET:
|
507 | dbda808a | bellard | retval = opp->mailboxes[n_mbx].mbr; |
508 | dbda808a | bellard | break;
|
509 | dbda808a | bellard | case MBX_IVPR_OFFSET:
|
510 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP); |
511 | dbda808a | bellard | break;
|
512 | dbda808a | bellard | case MBX_DMR_OFFSET:
|
513 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE); |
514 | dbda808a | bellard | break;
|
515 | dbda808a | bellard | } |
516 | dbda808a | bellard | |
517 | dbda808a | bellard | return retval;
|
518 | dbda808a | bellard | } |
519 | dbda808a | bellard | |
520 | dbda808a | bellard | static void write_mailbox_register (openpic_t *opp, int n_mbx, |
521 | dbda808a | bellard | uint32_t address, uint32_t value) |
522 | dbda808a | bellard | { |
523 | dbda808a | bellard | switch (offset) {
|
524 | dbda808a | bellard | case MBX_MBR_OFFSET:
|
525 | dbda808a | bellard | opp->mailboxes[n_mbx].mbr = value; |
526 | dbda808a | bellard | break;
|
527 | dbda808a | bellard | case MBX_IVPR_OFFSET:
|
528 | dbda808a | bellard | write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value); |
529 | dbda808a | bellard | break;
|
530 | dbda808a | bellard | case MBX_DMR_OFFSET:
|
531 | dbda808a | bellard | write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value); |
532 | dbda808a | bellard | break;
|
533 | dbda808a | bellard | } |
534 | dbda808a | bellard | } |
535 | dbda808a | bellard | #endif
|
536 | dbda808a | bellard | #endif /* 0 : Code provision for Intel model */ |
537 | dbda808a | bellard | |
538 | dbda808a | bellard | static void openpic_gbl_write (void *opaque, uint32_t addr, uint32_t val) |
539 | dbda808a | bellard | { |
540 | dbda808a | bellard | openpic_t *opp = opaque; |
541 | e9df014c | j_mayer | IRQ_dst_t *dst; |
542 | e9df014c | j_mayer | int idx;
|
543 | dbda808a | bellard | |
544 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
545 | dbda808a | bellard | if (addr & 0xF) |
546 | dbda808a | bellard | return;
|
547 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
548 | dbda808a | bellard | val = bswap32(val); |
549 | dbda808a | bellard | #endif
|
550 | dbda808a | bellard | addr &= 0xFF;
|
551 | dbda808a | bellard | switch (addr) {
|
552 | dbda808a | bellard | case 0x00: /* FREP */ |
553 | dbda808a | bellard | break;
|
554 | dbda808a | bellard | case 0x20: /* GLBC */ |
555 | dbda808a | bellard | if (val & 0x80000000) |
556 | dbda808a | bellard | openpic_reset(opp); |
557 | dbda808a | bellard | opp->glbc = val & ~0x80000000;
|
558 | dbda808a | bellard | break;
|
559 | dbda808a | bellard | case 0x80: /* VENI */ |
560 | dbda808a | bellard | break;
|
561 | dbda808a | bellard | case 0x90: /* PINT */ |
562 | e9df014c | j_mayer | for (idx = 0; idx < opp->nb_cpus; idx++) { |
563 | e9df014c | j_mayer | if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) { |
564 | e9df014c | j_mayer | DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
|
565 | e9df014c | j_mayer | dst = &opp->dst[idx]; |
566 | e9df014c | j_mayer | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); |
567 | e9df014c | j_mayer | } else if (!(val & (1 << idx)) && (opp->pint & (1 << idx))) { |
568 | e9df014c | j_mayer | DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
|
569 | e9df014c | j_mayer | dst = &opp->dst[idx]; |
570 | e9df014c | j_mayer | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); |
571 | e9df014c | j_mayer | } |
572 | dbda808a | bellard | } |
573 | e9df014c | j_mayer | opp->pint = val; |
574 | dbda808a | bellard | break;
|
575 | dbda808a | bellard | #if MAX_IPI > 0 |
576 | dbda808a | bellard | case 0xA0: /* IPI_IPVP */ |
577 | dbda808a | bellard | case 0xB0: |
578 | dbda808a | bellard | case 0xC0: |
579 | dbda808a | bellard | case 0xD0: |
580 | dbda808a | bellard | { |
581 | dbda808a | bellard | int idx;
|
582 | dbda808a | bellard | idx = (addr - 0xA0) >> 4; |
583 | dbda808a | bellard | write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP, val); |
584 | dbda808a | bellard | } |
585 | dbda808a | bellard | break;
|
586 | dbda808a | bellard | #endif
|
587 | dbda808a | bellard | case 0xE0: /* SPVE */ |
588 | dbda808a | bellard | opp->spve = val & 0x000000FF;
|
589 | dbda808a | bellard | break;
|
590 | dbda808a | bellard | case 0xF0: /* TIFR */ |
591 | dbda808a | bellard | opp->tifr = val; |
592 | dbda808a | bellard | break;
|
593 | dbda808a | bellard | default:
|
594 | dbda808a | bellard | break;
|
595 | dbda808a | bellard | } |
596 | dbda808a | bellard | } |
597 | dbda808a | bellard | |
598 | dbda808a | bellard | static uint32_t openpic_gbl_read (void *opaque, uint32_t addr) |
599 | dbda808a | bellard | { |
600 | dbda808a | bellard | openpic_t *opp = opaque; |
601 | dbda808a | bellard | uint32_t retval; |
602 | dbda808a | bellard | |
603 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
604 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
605 | dbda808a | bellard | if (addr & 0xF) |
606 | dbda808a | bellard | return retval;
|
607 | dbda808a | bellard | addr &= 0xFF;
|
608 | dbda808a | bellard | switch (addr) {
|
609 | dbda808a | bellard | case 0x00: /* FREP */ |
610 | dbda808a | bellard | retval = opp->frep; |
611 | dbda808a | bellard | break;
|
612 | dbda808a | bellard | case 0x20: /* GLBC */ |
613 | dbda808a | bellard | retval = opp->glbc; |
614 | dbda808a | bellard | break;
|
615 | dbda808a | bellard | case 0x80: /* VENI */ |
616 | dbda808a | bellard | retval = opp->veni; |
617 | dbda808a | bellard | break;
|
618 | dbda808a | bellard | case 0x90: /* PINT */ |
619 | dbda808a | bellard | retval = 0x00000000;
|
620 | dbda808a | bellard | break;
|
621 | dbda808a | bellard | #if MAX_IPI > 0 |
622 | dbda808a | bellard | case 0xA0: /* IPI_IPVP */ |
623 | dbda808a | bellard | case 0xB0: |
624 | dbda808a | bellard | case 0xC0: |
625 | dbda808a | bellard | case 0xD0: |
626 | dbda808a | bellard | { |
627 | dbda808a | bellard | int idx;
|
628 | dbda808a | bellard | idx = (addr - 0xA0) >> 4; |
629 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP); |
630 | dbda808a | bellard | } |
631 | dbda808a | bellard | break;
|
632 | dbda808a | bellard | #endif
|
633 | dbda808a | bellard | case 0xE0: /* SPVE */ |
634 | dbda808a | bellard | retval = opp->spve; |
635 | dbda808a | bellard | break;
|
636 | dbda808a | bellard | case 0xF0: /* TIFR */ |
637 | dbda808a | bellard | retval = opp->tifr; |
638 | dbda808a | bellard | break;
|
639 | dbda808a | bellard | default:
|
640 | dbda808a | bellard | break;
|
641 | dbda808a | bellard | } |
642 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
643 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
644 | dbda808a | bellard | retval = bswap32(retval); |
645 | dbda808a | bellard | #endif
|
646 | dbda808a | bellard | |
647 | dbda808a | bellard | return retval;
|
648 | dbda808a | bellard | } |
649 | dbda808a | bellard | |
650 | dbda808a | bellard | static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) |
651 | dbda808a | bellard | { |
652 | dbda808a | bellard | openpic_t *opp = opaque; |
653 | dbda808a | bellard | int idx;
|
654 | dbda808a | bellard | |
655 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
656 | dbda808a | bellard | if (addr & 0xF) |
657 | dbda808a | bellard | return;
|
658 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
659 | dbda808a | bellard | val = bswap32(val); |
660 | dbda808a | bellard | #endif
|
661 | dbda808a | bellard | addr -= 0x1100;
|
662 | dbda808a | bellard | addr &= 0xFFFF;
|
663 | dbda808a | bellard | idx = (addr & 0xFFF0) >> 6; |
664 | dbda808a | bellard | addr = addr & 0x30;
|
665 | dbda808a | bellard | switch (addr) {
|
666 | dbda808a | bellard | case 0x00: /* TICC */ |
667 | dbda808a | bellard | break;
|
668 | dbda808a | bellard | case 0x10: /* TIBC */ |
669 | dbda808a | bellard | if ((opp->timers[idx].ticc & 0x80000000) != 0 && |
670 | 8adbc566 | bellard | (val & 0x80000000) == 0 && |
671 | dbda808a | bellard | (opp->timers[idx].tibc & 0x80000000) != 0) |
672 | dbda808a | bellard | opp->timers[idx].ticc &= ~0x80000000;
|
673 | dbda808a | bellard | opp->timers[idx].tibc = val; |
674 | dbda808a | bellard | break;
|
675 | dbda808a | bellard | case 0x20: /* TIVP */ |
676 | dbda808a | bellard | write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP, val); |
677 | dbda808a | bellard | break;
|
678 | dbda808a | bellard | case 0x30: /* TIDE */ |
679 | dbda808a | bellard | write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE, val); |
680 | dbda808a | bellard | break;
|
681 | dbda808a | bellard | } |
682 | dbda808a | bellard | } |
683 | dbda808a | bellard | |
684 | dbda808a | bellard | static uint32_t openpic_timer_read (void *opaque, uint32_t addr) |
685 | dbda808a | bellard | { |
686 | dbda808a | bellard | openpic_t *opp = opaque; |
687 | dbda808a | bellard | uint32_t retval; |
688 | dbda808a | bellard | int idx;
|
689 | dbda808a | bellard | |
690 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
691 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
692 | dbda808a | bellard | if (addr & 0xF) |
693 | dbda808a | bellard | return retval;
|
694 | dbda808a | bellard | addr -= 0x1100;
|
695 | dbda808a | bellard | addr &= 0xFFFF;
|
696 | dbda808a | bellard | idx = (addr & 0xFFF0) >> 6; |
697 | dbda808a | bellard | addr = addr & 0x30;
|
698 | dbda808a | bellard | switch (addr) {
|
699 | dbda808a | bellard | case 0x00: /* TICC */ |
700 | dbda808a | bellard | retval = opp->timers[idx].ticc; |
701 | dbda808a | bellard | break;
|
702 | dbda808a | bellard | case 0x10: /* TIBC */ |
703 | dbda808a | bellard | retval = opp->timers[idx].tibc; |
704 | dbda808a | bellard | break;
|
705 | dbda808a | bellard | case 0x20: /* TIPV */ |
706 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP); |
707 | dbda808a | bellard | break;
|
708 | dbda808a | bellard | case 0x30: /* TIDE */ |
709 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE); |
710 | dbda808a | bellard | break;
|
711 | dbda808a | bellard | } |
712 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
713 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
714 | dbda808a | bellard | retval = bswap32(retval); |
715 | dbda808a | bellard | #endif
|
716 | dbda808a | bellard | |
717 | dbda808a | bellard | return retval;
|
718 | dbda808a | bellard | } |
719 | dbda808a | bellard | |
720 | dbda808a | bellard | static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) |
721 | dbda808a | bellard | { |
722 | dbda808a | bellard | openpic_t *opp = opaque; |
723 | dbda808a | bellard | int idx;
|
724 | dbda808a | bellard | |
725 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
726 | dbda808a | bellard | if (addr & 0xF) |
727 | dbda808a | bellard | return;
|
728 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
729 | dbda808a | bellard | val = tswap32(val); |
730 | dbda808a | bellard | #endif
|
731 | dbda808a | bellard | addr = addr & 0xFFF0;
|
732 | dbda808a | bellard | idx = addr >> 5;
|
733 | dbda808a | bellard | if (addr & 0x10) { |
734 | dbda808a | bellard | /* EXDE / IFEDE / IEEDE */
|
735 | dbda808a | bellard | write_IRQreg(opp, idx, IRQ_IDE, val); |
736 | dbda808a | bellard | } else {
|
737 | dbda808a | bellard | /* EXVP / IFEVP / IEEVP */
|
738 | dbda808a | bellard | write_IRQreg(opp, idx, IRQ_IPVP, val); |
739 | dbda808a | bellard | } |
740 | dbda808a | bellard | } |
741 | dbda808a | bellard | |
742 | dbda808a | bellard | static uint32_t openpic_src_read (void *opaque, uint32_t addr) |
743 | dbda808a | bellard | { |
744 | dbda808a | bellard | openpic_t *opp = opaque; |
745 | dbda808a | bellard | uint32_t retval; |
746 | dbda808a | bellard | int idx;
|
747 | dbda808a | bellard | |
748 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
749 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
750 | dbda808a | bellard | if (addr & 0xF) |
751 | dbda808a | bellard | return retval;
|
752 | dbda808a | bellard | addr = addr & 0xFFF0;
|
753 | dbda808a | bellard | idx = addr >> 5;
|
754 | dbda808a | bellard | if (addr & 0x10) { |
755 | dbda808a | bellard | /* EXDE / IFEDE / IEEDE */
|
756 | dbda808a | bellard | retval = read_IRQreg(opp, idx, IRQ_IDE); |
757 | dbda808a | bellard | } else {
|
758 | dbda808a | bellard | /* EXVP / IFEVP / IEEVP */
|
759 | dbda808a | bellard | retval = read_IRQreg(opp, idx, IRQ_IPVP); |
760 | dbda808a | bellard | } |
761 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
762 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
763 | dbda808a | bellard | retval = tswap32(retval); |
764 | dbda808a | bellard | #endif
|
765 | dbda808a | bellard | |
766 | dbda808a | bellard | return retval;
|
767 | dbda808a | bellard | } |
768 | dbda808a | bellard | |
769 | dbda808a | bellard | static void openpic_cpu_write (void *opaque, uint32_t addr, uint32_t val) |
770 | dbda808a | bellard | { |
771 | dbda808a | bellard | openpic_t *opp = opaque; |
772 | dbda808a | bellard | IRQ_src_t *src; |
773 | dbda808a | bellard | IRQ_dst_t *dst; |
774 | e9df014c | j_mayer | int idx, s_IRQ, n_IRQ;
|
775 | dbda808a | bellard | |
776 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
777 | dbda808a | bellard | if (addr & 0xF) |
778 | dbda808a | bellard | return;
|
779 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
780 | dbda808a | bellard | val = bswap32(val); |
781 | dbda808a | bellard | #endif
|
782 | dbda808a | bellard | addr &= 0x1FFF0;
|
783 | dbda808a | bellard | idx = addr / 0x1000;
|
784 | dbda808a | bellard | dst = &opp->dst[idx]; |
785 | dbda808a | bellard | addr &= 0xFF0;
|
786 | dbda808a | bellard | switch (addr) {
|
787 | dbda808a | bellard | #if MAX_IPI > 0 |
788 | dbda808a | bellard | case 0x40: /* PIPD */ |
789 | dbda808a | bellard | case 0x50: |
790 | dbda808a | bellard | case 0x60: |
791 | dbda808a | bellard | case 0x70: |
792 | dbda808a | bellard | idx = (addr - 0x40) >> 4; |
793 | dbda808a | bellard | write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE, val); |
794 | 611493d9 | bellard | openpic_set_irq(opp, IRQ_IPI0 + idx, 1);
|
795 | 611493d9 | bellard | openpic_set_irq(opp, IRQ_IPI0 + idx, 0);
|
796 | dbda808a | bellard | break;
|
797 | dbda808a | bellard | #endif
|
798 | dbda808a | bellard | case 0x80: /* PCTP */ |
799 | dbda808a | bellard | dst->pctp = val & 0x0000000F;
|
800 | dbda808a | bellard | break;
|
801 | dbda808a | bellard | case 0x90: /* WHOAMI */ |
802 | dbda808a | bellard | /* Read-only register */
|
803 | dbda808a | bellard | break;
|
804 | dbda808a | bellard | case 0xA0: /* PIAC */ |
805 | dbda808a | bellard | /* Read-only register */
|
806 | dbda808a | bellard | break;
|
807 | dbda808a | bellard | case 0xB0: /* PEOI */ |
808 | dbda808a | bellard | DPRINTF("PEOI\n");
|
809 | e9df014c | j_mayer | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
810 | e9df014c | j_mayer | IRQ_resetbit(&dst->servicing, s_IRQ); |
811 | dbda808a | bellard | dst->servicing.next = -1;
|
812 | dbda808a | bellard | /* Set up next servicing IRQ */
|
813 | e9df014c | j_mayer | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
814 | e9df014c | j_mayer | /* Check queued interrupts. */
|
815 | e9df014c | j_mayer | n_IRQ = IRQ_get_next(opp, &dst->raised); |
816 | e9df014c | j_mayer | src = &opp->src[n_IRQ]; |
817 | e9df014c | j_mayer | if (n_IRQ != -1 && |
818 | e9df014c | j_mayer | (s_IRQ == -1 ||
|
819 | e9df014c | j_mayer | IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) { |
820 | e9df014c | j_mayer | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
|
821 | e9df014c | j_mayer | idx, n_IRQ); |
822 | e9df014c | j_mayer | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]); |
823 | e9df014c | j_mayer | } |
824 | dbda808a | bellard | break;
|
825 | dbda808a | bellard | default:
|
826 | dbda808a | bellard | break;
|
827 | dbda808a | bellard | } |
828 | dbda808a | bellard | } |
829 | dbda808a | bellard | |
830 | dbda808a | bellard | static uint32_t openpic_cpu_read (void *opaque, uint32_t addr) |
831 | dbda808a | bellard | { |
832 | dbda808a | bellard | openpic_t *opp = opaque; |
833 | dbda808a | bellard | IRQ_src_t *src; |
834 | dbda808a | bellard | IRQ_dst_t *dst; |
835 | dbda808a | bellard | uint32_t retval; |
836 | dbda808a | bellard | int idx, n_IRQ;
|
837 | 3b46e624 | ths | |
838 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
839 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
840 | dbda808a | bellard | if (addr & 0xF) |
841 | dbda808a | bellard | return retval;
|
842 | dbda808a | bellard | addr &= 0x1FFF0;
|
843 | dbda808a | bellard | idx = addr / 0x1000;
|
844 | dbda808a | bellard | dst = &opp->dst[idx]; |
845 | dbda808a | bellard | addr &= 0xFF0;
|
846 | dbda808a | bellard | switch (addr) {
|
847 | dbda808a | bellard | case 0x80: /* PCTP */ |
848 | dbda808a | bellard | retval = dst->pctp; |
849 | dbda808a | bellard | break;
|
850 | dbda808a | bellard | case 0x90: /* WHOAMI */ |
851 | dbda808a | bellard | retval = idx; |
852 | dbda808a | bellard | break;
|
853 | dbda808a | bellard | case 0xA0: /* PIAC */ |
854 | e9df014c | j_mayer | DPRINTF("Lower OpenPIC INT output\n");
|
855 | e9df014c | j_mayer | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); |
856 | dbda808a | bellard | n_IRQ = IRQ_get_next(opp, &dst->raised); |
857 | dbda808a | bellard | DPRINTF("PIAC: irq=%d\n", n_IRQ);
|
858 | dbda808a | bellard | if (n_IRQ == -1) { |
859 | dbda808a | bellard | /* No more interrupt pending */
|
860 | e9df014c | j_mayer | retval = IPVP_VECTOR(opp->spve); |
861 | dbda808a | bellard | } else {
|
862 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
863 | dbda808a | bellard | if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
|
864 | dbda808a | bellard | !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) { |
865 | dbda808a | bellard | /* - Spurious level-sensitive IRQ
|
866 | dbda808a | bellard | * - Priorities has been changed
|
867 | dbda808a | bellard | * and the pending IRQ isn't allowed anymore
|
868 | dbda808a | bellard | */
|
869 | dbda808a | bellard | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
870 | dbda808a | bellard | retval = IPVP_VECTOR(opp->spve); |
871 | dbda808a | bellard | } else {
|
872 | dbda808a | bellard | /* IRQ enter servicing state */
|
873 | dbda808a | bellard | IRQ_setbit(&dst->servicing, n_IRQ); |
874 | dbda808a | bellard | retval = IPVP_VECTOR(src->ipvp); |
875 | dbda808a | bellard | } |
876 | dbda808a | bellard | IRQ_resetbit(&dst->raised, n_IRQ); |
877 | dbda808a | bellard | dst->raised.next = -1;
|
878 | 611493d9 | bellard | if (!test_bit(&src->ipvp, IPVP_SENSE)) {
|
879 | 611493d9 | bellard | /* edge-sensitive IRQ */
|
880 | dbda808a | bellard | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
881 | 611493d9 | bellard | src->pending = 0;
|
882 | 611493d9 | bellard | } |
883 | dbda808a | bellard | } |
884 | dbda808a | bellard | break;
|
885 | dbda808a | bellard | case 0xB0: /* PEOI */ |
886 | dbda808a | bellard | retval = 0;
|
887 | dbda808a | bellard | break;
|
888 | dbda808a | bellard | #if MAX_IPI > 0 |
889 | dbda808a | bellard | case 0x40: /* IDE */ |
890 | dbda808a | bellard | case 0x50: |
891 | dbda808a | bellard | idx = (addr - 0x40) >> 4; |
892 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE); |
893 | dbda808a | bellard | break;
|
894 | dbda808a | bellard | #endif
|
895 | dbda808a | bellard | default:
|
896 | dbda808a | bellard | break;
|
897 | dbda808a | bellard | } |
898 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
899 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
900 | dbda808a | bellard | retval= bswap32(retval); |
901 | dbda808a | bellard | #endif
|
902 | dbda808a | bellard | |
903 | dbda808a | bellard | return retval;
|
904 | dbda808a | bellard | } |
905 | dbda808a | bellard | |
906 | dbda808a | bellard | static void openpic_buggy_write (void *opaque, |
907 | dbda808a | bellard | target_phys_addr_t addr, uint32_t val) |
908 | dbda808a | bellard | { |
909 | dbda808a | bellard | printf("Invalid OPENPIC write access !\n");
|
910 | dbda808a | bellard | } |
911 | dbda808a | bellard | |
912 | dbda808a | bellard | static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr) |
913 | dbda808a | bellard | { |
914 | dbda808a | bellard | printf("Invalid OPENPIC read access !\n");
|
915 | dbda808a | bellard | |
916 | dbda808a | bellard | return -1; |
917 | dbda808a | bellard | } |
918 | dbda808a | bellard | |
919 | dbda808a | bellard | static void openpic_writel (void *opaque, |
920 | dbda808a | bellard | target_phys_addr_t addr, uint32_t val) |
921 | dbda808a | bellard | { |
922 | dbda808a | bellard | openpic_t *opp = opaque; |
923 | dbda808a | bellard | |
924 | dbda808a | bellard | addr &= 0x3FFFF;
|
925 | 611493d9 | bellard | DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val); |
926 | dbda808a | bellard | if (addr < 0x1100) { |
927 | dbda808a | bellard | /* Global registers */
|
928 | dbda808a | bellard | openpic_gbl_write(opp, addr, val); |
929 | dbda808a | bellard | } else if (addr < 0x10000) { |
930 | dbda808a | bellard | /* Timers registers */
|
931 | dbda808a | bellard | openpic_timer_write(opp, addr, val); |
932 | dbda808a | bellard | } else if (addr < 0x20000) { |
933 | dbda808a | bellard | /* Source registers */
|
934 | dbda808a | bellard | openpic_src_write(opp, addr, val); |
935 | dbda808a | bellard | } else {
|
936 | dbda808a | bellard | /* CPU registers */
|
937 | dbda808a | bellard | openpic_cpu_write(opp, addr, val); |
938 | dbda808a | bellard | } |
939 | dbda808a | bellard | } |
940 | dbda808a | bellard | |
941 | dbda808a | bellard | static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr) |
942 | dbda808a | bellard | { |
943 | dbda808a | bellard | openpic_t *opp = opaque; |
944 | dbda808a | bellard | uint32_t retval; |
945 | dbda808a | bellard | |
946 | dbda808a | bellard | addr &= 0x3FFFF;
|
947 | 611493d9 | bellard | DPRINTF("%s: offset %08x\n", __func__, (int)addr); |
948 | dbda808a | bellard | if (addr < 0x1100) { |
949 | dbda808a | bellard | /* Global registers */
|
950 | dbda808a | bellard | retval = openpic_gbl_read(opp, addr); |
951 | dbda808a | bellard | } else if (addr < 0x10000) { |
952 | dbda808a | bellard | /* Timers registers */
|
953 | dbda808a | bellard | retval = openpic_timer_read(opp, addr); |
954 | dbda808a | bellard | } else if (addr < 0x20000) { |
955 | dbda808a | bellard | /* Source registers */
|
956 | dbda808a | bellard | retval = openpic_src_read(opp, addr); |
957 | dbda808a | bellard | } else {
|
958 | dbda808a | bellard | /* CPU registers */
|
959 | dbda808a | bellard | retval = openpic_cpu_read(opp, addr); |
960 | dbda808a | bellard | } |
961 | dbda808a | bellard | |
962 | dbda808a | bellard | return retval;
|
963 | dbda808a | bellard | } |
964 | dbda808a | bellard | |
965 | dbda808a | bellard | static CPUWriteMemoryFunc *openpic_write[] = {
|
966 | dbda808a | bellard | &openpic_buggy_write, |
967 | dbda808a | bellard | &openpic_buggy_write, |
968 | dbda808a | bellard | &openpic_writel, |
969 | dbda808a | bellard | }; |
970 | dbda808a | bellard | |
971 | dbda808a | bellard | static CPUReadMemoryFunc *openpic_read[] = {
|
972 | dbda808a | bellard | &openpic_buggy_read, |
973 | dbda808a | bellard | &openpic_buggy_read, |
974 | dbda808a | bellard | &openpic_readl, |
975 | dbda808a | bellard | }; |
976 | dbda808a | bellard | |
977 | 5fafdf24 | ths | static void openpic_map(PCIDevice *pci_dev, int region_num, |
978 | dbda808a | bellard | uint32_t addr, uint32_t size, int type)
|
979 | dbda808a | bellard | { |
980 | dbda808a | bellard | openpic_t *opp; |
981 | dbda808a | bellard | |
982 | dbda808a | bellard | DPRINTF("Map OpenPIC\n");
|
983 | dbda808a | bellard | opp = (openpic_t *)pci_dev; |
984 | dbda808a | bellard | /* Global registers */
|
985 | dbda808a | bellard | DPRINTF("Register OPENPIC gbl %08x => %08x\n",
|
986 | dbda808a | bellard | addr + 0x1000, addr + 0x1000 + 0x100); |
987 | dbda808a | bellard | /* Timer registers */
|
988 | dbda808a | bellard | DPRINTF("Register OPENPIC timer %08x => %08x\n",
|
989 | dbda808a | bellard | addr + 0x1100, addr + 0x1100 + 0x40 * MAX_TMR); |
990 | dbda808a | bellard | /* Interrupt source registers */
|
991 | dbda808a | bellard | DPRINTF("Register OPENPIC src %08x => %08x\n",
|
992 | dbda808a | bellard | addr + 0x10000, addr + 0x10000 + 0x20 * (EXT_IRQ + 2)); |
993 | dbda808a | bellard | /* Per CPU registers */
|
994 | dbda808a | bellard | DPRINTF("Register OPENPIC dst %08x => %08x\n",
|
995 | dbda808a | bellard | addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU); |
996 | 91d848eb | bellard | cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
|
997 | dbda808a | bellard | #if 0 // Don't implement ISU for now
|
998 | dbda808a | bellard | opp_io_memory = cpu_register_io_memory(0, openpic_src_read,
|
999 | dbda808a | bellard | openpic_src_write);
|
1000 | dbda808a | bellard | cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
|
1001 | dbda808a | bellard | opp_io_memory);
|
1002 | dbda808a | bellard | #endif
|
1003 | dbda808a | bellard | } |
1004 | dbda808a | bellard | |
1005 | 67b55785 | blueswir1 | static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
1006 | 67b55785 | blueswir1 | { |
1007 | 67b55785 | blueswir1 | unsigned int i; |
1008 | 67b55785 | blueswir1 | |
1009 | 67b55785 | blueswir1 | for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) |
1010 | 67b55785 | blueswir1 | qemu_put_be32s(f, &q->queue[i]); |
1011 | 67b55785 | blueswir1 | |
1012 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &q->next); |
1013 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &q->priority); |
1014 | 67b55785 | blueswir1 | } |
1015 | 67b55785 | blueswir1 | |
1016 | 67b55785 | blueswir1 | static void openpic_save(QEMUFile* f, void *opaque) |
1017 | 67b55785 | blueswir1 | { |
1018 | 67b55785 | blueswir1 | openpic_t *opp = (openpic_t *)opaque; |
1019 | 67b55785 | blueswir1 | unsigned int i; |
1020 | 67b55785 | blueswir1 | |
1021 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->frep); |
1022 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->glbc); |
1023 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->micr); |
1024 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->veni); |
1025 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->pint); |
1026 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->spve); |
1027 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->tifr); |
1028 | 67b55785 | blueswir1 | |
1029 | 67b55785 | blueswir1 | for (i = 0; i < MAX_IRQ; i++) { |
1030 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->src[i].ipvp); |
1031 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->src[i].ide); |
1032 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &opp->src[i].type); |
1033 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &opp->src[i].last_cpu); |
1034 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &opp->src[i].pending); |
1035 | 67b55785 | blueswir1 | } |
1036 | 67b55785 | blueswir1 | |
1037 | 67b55785 | blueswir1 | for (i = 0; i < MAX_IRQ; i++) { |
1038 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->dst[i].pctp); |
1039 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->dst[i].pcsr); |
1040 | 67b55785 | blueswir1 | openpic_save_IRQ_queue(f, &opp->dst[i].raised); |
1041 | 67b55785 | blueswir1 | openpic_save_IRQ_queue(f, &opp->dst[i].servicing); |
1042 | 67b55785 | blueswir1 | } |
1043 | 67b55785 | blueswir1 | |
1044 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &opp->nb_cpus); |
1045 | 67b55785 | blueswir1 | |
1046 | 67b55785 | blueswir1 | for (i = 0; i < MAX_TMR; i++) { |
1047 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->timers[i].ticc); |
1048 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->timers[i].tibc); |
1049 | 67b55785 | blueswir1 | } |
1050 | 67b55785 | blueswir1 | |
1051 | 67b55785 | blueswir1 | #if MAX_DBL > 0 |
1052 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->dar); |
1053 | 67b55785 | blueswir1 | |
1054 | 67b55785 | blueswir1 | for (i = 0; i < MAX_DBL; i++) { |
1055 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->doorbells[i].dmr); |
1056 | 67b55785 | blueswir1 | } |
1057 | 67b55785 | blueswir1 | #endif
|
1058 | 67b55785 | blueswir1 | |
1059 | 67b55785 | blueswir1 | #if MAX_MBX > 0 |
1060 | 67b55785 | blueswir1 | for (i = 0; i < MAX_MAILBOXES; i++) { |
1061 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->mailboxes[i].mbr); |
1062 | 67b55785 | blueswir1 | } |
1063 | 67b55785 | blueswir1 | #endif
|
1064 | 67b55785 | blueswir1 | |
1065 | 67b55785 | blueswir1 | pci_device_save(&opp->pci_dev, f); |
1066 | 67b55785 | blueswir1 | } |
1067 | 67b55785 | blueswir1 | |
1068 | 67b55785 | blueswir1 | static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
1069 | 67b55785 | blueswir1 | { |
1070 | 67b55785 | blueswir1 | unsigned int i; |
1071 | 67b55785 | blueswir1 | |
1072 | 67b55785 | blueswir1 | for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) |
1073 | 67b55785 | blueswir1 | qemu_get_be32s(f, &q->queue[i]); |
1074 | 67b55785 | blueswir1 | |
1075 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &q->next); |
1076 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &q->priority); |
1077 | 67b55785 | blueswir1 | } |
1078 | 67b55785 | blueswir1 | |
1079 | 67b55785 | blueswir1 | static int openpic_load(QEMUFile* f, void *opaque, int version_id) |
1080 | 67b55785 | blueswir1 | { |
1081 | 67b55785 | blueswir1 | openpic_t *opp = (openpic_t *)opaque; |
1082 | 67b55785 | blueswir1 | unsigned int i; |
1083 | 67b55785 | blueswir1 | |
1084 | 67b55785 | blueswir1 | if (version_id != 1) |
1085 | 67b55785 | blueswir1 | return -EINVAL;
|
1086 | 67b55785 | blueswir1 | |
1087 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->frep); |
1088 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->glbc); |
1089 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->micr); |
1090 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->veni); |
1091 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->pint); |
1092 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->spve); |
1093 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->tifr); |
1094 | 67b55785 | blueswir1 | |
1095 | 67b55785 | blueswir1 | for (i = 0; i < MAX_IRQ; i++) { |
1096 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->src[i].ipvp); |
1097 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->src[i].ide); |
1098 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &opp->src[i].type); |
1099 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &opp->src[i].last_cpu); |
1100 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &opp->src[i].pending); |
1101 | 67b55785 | blueswir1 | } |
1102 | 67b55785 | blueswir1 | |
1103 | 67b55785 | blueswir1 | for (i = 0; i < MAX_IRQ; i++) { |
1104 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->dst[i].pctp); |
1105 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->dst[i].pcsr); |
1106 | 67b55785 | blueswir1 | openpic_load_IRQ_queue(f, &opp->dst[i].raised); |
1107 | 67b55785 | blueswir1 | openpic_load_IRQ_queue(f, &opp->dst[i].servicing); |
1108 | 67b55785 | blueswir1 | } |
1109 | 67b55785 | blueswir1 | |
1110 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &opp->nb_cpus); |
1111 | 67b55785 | blueswir1 | |
1112 | 67b55785 | blueswir1 | for (i = 0; i < MAX_TMR; i++) { |
1113 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->timers[i].ticc); |
1114 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->timers[i].tibc); |
1115 | 67b55785 | blueswir1 | } |
1116 | 67b55785 | blueswir1 | |
1117 | 67b55785 | blueswir1 | #if MAX_DBL > 0 |
1118 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->dar); |
1119 | 67b55785 | blueswir1 | |
1120 | 67b55785 | blueswir1 | for (i = 0; i < MAX_DBL; i++) { |
1121 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->doorbells[i].dmr); |
1122 | 67b55785 | blueswir1 | } |
1123 | 67b55785 | blueswir1 | #endif
|
1124 | 67b55785 | blueswir1 | |
1125 | 67b55785 | blueswir1 | #if MAX_MBX > 0 |
1126 | 67b55785 | blueswir1 | for (i = 0; i < MAX_MAILBOXES; i++) { |
1127 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->mailboxes[i].mbr); |
1128 | 67b55785 | blueswir1 | } |
1129 | 67b55785 | blueswir1 | #endif
|
1130 | 67b55785 | blueswir1 | |
1131 | 67b55785 | blueswir1 | return pci_device_load(&opp->pci_dev, f);
|
1132 | 67b55785 | blueswir1 | } |
1133 | 67b55785 | blueswir1 | |
1134 | e9df014c | j_mayer | qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
1135 | e9df014c | j_mayer | qemu_irq **irqs, qemu_irq irq_out) |
1136 | dbda808a | bellard | { |
1137 | dbda808a | bellard | openpic_t *opp; |
1138 | dbda808a | bellard | uint8_t *pci_conf; |
1139 | dbda808a | bellard | int i, m;
|
1140 | 3b46e624 | ths | |
1141 | dbda808a | bellard | /* XXX: for now, only one CPU is supported */
|
1142 | dbda808a | bellard | if (nb_cpus != 1) |
1143 | dbda808a | bellard | return NULL; |
1144 | 91d848eb | bellard | if (bus) {
|
1145 | 91d848eb | bellard | opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t), |
1146 | 91d848eb | bellard | -1, NULL, NULL); |
1147 | 91d848eb | bellard | if (opp == NULL) |
1148 | 91d848eb | bellard | return NULL; |
1149 | 91d848eb | bellard | pci_conf = opp->pci_dev.config; |
1150 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); |
1151 | 4ebcf884 | blueswir1 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2); |
1152 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME?
|
1153 | 91d848eb | bellard | pci_conf[0x0e] = 0x00; // header_type |
1154 | 91d848eb | bellard | pci_conf[0x3d] = 0x00; // no interrupt pin |
1155 | 3b46e624 | ths | |
1156 | 91d848eb | bellard | /* Register I/O spaces */
|
1157 | 91d848eb | bellard | pci_register_io_region((PCIDevice *)opp, 0, 0x40000, |
1158 | 91d848eb | bellard | PCI_ADDRESS_SPACE_MEM, &openpic_map); |
1159 | 91d848eb | bellard | } else {
|
1160 | 91d848eb | bellard | opp = qemu_mallocz(sizeof(openpic_t));
|
1161 | 91d848eb | bellard | } |
1162 | 91d848eb | bellard | opp->mem_index = cpu_register_io_memory(0, openpic_read,
|
1163 | 91d848eb | bellard | openpic_write, opp); |
1164 | 3b46e624 | ths | |
1165 | 91d848eb | bellard | // isu_base &= 0xFFFC0000;
|
1166 | dbda808a | bellard | opp->nb_cpus = nb_cpus; |
1167 | dbda808a | bellard | /* Set IRQ types */
|
1168 | dbda808a | bellard | for (i = 0; i < EXT_IRQ; i++) { |
1169 | dbda808a | bellard | opp->src[i].type = IRQ_EXTERNAL; |
1170 | dbda808a | bellard | } |
1171 | dbda808a | bellard | for (; i < IRQ_TIM0; i++) {
|
1172 | dbda808a | bellard | opp->src[i].type = IRQ_SPECIAL; |
1173 | dbda808a | bellard | } |
1174 | dbda808a | bellard | #if MAX_IPI > 0 |
1175 | dbda808a | bellard | m = IRQ_IPI0; |
1176 | dbda808a | bellard | #else
|
1177 | dbda808a | bellard | m = IRQ_DBL0; |
1178 | dbda808a | bellard | #endif
|
1179 | dbda808a | bellard | for (; i < m; i++) {
|
1180 | dbda808a | bellard | opp->src[i].type = IRQ_TIMER; |
1181 | dbda808a | bellard | } |
1182 | dbda808a | bellard | for (; i < MAX_IRQ; i++) {
|
1183 | dbda808a | bellard | opp->src[i].type = IRQ_INTERNAL; |
1184 | dbda808a | bellard | } |
1185 | 7668a27f | bellard | for (i = 0; i < nb_cpus; i++) |
1186 | e9df014c | j_mayer | opp->dst[i].irqs = irqs[i]; |
1187 | e9df014c | j_mayer | opp->irq_out = irq_out; |
1188 | 67b55785 | blueswir1 | |
1189 | 67b55785 | blueswir1 | register_savevm("openpic", 0, 1, openpic_save, openpic_load, opp); |
1190 | 67b55785 | blueswir1 | qemu_register_reset(openpic_reset, opp); |
1191 | dbda808a | bellard | openpic_reset(opp); |
1192 | 91d848eb | bellard | if (pmem_index)
|
1193 | 91d848eb | bellard | *pmem_index = opp->mem_index; |
1194 | e9df014c | j_mayer | |
1195 | d537cf6c | pbrook | return qemu_allocate_irqs(openpic_set_irq, opp, MAX_IRQ);
|
1196 | dbda808a | bellard | } |