Archipelago » qemu

        case OPC_BLTZALL: /* 0 < 0 likely */

            gen_op_set_T0(ctx->pc + 8);

            gen_op_store_T0_gpr(31);

            return;

        case OPC_BNEL:    /* rx != rx likely */

        case OPC_BGTZL:   /* 0 > 0 likely */

        case OPC_BLTZL:   /* 0 < 0 likely */

            /* Skip the instruction in the delay slot */

            MIPS_DEBUG("bnever and skip");

            return;

        case OPC_J:

            ctx->hflags |= MIPS_HFLAG_B;