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1 | 4ce7ff6e | aurel32 | /*
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2 | 4ce7ff6e | aurel32 | * QEMU JAZZ RC4030 chipset
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3 | 4ce7ff6e | aurel32 | *
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4 | 4ce7ff6e | aurel32 | * Copyright (c) 2007-2008 Hervé Poussineau
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5 | 4ce7ff6e | aurel32 | *
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6 | 4ce7ff6e | aurel32 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 4ce7ff6e | aurel32 | * of this software and associated documentation files (the "Software"), to deal
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8 | 4ce7ff6e | aurel32 | * in the Software without restriction, including without limitation the rights
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9 | 4ce7ff6e | aurel32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 4ce7ff6e | aurel32 | * copies of the Software, and to permit persons to whom the Software is
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11 | 4ce7ff6e | aurel32 | * furnished to do so, subject to the following conditions:
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12 | 4ce7ff6e | aurel32 | *
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13 | 4ce7ff6e | aurel32 | * The above copyright notice and this permission notice shall be included in
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14 | 4ce7ff6e | aurel32 | * all copies or substantial portions of the Software.
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15 | 4ce7ff6e | aurel32 | *
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16 | 4ce7ff6e | aurel32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 4ce7ff6e | aurel32 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 4ce7ff6e | aurel32 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 4ce7ff6e | aurel32 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 4ce7ff6e | aurel32 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 4ce7ff6e | aurel32 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 4ce7ff6e | aurel32 | * THE SOFTWARE.
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23 | 4ce7ff6e | aurel32 | */
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24 | 4ce7ff6e | aurel32 | |
25 | 4ce7ff6e | aurel32 | #include "hw.h" |
26 | cd5158ea | aurel32 | #include "mips.h" |
27 | 4ce7ff6e | aurel32 | #include "qemu-timer.h" |
28 | 4ce7ff6e | aurel32 | |
29 | c6945b15 | aurel32 | /********************************************************/
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30 | c6945b15 | aurel32 | /* debug rc4030 */
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31 | c6945b15 | aurel32 | |
32 | 4ce7ff6e | aurel32 | //#define DEBUG_RC4030
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33 | c6945b15 | aurel32 | //#define DEBUG_RC4030_DMA
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34 | 4ce7ff6e | aurel32 | |
35 | 4ce7ff6e | aurel32 | #ifdef DEBUG_RC4030
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36 | c6945b15 | aurel32 | #define DPRINTF(fmt, args...) \
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37 | c6945b15 | aurel32 | do { printf("rc4030: " fmt , ##args); } while (0) |
38 | 4ce7ff6e | aurel32 | static const char* irq_names[] = { "parallel", "floppy", "sound", "video", |
39 | 4ce7ff6e | aurel32 | "network", "scsi", "keyboard", "mouse", "serial0", "serial1" }; |
40 | c6945b15 | aurel32 | #else
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41 | c6945b15 | aurel32 | #define DPRINTF(fmt, args...)
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42 | 4ce7ff6e | aurel32 | #endif
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43 | 4ce7ff6e | aurel32 | |
44 | c6945b15 | aurel32 | #define RC4030_ERROR(fmt, args...) \
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45 | c6945b15 | aurel32 | do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ##args); } while (0) |
46 | c6945b15 | aurel32 | |
47 | c6945b15 | aurel32 | /********************************************************/
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48 | c6945b15 | aurel32 | /* rc4030 emulation */
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49 | c6945b15 | aurel32 | |
50 | c6945b15 | aurel32 | typedef struct dma_pagetable_entry { |
51 | c6945b15 | aurel32 | int32_t frame; |
52 | c6945b15 | aurel32 | int32_t owner; |
53 | c6945b15 | aurel32 | } __attribute__((packed)) dma_pagetable_entry; |
54 | c6945b15 | aurel32 | |
55 | c6945b15 | aurel32 | #define DMA_PAGESIZE 4096 |
56 | c6945b15 | aurel32 | #define DMA_REG_ENABLE 1 |
57 | c6945b15 | aurel32 | #define DMA_REG_COUNT 2 |
58 | c6945b15 | aurel32 | #define DMA_REG_ADDRESS 3 |
59 | c6945b15 | aurel32 | |
60 | c6945b15 | aurel32 | #define DMA_FLAG_ENABLE 0x0001 |
61 | c6945b15 | aurel32 | #define DMA_FLAG_MEM_TO_DEV 0x0002 |
62 | c6945b15 | aurel32 | #define DMA_FLAG_TC_INTR 0x0100 |
63 | c6945b15 | aurel32 | #define DMA_FLAG_MEM_INTR 0x0200 |
64 | c6945b15 | aurel32 | #define DMA_FLAG_ADDR_INTR 0x0400 |
65 | c6945b15 | aurel32 | |
66 | 4ce7ff6e | aurel32 | typedef struct rc4030State |
67 | 4ce7ff6e | aurel32 | { |
68 | 4ce7ff6e | aurel32 | uint32_t config; /* 0x0000: RC4030 config register */
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69 | 4ce7ff6e | aurel32 | uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
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70 | 4ce7ff6e | aurel32 | |
71 | 4ce7ff6e | aurel32 | /* DMA */
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72 | 4ce7ff6e | aurel32 | uint32_t dma_regs[8][4]; |
73 | 4ce7ff6e | aurel32 | uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
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74 | 4ce7ff6e | aurel32 | uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
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75 | 4ce7ff6e | aurel32 | |
76 | 4ce7ff6e | aurel32 | /* cache */
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77 | 4ce7ff6e | aurel32 | uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
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78 | 4ce7ff6e | aurel32 | uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
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79 | 4ce7ff6e | aurel32 | uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
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80 | 4ce7ff6e | aurel32 | uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
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81 | 4ce7ff6e | aurel32 | uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
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82 | 4ce7ff6e | aurel32 | uint32_t cache_bwin; /* 0x0060: I/O Cache Buffer Window */
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83 | 4ce7ff6e | aurel32 | |
84 | 4ce7ff6e | aurel32 | uint32_t offset210; |
85 | 4ce7ff6e | aurel32 | uint32_t nvram_protect; /* 0x0220: NV ram protect register */
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86 | 4ce7ff6e | aurel32 | uint32_t offset238; |
87 | 4ce7ff6e | aurel32 | uint32_t rem_speed[15];
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88 | 4ce7ff6e | aurel32 | uint32_t imr_jazz; /* Local bus int enable mask */
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89 | 4ce7ff6e | aurel32 | uint32_t isr_jazz; /* Local bus int source */
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90 | 4ce7ff6e | aurel32 | |
91 | 4ce7ff6e | aurel32 | /* timer */
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92 | 4ce7ff6e | aurel32 | QEMUTimer *periodic_timer; |
93 | 4ce7ff6e | aurel32 | uint32_t itr; /* Interval timer reload */
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94 | 4ce7ff6e | aurel32 | |
95 | 4ce7ff6e | aurel32 | qemu_irq timer_irq; |
96 | 4ce7ff6e | aurel32 | qemu_irq jazz_bus_irq; |
97 | 4ce7ff6e | aurel32 | } rc4030State; |
98 | 4ce7ff6e | aurel32 | |
99 | 4ce7ff6e | aurel32 | static void set_next_tick(rc4030State *s) |
100 | 4ce7ff6e | aurel32 | { |
101 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
102 | b0f74c87 | balrog | uint32_t tm_hz; |
103 | 4ce7ff6e | aurel32 | |
104 | b0f74c87 | balrog | tm_hz = 1000 / (s->itr + 1); |
105 | 4ce7ff6e | aurel32 | |
106 | b0f74c87 | balrog | qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + ticks_per_sec / tm_hz); |
107 | 4ce7ff6e | aurel32 | } |
108 | 4ce7ff6e | aurel32 | |
109 | 4ce7ff6e | aurel32 | /* called for accesses to rc4030 */
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110 | 4ce7ff6e | aurel32 | static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr) |
111 | 4ce7ff6e | aurel32 | { |
112 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
113 | 4ce7ff6e | aurel32 | uint32_t val; |
114 | 4ce7ff6e | aurel32 | |
115 | 4ce7ff6e | aurel32 | addr &= 0x3fff;
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116 | 4ce7ff6e | aurel32 | switch (addr & ~0x3) { |
117 | 4ce7ff6e | aurel32 | /* Global config register */
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118 | 4ce7ff6e | aurel32 | case 0x0000: |
119 | 4ce7ff6e | aurel32 | val = s->config; |
120 | 4ce7ff6e | aurel32 | break;
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121 | 4ce7ff6e | aurel32 | /* Invalid Address register */
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122 | 4ce7ff6e | aurel32 | case 0x0010: |
123 | 4ce7ff6e | aurel32 | val = s->invalid_address_register; |
124 | 4ce7ff6e | aurel32 | break;
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125 | 4ce7ff6e | aurel32 | /* DMA transl. table base */
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126 | 4ce7ff6e | aurel32 | case 0x0018: |
127 | 4ce7ff6e | aurel32 | val = s->dma_tl_base; |
128 | 4ce7ff6e | aurel32 | break;
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129 | 4ce7ff6e | aurel32 | /* DMA transl. table limit */
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130 | 4ce7ff6e | aurel32 | case 0x0020: |
131 | 4ce7ff6e | aurel32 | val = s->dma_tl_limit; |
132 | 4ce7ff6e | aurel32 | break;
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133 | 4ce7ff6e | aurel32 | /* Remote Failed Address */
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134 | 4ce7ff6e | aurel32 | case 0x0038: |
135 | 4ce7ff6e | aurel32 | val = s->remote_failed_address; |
136 | 4ce7ff6e | aurel32 | break;
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137 | 4ce7ff6e | aurel32 | /* Memory Failed Address */
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138 | 4ce7ff6e | aurel32 | case 0x0040: |
139 | 4ce7ff6e | aurel32 | val = s->memory_failed_address; |
140 | 4ce7ff6e | aurel32 | break;
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141 | 4ce7ff6e | aurel32 | /* I/O Cache Byte Mask */
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142 | 4ce7ff6e | aurel32 | case 0x0058: |
143 | 4ce7ff6e | aurel32 | val = s->cache_bmask; |
144 | 4ce7ff6e | aurel32 | /* HACK */
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145 | 4ce7ff6e | aurel32 | if (s->cache_bmask == (uint32_t)-1) |
146 | 4ce7ff6e | aurel32 | s->cache_bmask = 0;
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147 | 4ce7ff6e | aurel32 | break;
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148 | 4ce7ff6e | aurel32 | /* Remote Speed Registers */
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149 | 4ce7ff6e | aurel32 | case 0x0070: |
150 | 4ce7ff6e | aurel32 | case 0x0078: |
151 | 4ce7ff6e | aurel32 | case 0x0080: |
152 | 4ce7ff6e | aurel32 | case 0x0088: |
153 | 4ce7ff6e | aurel32 | case 0x0090: |
154 | 4ce7ff6e | aurel32 | case 0x0098: |
155 | 4ce7ff6e | aurel32 | case 0x00a0: |
156 | 4ce7ff6e | aurel32 | case 0x00a8: |
157 | 4ce7ff6e | aurel32 | case 0x00b0: |
158 | 4ce7ff6e | aurel32 | case 0x00b8: |
159 | 4ce7ff6e | aurel32 | case 0x00c0: |
160 | 4ce7ff6e | aurel32 | case 0x00c8: |
161 | 4ce7ff6e | aurel32 | case 0x00d0: |
162 | 4ce7ff6e | aurel32 | case 0x00d8: |
163 | 4ce7ff6e | aurel32 | case 0x00e0: |
164 | 4ce7ff6e | aurel32 | val = s->rem_speed[(addr - 0x0070) >> 3]; |
165 | 4ce7ff6e | aurel32 | break;
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166 | 4ce7ff6e | aurel32 | /* DMA channel base address */
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167 | 4ce7ff6e | aurel32 | case 0x0100: |
168 | 4ce7ff6e | aurel32 | case 0x0108: |
169 | 4ce7ff6e | aurel32 | case 0x0110: |
170 | 4ce7ff6e | aurel32 | case 0x0118: |
171 | 4ce7ff6e | aurel32 | case 0x0120: |
172 | 4ce7ff6e | aurel32 | case 0x0128: |
173 | 4ce7ff6e | aurel32 | case 0x0130: |
174 | 4ce7ff6e | aurel32 | case 0x0138: |
175 | 4ce7ff6e | aurel32 | case 0x0140: |
176 | 4ce7ff6e | aurel32 | case 0x0148: |
177 | 4ce7ff6e | aurel32 | case 0x0150: |
178 | 4ce7ff6e | aurel32 | case 0x0158: |
179 | 4ce7ff6e | aurel32 | case 0x0160: |
180 | 4ce7ff6e | aurel32 | case 0x0168: |
181 | 4ce7ff6e | aurel32 | case 0x0170: |
182 | 4ce7ff6e | aurel32 | case 0x0178: |
183 | 4ce7ff6e | aurel32 | case 0x0180: |
184 | 4ce7ff6e | aurel32 | case 0x0188: |
185 | 4ce7ff6e | aurel32 | case 0x0190: |
186 | 4ce7ff6e | aurel32 | case 0x0198: |
187 | 4ce7ff6e | aurel32 | case 0x01a0: |
188 | 4ce7ff6e | aurel32 | case 0x01a8: |
189 | 4ce7ff6e | aurel32 | case 0x01b0: |
190 | 4ce7ff6e | aurel32 | case 0x01b8: |
191 | 4ce7ff6e | aurel32 | case 0x01c0: |
192 | 4ce7ff6e | aurel32 | case 0x01c8: |
193 | 4ce7ff6e | aurel32 | case 0x01d0: |
194 | 4ce7ff6e | aurel32 | case 0x01d8: |
195 | 4ce7ff6e | aurel32 | case 0x01e0: |
196 | c6945b15 | aurel32 | case 0x01e8: |
197 | 4ce7ff6e | aurel32 | case 0x01f0: |
198 | 4ce7ff6e | aurel32 | case 0x01f8: |
199 | 4ce7ff6e | aurel32 | { |
200 | 4ce7ff6e | aurel32 | int entry = (addr - 0x0100) >> 5; |
201 | 4ce7ff6e | aurel32 | int idx = (addr & 0x1f) >> 3; |
202 | 4ce7ff6e | aurel32 | val = s->dma_regs[entry][idx]; |
203 | 4ce7ff6e | aurel32 | } |
204 | 4ce7ff6e | aurel32 | break;
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205 | 4ce7ff6e | aurel32 | /* Offset 0x0208 */
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206 | 4ce7ff6e | aurel32 | case 0x0208: |
207 | c6945b15 | aurel32 | val = 0;
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208 | 4ce7ff6e | aurel32 | break;
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209 | 4ce7ff6e | aurel32 | /* Offset 0x0210 */
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210 | 4ce7ff6e | aurel32 | case 0x0210: |
211 | 4ce7ff6e | aurel32 | val = s->offset210; |
212 | 4ce7ff6e | aurel32 | break;
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213 | 4ce7ff6e | aurel32 | /* NV ram protect register */
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214 | 4ce7ff6e | aurel32 | case 0x0220: |
215 | 4ce7ff6e | aurel32 | val = s->nvram_protect; |
216 | 4ce7ff6e | aurel32 | break;
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217 | 4ce7ff6e | aurel32 | /* Interval timer count */
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218 | 4ce7ff6e | aurel32 | case 0x0230: |
219 | c6945b15 | aurel32 | val = 0;
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220 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
221 | 4ce7ff6e | aurel32 | break;
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222 | 4ce7ff6e | aurel32 | /* Offset 0x0238 */
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223 | 4ce7ff6e | aurel32 | case 0x0238: |
224 | 4ce7ff6e | aurel32 | val = s->offset238; |
225 | 4ce7ff6e | aurel32 | break;
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226 | 4ce7ff6e | aurel32 | default:
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227 | c6945b15 | aurel32 | RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr); |
228 | 4ce7ff6e | aurel32 | val = 0;
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229 | 4ce7ff6e | aurel32 | break;
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230 | 4ce7ff6e | aurel32 | } |
231 | 4ce7ff6e | aurel32 | |
232 | 4ce7ff6e | aurel32 | if ((addr & ~3) != 0x230) |
233 | c6945b15 | aurel32 | DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr); |
234 | 4ce7ff6e | aurel32 | |
235 | 4ce7ff6e | aurel32 | return val;
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236 | 4ce7ff6e | aurel32 | } |
237 | 4ce7ff6e | aurel32 | |
238 | 4ce7ff6e | aurel32 | static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr) |
239 | 4ce7ff6e | aurel32 | { |
240 | 4ce7ff6e | aurel32 | uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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241 | 4ce7ff6e | aurel32 | if (addr & 0x2) |
242 | 4ce7ff6e | aurel32 | return v >> 16; |
243 | 4ce7ff6e | aurel32 | else
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244 | 4ce7ff6e | aurel32 | return v & 0xffff; |
245 | 4ce7ff6e | aurel32 | } |
246 | 4ce7ff6e | aurel32 | |
247 | 4ce7ff6e | aurel32 | static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr) |
248 | 4ce7ff6e | aurel32 | { |
249 | 4ce7ff6e | aurel32 | uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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250 | 4ce7ff6e | aurel32 | return (v >> (8 * (addr & 0x3))) & 0xff; |
251 | 4ce7ff6e | aurel32 | } |
252 | 4ce7ff6e | aurel32 | |
253 | 4ce7ff6e | aurel32 | static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
254 | 4ce7ff6e | aurel32 | { |
255 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
256 | 4ce7ff6e | aurel32 | addr &= 0x3fff;
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257 | 4ce7ff6e | aurel32 | |
258 | c6945b15 | aurel32 | DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr); |
259 | 4ce7ff6e | aurel32 | |
260 | 4ce7ff6e | aurel32 | switch (addr & ~0x3) { |
261 | 4ce7ff6e | aurel32 | /* Global config register */
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262 | 4ce7ff6e | aurel32 | case 0x0000: |
263 | 4ce7ff6e | aurel32 | s->config = val; |
264 | 4ce7ff6e | aurel32 | break;
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265 | 4ce7ff6e | aurel32 | /* DMA transl. table base */
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266 | 4ce7ff6e | aurel32 | case 0x0018: |
267 | 4ce7ff6e | aurel32 | s->dma_tl_base = val; |
268 | 4ce7ff6e | aurel32 | break;
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269 | 4ce7ff6e | aurel32 | /* DMA transl. table limit */
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270 | 4ce7ff6e | aurel32 | case 0x0020: |
271 | 4ce7ff6e | aurel32 | s->dma_tl_limit = val; |
272 | 4ce7ff6e | aurel32 | break;
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273 | c6945b15 | aurel32 | /* DMA transl. table invalidated */
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274 | c6945b15 | aurel32 | case 0x0028: |
275 | c6945b15 | aurel32 | break;
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276 | c6945b15 | aurel32 | /* Cache Maintenance */
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277 | c6945b15 | aurel32 | case 0x0030: |
278 | c6945b15 | aurel32 | RC4030_ERROR("Cache maintenance not handled yet (val 0x%02x)\n", val);
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279 | c6945b15 | aurel32 | break;
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280 | 4ce7ff6e | aurel32 | /* I/O Cache Physical Tag */
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281 | 4ce7ff6e | aurel32 | case 0x0048: |
282 | 4ce7ff6e | aurel32 | s->cache_ptag = val; |
283 | 4ce7ff6e | aurel32 | break;
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284 | 4ce7ff6e | aurel32 | /* I/O Cache Logical Tag */
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285 | 4ce7ff6e | aurel32 | case 0x0050: |
286 | 4ce7ff6e | aurel32 | s->cache_ltag = val; |
287 | 4ce7ff6e | aurel32 | break;
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288 | 4ce7ff6e | aurel32 | /* I/O Cache Byte Mask */
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289 | 4ce7ff6e | aurel32 | case 0x0058: |
290 | 4ce7ff6e | aurel32 | s->cache_bmask |= val; /* HACK */
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291 | 4ce7ff6e | aurel32 | break;
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292 | 4ce7ff6e | aurel32 | /* I/O Cache Buffer Window */
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293 | 4ce7ff6e | aurel32 | case 0x0060: |
294 | 4ce7ff6e | aurel32 | s->cache_bwin = val; |
295 | 4ce7ff6e | aurel32 | /* HACK */
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296 | 4ce7ff6e | aurel32 | if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) { |
297 | 4ce7ff6e | aurel32 | target_phys_addr_t dests[] = { 4, 0, 8, 0x10 }; |
298 | 4ce7ff6e | aurel32 | static int current = 0; |
299 | 4ce7ff6e | aurel32 | target_phys_addr_t dest = 0 + dests[current];
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300 | 4ce7ff6e | aurel32 | uint8_t buf; |
301 | b1503cda | malc | current = (current + 1) % (ARRAY_SIZE(dests));
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302 | 4ce7ff6e | aurel32 | buf = s->cache_bwin - 1;
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303 | 4ce7ff6e | aurel32 | cpu_physical_memory_rw(dest, &buf, 1, 1); |
304 | 4ce7ff6e | aurel32 | } |
305 | 4ce7ff6e | aurel32 | break;
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306 | 4ce7ff6e | aurel32 | /* Remote Speed Registers */
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307 | 4ce7ff6e | aurel32 | case 0x0070: |
308 | 4ce7ff6e | aurel32 | case 0x0078: |
309 | 4ce7ff6e | aurel32 | case 0x0080: |
310 | 4ce7ff6e | aurel32 | case 0x0088: |
311 | 4ce7ff6e | aurel32 | case 0x0090: |
312 | 4ce7ff6e | aurel32 | case 0x0098: |
313 | 4ce7ff6e | aurel32 | case 0x00a0: |
314 | 4ce7ff6e | aurel32 | case 0x00a8: |
315 | 4ce7ff6e | aurel32 | case 0x00b0: |
316 | 4ce7ff6e | aurel32 | case 0x00b8: |
317 | 4ce7ff6e | aurel32 | case 0x00c0: |
318 | 4ce7ff6e | aurel32 | case 0x00c8: |
319 | 4ce7ff6e | aurel32 | case 0x00d0: |
320 | 4ce7ff6e | aurel32 | case 0x00d8: |
321 | 4ce7ff6e | aurel32 | case 0x00e0: |
322 | 4ce7ff6e | aurel32 | s->rem_speed[(addr - 0x0070) >> 3] = val; |
323 | 4ce7ff6e | aurel32 | break;
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324 | 4ce7ff6e | aurel32 | /* DMA channel base address */
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325 | 4ce7ff6e | aurel32 | case 0x0100: |
326 | 4ce7ff6e | aurel32 | case 0x0108: |
327 | 4ce7ff6e | aurel32 | case 0x0110: |
328 | 4ce7ff6e | aurel32 | case 0x0118: |
329 | 4ce7ff6e | aurel32 | case 0x0120: |
330 | 4ce7ff6e | aurel32 | case 0x0128: |
331 | 4ce7ff6e | aurel32 | case 0x0130: |
332 | 4ce7ff6e | aurel32 | case 0x0138: |
333 | 4ce7ff6e | aurel32 | case 0x0140: |
334 | 4ce7ff6e | aurel32 | case 0x0148: |
335 | 4ce7ff6e | aurel32 | case 0x0150: |
336 | 4ce7ff6e | aurel32 | case 0x0158: |
337 | 4ce7ff6e | aurel32 | case 0x0160: |
338 | 4ce7ff6e | aurel32 | case 0x0168: |
339 | 4ce7ff6e | aurel32 | case 0x0170: |
340 | 4ce7ff6e | aurel32 | case 0x0178: |
341 | 4ce7ff6e | aurel32 | case 0x0180: |
342 | 4ce7ff6e | aurel32 | case 0x0188: |
343 | 4ce7ff6e | aurel32 | case 0x0190: |
344 | 4ce7ff6e | aurel32 | case 0x0198: |
345 | 4ce7ff6e | aurel32 | case 0x01a0: |
346 | 4ce7ff6e | aurel32 | case 0x01a8: |
347 | 4ce7ff6e | aurel32 | case 0x01b0: |
348 | 4ce7ff6e | aurel32 | case 0x01b8: |
349 | 4ce7ff6e | aurel32 | case 0x01c0: |
350 | 4ce7ff6e | aurel32 | case 0x01c8: |
351 | 4ce7ff6e | aurel32 | case 0x01d0: |
352 | 4ce7ff6e | aurel32 | case 0x01d8: |
353 | 4ce7ff6e | aurel32 | case 0x01e0: |
354 | c6945b15 | aurel32 | case 0x01e8: |
355 | 4ce7ff6e | aurel32 | case 0x01f0: |
356 | 4ce7ff6e | aurel32 | case 0x01f8: |
357 | 4ce7ff6e | aurel32 | { |
358 | 4ce7ff6e | aurel32 | int entry = (addr - 0x0100) >> 5; |
359 | 4ce7ff6e | aurel32 | int idx = (addr & 0x1f) >> 3; |
360 | 4ce7ff6e | aurel32 | s->dma_regs[entry][idx] = val; |
361 | 4ce7ff6e | aurel32 | } |
362 | 4ce7ff6e | aurel32 | break;
|
363 | 4ce7ff6e | aurel32 | /* Offset 0x0210 */
|
364 | 4ce7ff6e | aurel32 | case 0x0210: |
365 | 4ce7ff6e | aurel32 | s->offset210 = val; |
366 | 4ce7ff6e | aurel32 | break;
|
367 | 4ce7ff6e | aurel32 | /* Interval timer reload */
|
368 | 4ce7ff6e | aurel32 | case 0x0228: |
369 | 4ce7ff6e | aurel32 | s->itr = val; |
370 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
371 | 4ce7ff6e | aurel32 | set_next_tick(s); |
372 | 4ce7ff6e | aurel32 | break;
|
373 | 4ce7ff6e | aurel32 | default:
|
374 | c6945b15 | aurel32 | RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr); |
375 | 4ce7ff6e | aurel32 | break;
|
376 | 4ce7ff6e | aurel32 | } |
377 | 4ce7ff6e | aurel32 | } |
378 | 4ce7ff6e | aurel32 | |
379 | 4ce7ff6e | aurel32 | static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
380 | 4ce7ff6e | aurel32 | { |
381 | 4ce7ff6e | aurel32 | uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
|
382 | 4ce7ff6e | aurel32 | |
383 | 4ce7ff6e | aurel32 | if (addr & 0x2) |
384 | 4ce7ff6e | aurel32 | val = (val << 16) | (old_val & 0x0000ffff); |
385 | 4ce7ff6e | aurel32 | else
|
386 | 4ce7ff6e | aurel32 | val = val | (old_val & 0xffff0000);
|
387 | 4ce7ff6e | aurel32 | rc4030_writel(opaque, addr & ~0x3, val);
|
388 | 4ce7ff6e | aurel32 | } |
389 | 4ce7ff6e | aurel32 | |
390 | 4ce7ff6e | aurel32 | static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
391 | 4ce7ff6e | aurel32 | { |
392 | 4ce7ff6e | aurel32 | uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
|
393 | 4ce7ff6e | aurel32 | |
394 | 4ce7ff6e | aurel32 | switch (addr & 3) { |
395 | 4ce7ff6e | aurel32 | case 0: |
396 | 4ce7ff6e | aurel32 | val = val | (old_val & 0xffffff00);
|
397 | 4ce7ff6e | aurel32 | break;
|
398 | 4ce7ff6e | aurel32 | case 1: |
399 | 4ce7ff6e | aurel32 | val = (val << 8) | (old_val & 0xffff00ff); |
400 | 4ce7ff6e | aurel32 | break;
|
401 | 4ce7ff6e | aurel32 | case 2: |
402 | 4ce7ff6e | aurel32 | val = (val << 16) | (old_val & 0xff00ffff); |
403 | 4ce7ff6e | aurel32 | break;
|
404 | 4ce7ff6e | aurel32 | case 3: |
405 | 4ce7ff6e | aurel32 | val = (val << 24) | (old_val & 0x00ffffff); |
406 | 4ce7ff6e | aurel32 | break;
|
407 | 4ce7ff6e | aurel32 | } |
408 | 4ce7ff6e | aurel32 | rc4030_writel(opaque, addr & ~0x3, val);
|
409 | 4ce7ff6e | aurel32 | } |
410 | 4ce7ff6e | aurel32 | |
411 | 4ce7ff6e | aurel32 | static CPUReadMemoryFunc *rc4030_read[3] = { |
412 | 4ce7ff6e | aurel32 | rc4030_readb, |
413 | 4ce7ff6e | aurel32 | rc4030_readw, |
414 | 4ce7ff6e | aurel32 | rc4030_readl, |
415 | 4ce7ff6e | aurel32 | }; |
416 | 4ce7ff6e | aurel32 | |
417 | 4ce7ff6e | aurel32 | static CPUWriteMemoryFunc *rc4030_write[3] = { |
418 | 4ce7ff6e | aurel32 | rc4030_writeb, |
419 | 4ce7ff6e | aurel32 | rc4030_writew, |
420 | 4ce7ff6e | aurel32 | rc4030_writel, |
421 | 4ce7ff6e | aurel32 | }; |
422 | 4ce7ff6e | aurel32 | |
423 | 4ce7ff6e | aurel32 | static void update_jazz_irq(rc4030State *s) |
424 | 4ce7ff6e | aurel32 | { |
425 | 4ce7ff6e | aurel32 | uint16_t pending; |
426 | 4ce7ff6e | aurel32 | |
427 | 4ce7ff6e | aurel32 | pending = s->isr_jazz & s->imr_jazz; |
428 | 4ce7ff6e | aurel32 | |
429 | 4ce7ff6e | aurel32 | #ifdef DEBUG_RC4030
|
430 | 4ce7ff6e | aurel32 | if (s->isr_jazz != 0) { |
431 | 4ce7ff6e | aurel32 | uint32_t irq = 0;
|
432 | c6945b15 | aurel32 | DPRINTF("pending irqs:");
|
433 | b1503cda | malc | for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) { |
434 | 4ce7ff6e | aurel32 | if (s->isr_jazz & (1 << irq)) { |
435 | 4ce7ff6e | aurel32 | printf(" %s", irq_names[irq]);
|
436 | 4ce7ff6e | aurel32 | if (!(s->imr_jazz & (1 << irq))) { |
437 | 4ce7ff6e | aurel32 | printf("(ignored)");
|
438 | 4ce7ff6e | aurel32 | } |
439 | 4ce7ff6e | aurel32 | } |
440 | 4ce7ff6e | aurel32 | } |
441 | 4ce7ff6e | aurel32 | printf("\n");
|
442 | 4ce7ff6e | aurel32 | } |
443 | 4ce7ff6e | aurel32 | #endif
|
444 | 4ce7ff6e | aurel32 | |
445 | 4ce7ff6e | aurel32 | if (pending != 0) |
446 | 4ce7ff6e | aurel32 | qemu_irq_raise(s->jazz_bus_irq); |
447 | 4ce7ff6e | aurel32 | else
|
448 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->jazz_bus_irq); |
449 | 4ce7ff6e | aurel32 | } |
450 | 4ce7ff6e | aurel32 | |
451 | 4ce7ff6e | aurel32 | static void rc4030_irq_jazz_request(void *opaque, int irq, int level) |
452 | 4ce7ff6e | aurel32 | { |
453 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
454 | 4ce7ff6e | aurel32 | |
455 | 4ce7ff6e | aurel32 | if (level) {
|
456 | 4ce7ff6e | aurel32 | s->isr_jazz |= 1 << irq;
|
457 | 4ce7ff6e | aurel32 | } else {
|
458 | 4ce7ff6e | aurel32 | s->isr_jazz &= ~(1 << irq);
|
459 | 4ce7ff6e | aurel32 | } |
460 | 4ce7ff6e | aurel32 | |
461 | 4ce7ff6e | aurel32 | update_jazz_irq(s); |
462 | 4ce7ff6e | aurel32 | } |
463 | 4ce7ff6e | aurel32 | |
464 | 4ce7ff6e | aurel32 | static void rc4030_periodic_timer(void *opaque) |
465 | 4ce7ff6e | aurel32 | { |
466 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
467 | 4ce7ff6e | aurel32 | |
468 | 4ce7ff6e | aurel32 | set_next_tick(s); |
469 | 4ce7ff6e | aurel32 | qemu_irq_raise(s->timer_irq); |
470 | 4ce7ff6e | aurel32 | } |
471 | 4ce7ff6e | aurel32 | |
472 | c6945b15 | aurel32 | static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr) |
473 | 4ce7ff6e | aurel32 | { |
474 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
475 | 4ce7ff6e | aurel32 | uint32_t val; |
476 | 4ce7ff6e | aurel32 | uint32_t irq; |
477 | 4ce7ff6e | aurel32 | addr &= 0xfff;
|
478 | 4ce7ff6e | aurel32 | |
479 | 4ce7ff6e | aurel32 | switch (addr) {
|
480 | c6945b15 | aurel32 | /* Local bus int source */
|
481 | 4ce7ff6e | aurel32 | case 0x00: { |
482 | 4ce7ff6e | aurel32 | uint32_t pending = s->isr_jazz & s->imr_jazz; |
483 | 4ce7ff6e | aurel32 | val = 0;
|
484 | 4ce7ff6e | aurel32 | irq = 0;
|
485 | 4ce7ff6e | aurel32 | while (pending) {
|
486 | 4ce7ff6e | aurel32 | if (pending & 1) { |
487 | c6945b15 | aurel32 | DPRINTF("returning irq %s\n", irq_names[irq]);
|
488 | 4ce7ff6e | aurel32 | val = (irq + 1) << 2; |
489 | 4ce7ff6e | aurel32 | break;
|
490 | 4ce7ff6e | aurel32 | } |
491 | 4ce7ff6e | aurel32 | irq++; |
492 | 4ce7ff6e | aurel32 | pending >>= 1;
|
493 | 4ce7ff6e | aurel32 | } |
494 | 4ce7ff6e | aurel32 | break;
|
495 | 4ce7ff6e | aurel32 | } |
496 | c6945b15 | aurel32 | /* Local bus int enable mask */
|
497 | c6945b15 | aurel32 | case 0x02: |
498 | c6945b15 | aurel32 | val = s->imr_jazz; |
499 | c6945b15 | aurel32 | break;
|
500 | 4ce7ff6e | aurel32 | default:
|
501 | c6945b15 | aurel32 | RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr); |
502 | c6945b15 | aurel32 | val = 0;
|
503 | 4ce7ff6e | aurel32 | } |
504 | 4ce7ff6e | aurel32 | |
505 | c6945b15 | aurel32 | DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr); |
506 | 4ce7ff6e | aurel32 | |
507 | 4ce7ff6e | aurel32 | return val;
|
508 | 4ce7ff6e | aurel32 | } |
509 | 4ce7ff6e | aurel32 | |
510 | c6945b15 | aurel32 | static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr) |
511 | 4ce7ff6e | aurel32 | { |
512 | 4ce7ff6e | aurel32 | uint32_t v; |
513 | c6945b15 | aurel32 | v = jazzio_readw(opaque, addr & ~0x1);
|
514 | c6945b15 | aurel32 | return (v >> (8 * (addr & 0x1))) & 0xff; |
515 | 4ce7ff6e | aurel32 | } |
516 | 4ce7ff6e | aurel32 | |
517 | c6945b15 | aurel32 | static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr) |
518 | 4ce7ff6e | aurel32 | { |
519 | 4ce7ff6e | aurel32 | uint32_t v; |
520 | c6945b15 | aurel32 | v = jazzio_readw(opaque, addr); |
521 | c6945b15 | aurel32 | v |= jazzio_readw(opaque, addr + 2) << 16; |
522 | 4ce7ff6e | aurel32 | return v;
|
523 | 4ce7ff6e | aurel32 | } |
524 | 4ce7ff6e | aurel32 | |
525 | c6945b15 | aurel32 | static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
526 | 4ce7ff6e | aurel32 | { |
527 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
528 | 4ce7ff6e | aurel32 | addr &= 0xfff;
|
529 | 4ce7ff6e | aurel32 | |
530 | c6945b15 | aurel32 | DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr); |
531 | 4ce7ff6e | aurel32 | |
532 | 4ce7ff6e | aurel32 | switch (addr) {
|
533 | 4ce7ff6e | aurel32 | /* Local bus int enable mask */
|
534 | 4ce7ff6e | aurel32 | case 0x02: |
535 | c6945b15 | aurel32 | s->imr_jazz = val; |
536 | c6945b15 | aurel32 | update_jazz_irq(s); |
537 | 4ce7ff6e | aurel32 | break;
|
538 | 4ce7ff6e | aurel32 | default:
|
539 | c6945b15 | aurel32 | RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr); |
540 | 4ce7ff6e | aurel32 | break;
|
541 | 4ce7ff6e | aurel32 | } |
542 | 4ce7ff6e | aurel32 | } |
543 | 4ce7ff6e | aurel32 | |
544 | c6945b15 | aurel32 | static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
545 | 4ce7ff6e | aurel32 | { |
546 | c6945b15 | aurel32 | uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
|
547 | c6945b15 | aurel32 | |
548 | c6945b15 | aurel32 | switch (addr & 1) { |
549 | c6945b15 | aurel32 | case 0: |
550 | c6945b15 | aurel32 | val = val | (old_val & 0xff00);
|
551 | c6945b15 | aurel32 | break;
|
552 | c6945b15 | aurel32 | case 1: |
553 | c6945b15 | aurel32 | val = (val << 8) | (old_val & 0x00ff); |
554 | c6945b15 | aurel32 | break;
|
555 | c6945b15 | aurel32 | } |
556 | c6945b15 | aurel32 | jazzio_writew(opaque, addr & ~0x1, val);
|
557 | 4ce7ff6e | aurel32 | } |
558 | 4ce7ff6e | aurel32 | |
559 | c6945b15 | aurel32 | static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
560 | 4ce7ff6e | aurel32 | { |
561 | c6945b15 | aurel32 | jazzio_writew(opaque, addr, val & 0xffff);
|
562 | c6945b15 | aurel32 | jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff); |
563 | 4ce7ff6e | aurel32 | } |
564 | 4ce7ff6e | aurel32 | |
565 | c6945b15 | aurel32 | static CPUReadMemoryFunc *jazzio_read[3] = { |
566 | c6945b15 | aurel32 | jazzio_readb, |
567 | c6945b15 | aurel32 | jazzio_readw, |
568 | c6945b15 | aurel32 | jazzio_readl, |
569 | 4ce7ff6e | aurel32 | }; |
570 | 4ce7ff6e | aurel32 | |
571 | c6945b15 | aurel32 | static CPUWriteMemoryFunc *jazzio_write[3] = { |
572 | c6945b15 | aurel32 | jazzio_writeb, |
573 | c6945b15 | aurel32 | jazzio_writew, |
574 | c6945b15 | aurel32 | jazzio_writel, |
575 | 4ce7ff6e | aurel32 | }; |
576 | 4ce7ff6e | aurel32 | |
577 | 4ce7ff6e | aurel32 | static void rc4030_reset(void *opaque) |
578 | 4ce7ff6e | aurel32 | { |
579 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
580 | 4ce7ff6e | aurel32 | int i;
|
581 | 4ce7ff6e | aurel32 | |
582 | c6945b15 | aurel32 | s->config = 0x410; /* some boards seem to accept 0x104 too */ |
583 | 4ce7ff6e | aurel32 | s->invalid_address_register = 0;
|
584 | 4ce7ff6e | aurel32 | |
585 | 4ce7ff6e | aurel32 | memset(s->dma_regs, 0, sizeof(s->dma_regs)); |
586 | 4ce7ff6e | aurel32 | s->dma_tl_base = s->dma_tl_limit = 0;
|
587 | 4ce7ff6e | aurel32 | |
588 | 4ce7ff6e | aurel32 | s->remote_failed_address = s->memory_failed_address = 0;
|
589 | 4ce7ff6e | aurel32 | s->cache_ptag = s->cache_ltag = 0;
|
590 | 4ce7ff6e | aurel32 | s->cache_bmask = s->cache_bwin = 0;
|
591 | 4ce7ff6e | aurel32 | |
592 | 4ce7ff6e | aurel32 | s->offset210 = 0x18186;
|
593 | 4ce7ff6e | aurel32 | s->nvram_protect = 7;
|
594 | 4ce7ff6e | aurel32 | s->offset238 = 7;
|
595 | 4ce7ff6e | aurel32 | for (i = 0; i < 15; i++) |
596 | 4ce7ff6e | aurel32 | s->rem_speed[i] = 7;
|
597 | 4ce7ff6e | aurel32 | s->imr_jazz = s->isr_jazz = 0;
|
598 | 4ce7ff6e | aurel32 | |
599 | 4ce7ff6e | aurel32 | s->itr = 0;
|
600 | 4ce7ff6e | aurel32 | |
601 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
602 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->jazz_bus_irq); |
603 | 4ce7ff6e | aurel32 | } |
604 | 4ce7ff6e | aurel32 | |
605 | c6945b15 | aurel32 | static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write) |
606 | c6945b15 | aurel32 | { |
607 | c6945b15 | aurel32 | rc4030State *s = opaque; |
608 | c6945b15 | aurel32 | target_phys_addr_t entry_addr; |
609 | c6945b15 | aurel32 | target_phys_addr_t dma_addr, phys_addr; |
610 | c6945b15 | aurel32 | dma_pagetable_entry entry; |
611 | c6945b15 | aurel32 | int index, dev_to_mem;
|
612 | c6945b15 | aurel32 | int ncpy, i;
|
613 | c6945b15 | aurel32 | |
614 | c6945b15 | aurel32 | s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); |
615 | c6945b15 | aurel32 | |
616 | c6945b15 | aurel32 | /* Check DMA channel consistency */
|
617 | c6945b15 | aurel32 | dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1; |
618 | c6945b15 | aurel32 | if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
|
619 | c6945b15 | aurel32 | (is_write != dev_to_mem)) { |
620 | c6945b15 | aurel32 | s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; |
621 | c6945b15 | aurel32 | return;
|
622 | c6945b15 | aurel32 | } |
623 | c6945b15 | aurel32 | |
624 | c6945b15 | aurel32 | if (len > s->dma_regs[n][DMA_REG_COUNT])
|
625 | c6945b15 | aurel32 | len = s->dma_regs[n][DMA_REG_COUNT]; |
626 | c6945b15 | aurel32 | |
627 | c6945b15 | aurel32 | dma_addr = s->dma_regs[n][DMA_REG_ADDRESS]; |
628 | c6945b15 | aurel32 | i = 0;
|
629 | c6945b15 | aurel32 | for (;;) {
|
630 | c6945b15 | aurel32 | if (i == len) {
|
631 | c6945b15 | aurel32 | s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR; |
632 | c6945b15 | aurel32 | break;
|
633 | c6945b15 | aurel32 | } |
634 | c6945b15 | aurel32 | |
635 | c6945b15 | aurel32 | ncpy = DMA_PAGESIZE - (dma_addr & (DMA_PAGESIZE - 1));
|
636 | c6945b15 | aurel32 | if (ncpy > len - i)
|
637 | c6945b15 | aurel32 | ncpy = len - i; |
638 | c6945b15 | aurel32 | |
639 | c6945b15 | aurel32 | /* Get DMA translation table entry */
|
640 | c6945b15 | aurel32 | index = dma_addr / DMA_PAGESIZE; |
641 | c6945b15 | aurel32 | if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) { |
642 | c6945b15 | aurel32 | s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; |
643 | c6945b15 | aurel32 | break;
|
644 | c6945b15 | aurel32 | } |
645 | c6945b15 | aurel32 | entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
|
646 | c6945b15 | aurel32 | /* XXX: not sure. should we really use only lowest bits? */
|
647 | c6945b15 | aurel32 | entry_addr &= 0x7fffffff;
|
648 | c6945b15 | aurel32 | cpu_physical_memory_rw(entry_addr, (uint8_t *)&entry, sizeof(entry), 0); |
649 | c6945b15 | aurel32 | |
650 | c6945b15 | aurel32 | /* Read/write data at right place */
|
651 | c6945b15 | aurel32 | phys_addr = entry.frame + (dma_addr & (DMA_PAGESIZE - 1));
|
652 | c6945b15 | aurel32 | cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write); |
653 | c6945b15 | aurel32 | |
654 | c6945b15 | aurel32 | i += ncpy; |
655 | c6945b15 | aurel32 | dma_addr += ncpy; |
656 | c6945b15 | aurel32 | s->dma_regs[n][DMA_REG_COUNT] -= ncpy; |
657 | c6945b15 | aurel32 | } |
658 | c6945b15 | aurel32 | |
659 | c6945b15 | aurel32 | #ifdef DEBUG_RC4030_DMA
|
660 | c6945b15 | aurel32 | { |
661 | c6945b15 | aurel32 | int i, j;
|
662 | c6945b15 | aurel32 | printf("rc4030 dma: Copying %d bytes %s host %p\n",
|
663 | c6945b15 | aurel32 | len, is_write ? "from" : "to", buf); |
664 | c6945b15 | aurel32 | for (i = 0; i < len; i += 16) { |
665 | c6945b15 | aurel32 | int n = min(16, len - i); |
666 | c6945b15 | aurel32 | for (j = 0; j < n; j++) |
667 | c6945b15 | aurel32 | printf("%02x ", buf[i + j]);
|
668 | c6945b15 | aurel32 | while (j++ < 16) |
669 | c6945b15 | aurel32 | printf(" ");
|
670 | c6945b15 | aurel32 | printf("| ");
|
671 | c6945b15 | aurel32 | for (j = 0; j < n; j++) |
672 | c6945b15 | aurel32 | printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.'); |
673 | c6945b15 | aurel32 | printf("\n");
|
674 | c6945b15 | aurel32 | } |
675 | c6945b15 | aurel32 | } |
676 | c6945b15 | aurel32 | #endif
|
677 | c6945b15 | aurel32 | } |
678 | c6945b15 | aurel32 | |
679 | c6945b15 | aurel32 | struct rc4030DMAState {
|
680 | c6945b15 | aurel32 | void *opaque;
|
681 | c6945b15 | aurel32 | int n;
|
682 | c6945b15 | aurel32 | }; |
683 | c6945b15 | aurel32 | |
684 | c6945b15 | aurel32 | static void rc4030_dma_read(void *dma, uint8_t *buf, int len) |
685 | c6945b15 | aurel32 | { |
686 | c6945b15 | aurel32 | rc4030_dma s = dma; |
687 | c6945b15 | aurel32 | rc4030_do_dma(s->opaque, s->n, buf, len, 0);
|
688 | c6945b15 | aurel32 | } |
689 | c6945b15 | aurel32 | |
690 | c6945b15 | aurel32 | static void rc4030_dma_write(void *dma, uint8_t *buf, int len) |
691 | c6945b15 | aurel32 | { |
692 | c6945b15 | aurel32 | rc4030_dma s = dma; |
693 | c6945b15 | aurel32 | rc4030_do_dma(s->opaque, s->n, buf, len, 1);
|
694 | c6945b15 | aurel32 | } |
695 | c6945b15 | aurel32 | |
696 | c6945b15 | aurel32 | static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) |
697 | c6945b15 | aurel32 | { |
698 | c6945b15 | aurel32 | rc4030_dma *s; |
699 | c6945b15 | aurel32 | struct rc4030DMAState *p;
|
700 | c6945b15 | aurel32 | int i;
|
701 | c6945b15 | aurel32 | |
702 | c6945b15 | aurel32 | s = (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n);
|
703 | c6945b15 | aurel32 | p = (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAState) * n); |
704 | c6945b15 | aurel32 | for (i = 0; i < n; i++) { |
705 | c6945b15 | aurel32 | p->opaque = opaque; |
706 | c6945b15 | aurel32 | p->n = i; |
707 | c6945b15 | aurel32 | s[i] = p; |
708 | c6945b15 | aurel32 | p++; |
709 | c6945b15 | aurel32 | } |
710 | c6945b15 | aurel32 | return s;
|
711 | c6945b15 | aurel32 | } |
712 | c6945b15 | aurel32 | |
713 | c6945b15 | aurel32 | qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus, |
714 | c6945b15 | aurel32 | rc4030_dma **dmas, |
715 | c6945b15 | aurel32 | rc4030_dma_function *dma_read, rc4030_dma_function *dma_write) |
716 | 4ce7ff6e | aurel32 | { |
717 | 4ce7ff6e | aurel32 | rc4030State *s; |
718 | c6945b15 | aurel32 | int s_chipset, s_jazzio;
|
719 | 4ce7ff6e | aurel32 | |
720 | 4ce7ff6e | aurel32 | s = qemu_mallocz(sizeof(rc4030State));
|
721 | 4ce7ff6e | aurel32 | if (!s)
|
722 | 4ce7ff6e | aurel32 | return NULL; |
723 | 4ce7ff6e | aurel32 | |
724 | c6945b15 | aurel32 | *dmas = rc4030_allocate_dmas(s, 4);
|
725 | c6945b15 | aurel32 | *dma_read = rc4030_dma_read; |
726 | c6945b15 | aurel32 | *dma_write = rc4030_dma_write; |
727 | c6945b15 | aurel32 | |
728 | 4ce7ff6e | aurel32 | s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s); |
729 | 4ce7ff6e | aurel32 | s->timer_irq = timer; |
730 | 4ce7ff6e | aurel32 | s->jazz_bus_irq = jazz_bus; |
731 | 4ce7ff6e | aurel32 | |
732 | 4ce7ff6e | aurel32 | qemu_register_reset(rc4030_reset, s); |
733 | 4ce7ff6e | aurel32 | rc4030_reset(s); |
734 | 4ce7ff6e | aurel32 | |
735 | 4ce7ff6e | aurel32 | s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
|
736 | 4ce7ff6e | aurel32 | cpu_register_physical_memory(0x80000000, 0x300, s_chipset); |
737 | c6945b15 | aurel32 | s_jazzio = cpu_register_io_memory(0, jazzio_read, jazzio_write, s);
|
738 | c6945b15 | aurel32 | cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio); |
739 | 4ce7ff6e | aurel32 | |
740 | 4ce7ff6e | aurel32 | return qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16); |
741 | 4ce7ff6e | aurel32 | } |