Revision e0bcb9ca target-sh4/cpu.h

b/target-sh4/cpu.h
167 167 
void do_interrupt(CPUSH4State * env);
168 168 

  		





  169
  169
  
    
void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));


  		





  
  170
  
    
void cpu_sh4_invalidate_tlb(CPUSH4State *s);


  		





  170
  171
  
    
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,


  		





  171
  172
  
    
				    uint32_t mem_value);


  		





  172
  173
  
    

  		





  ......




  222
  223
  
    
/* MMU control register */


  		





  223
  224
  
    
#define MMUCR    0x1F000010


  		





  224
  225
  
    
#define MMUCR_AT (1<<0)


  		





  
  226
  
    
#define MMUCR_TI (1<<2)


  		





  225
  227
  
    
#define MMUCR_SV (1<<8)


  		





  226
  228
  
    
#define MMUCR_URC_BITS (6)


  		





  227
  229
  
    
#define MMUCR_URC_OFFSET (10)


  		












Also available in:
  Unified diff