Revision e0c84da7 target-mips/translate.c
| b/target-mips/translate.c | ||
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| 358 | 358 |
#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F) |
| 359 | 359 |
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| 360 | 360 |
#define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) |
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#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) |
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enum {
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OPC_MFC2 = (0x00 << 21) | OPC_CP2, |
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OPC_DMFC2 = (0x01 << 21) | OPC_CP2, |
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OPC_CFC2 = (0x02 << 21) | OPC_CP2, |
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OPC_MFHC2 = (0x03 << 21) | OPC_CP2, |
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OPC_MTC2 = (0x04 << 21) | OPC_CP2, |
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OPC_DMTC2 = (0x05 << 21) | OPC_CP2, |
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OPC_CTC2 = (0x06 << 21) | OPC_CP2, |
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OPC_MTHC2 = (0x07 << 21) | OPC_CP2, |
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OPC_BC2 = (0x08 << 21) | OPC_CP2, |
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}; |
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#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F) |
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enum {
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OPC_LWXC1 = 0x00 | OPC_CP3, |
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OPC_LDXC1 = 0x01 | OPC_CP3, |
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OPC_LUXC1 = 0x05 | OPC_CP3, |
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OPC_SWXC1 = 0x08 | OPC_CP3, |
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OPC_SDXC1 = 0x09 | OPC_CP3, |
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OPC_SUXC1 = 0x0D | OPC_CP3, |
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OPC_PREFX = 0x0F | OPC_CP3, |
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OPC_ALNV_PS = 0x1E | OPC_CP3, |
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OPC_MADD_S = 0x20 | OPC_CP3, |
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OPC_MADD_D = 0x21 | OPC_CP3, |
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OPC_MADD_PS = 0x26 | OPC_CP3, |
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OPC_MSUB_S = 0x28 | OPC_CP3, |
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OPC_MSUB_D = 0x29 | OPC_CP3, |
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OPC_MSUB_PS = 0x2E | OPC_CP3, |
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OPC_NMADD_S = 0x30 | OPC_CP3, |
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OPC_NMADD_D = 0x32 | OPC_CP3, |
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OPC_NMADD_PS= 0x36 | OPC_CP3, |
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OPC_NMSUB_S = 0x38 | OPC_CP3, |
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OPC_NMSUB_D = 0x39 | OPC_CP3, |
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OPC_NMSUB_PS= 0x3E | OPC_CP3, |
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}; |
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| 362 | 399 |
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const unsigned char *regnames[] = |
| 364 | 401 |
{ "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
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| ... | ... | |
| 5019 | 5056 |
gen_op_cp1_enabled(); |
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op1 = MASK_CP3(ctx->opcode); |
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switch (op1) {
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case OPC_PREFX: |
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/* treat as noop */ |
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break; |
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/* Not implemented */ |
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default: |
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generate_exception (ctx, EXCP_RI); |
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