root / hw / mc146818rtc.c @ e0ca7b94
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/*
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* QEMU MC146818 RTC emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "pc.h" |
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#include "isa.h" |
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#include "hpet_emul.h" |
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//#define DEBUG_CMOS
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#define RTC_SECONDS 0 |
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#define RTC_SECONDS_ALARM 1 |
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#define RTC_MINUTES 2 |
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#define RTC_MINUTES_ALARM 3 |
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#define RTC_HOURS 4 |
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#define RTC_HOURS_ALARM 5 |
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#define RTC_ALARM_DONT_CARE 0xC0 |
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|
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#define RTC_DAY_OF_WEEK 6 |
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#define RTC_DAY_OF_MONTH 7 |
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#define RTC_MONTH 8 |
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#define RTC_YEAR 9 |
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|
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#define RTC_REG_A 10 |
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#define RTC_REG_B 11 |
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#define RTC_REG_C 12 |
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#define RTC_REG_D 13 |
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|
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#define REG_A_UIP 0x80 |
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|
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#define REG_B_SET 0x80 |
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#define REG_B_PIE 0x40 |
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#define REG_B_AIE 0x20 |
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#define REG_B_UIE 0x10 |
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#define REG_B_SQWE 0x08 |
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#define REG_B_DM 0x04 |
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#define REG_C_UF 0x10 |
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#define REG_C_IRQF 0x80 |
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#define REG_C_PF 0x40 |
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#define REG_C_AF 0x20 |
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struct RTCState {
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ISADevice dev; |
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uint8_t cmos_data[128];
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uint8_t cmos_index; |
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struct tm current_tm;
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int32_t base_year; |
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qemu_irq irq; |
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qemu_irq sqw_irq; |
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int it_shift;
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/* periodic timer */
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QEMUTimer *periodic_timer; |
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int64_t next_periodic_time; |
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/* second update */
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int64_t next_second_time; |
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uint32_t irq_coalesced; |
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uint32_t period; |
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QEMUTimer *coalesced_timer; |
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QEMUTimer *second_timer; |
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QEMUTimer *second_timer2; |
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}; |
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static void rtc_irq_raise(qemu_irq irq) |
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{ |
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/* When HPET is operating in legacy mode, RTC interrupts are disabled
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* We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
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* mode is established while interrupt is raised. We want it to
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* be lowered in any case
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*/
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#if defined TARGET_I386
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if (!hpet_in_legacy_mode())
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#endif
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qemu_irq_raise(irq); |
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} |
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static void rtc_set_time(RTCState *s); |
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static void rtc_copy_date(RTCState *s); |
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#ifdef TARGET_I386
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static void rtc_coalesced_timer_update(RTCState *s) |
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{ |
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if (s->irq_coalesced == 0) { |
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qemu_del_timer(s->coalesced_timer); |
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} else {
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/* divide each RTC interval to 2 - 8 smaller intervals */
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int c = MIN(s->irq_coalesced, 7) + 1; |
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int64_t next_clock = qemu_get_clock(rtc_clock) + |
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muldiv64(s->period / c, get_ticks_per_sec(), 32768);
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qemu_mod_timer(s->coalesced_timer, next_clock); |
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} |
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} |
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static void rtc_coalesced_timer(void *opaque) |
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{ |
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RTCState *s = opaque; |
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if (s->irq_coalesced != 0) { |
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apic_reset_irq_delivered(); |
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s->cmos_data[RTC_REG_C] |= 0xc0;
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rtc_irq_raise(s->irq); |
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if (apic_get_irq_delivered()) {
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s->irq_coalesced--; |
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} |
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} |
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rtc_coalesced_timer_update(s); |
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} |
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#endif
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static void rtc_timer_update(RTCState *s, int64_t current_time) |
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{ |
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int period_code, period;
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int64_t cur_clock, next_irq_clock; |
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int enable_pie;
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period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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#if defined TARGET_I386
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/* disable periodic timer if hpet is in legacy mode, since interrupts are
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* disabled anyway.
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*/
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enable_pie = !hpet_in_legacy_mode(); |
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#else
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enable_pie = 1;
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#endif
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if (period_code != 0 |
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&& (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) |
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|| ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
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if (period_code <= 2) |
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period_code += 7;
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/* period in 32 Khz cycles */
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period = 1 << (period_code - 1); |
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#ifdef TARGET_I386
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if(period != s->period)
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s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
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s->period = period; |
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#endif
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/* compute 32 khz clock */
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cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
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next_irq_clock = (cur_clock & ~(period - 1)) + period;
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s->next_periodic_time = |
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muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; |
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qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
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} else {
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#ifdef TARGET_I386
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s->irq_coalesced = 0;
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#endif
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qemu_del_timer(s->periodic_timer); |
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} |
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} |
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static void rtc_periodic_timer(void *opaque) |
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{ |
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RTCState *s = opaque; |
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rtc_timer_update(s, s->next_periodic_time); |
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if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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s->cmos_data[RTC_REG_C] |= 0xc0;
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#ifdef TARGET_I386
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if(rtc_td_hack) {
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apic_reset_irq_delivered(); |
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rtc_irq_raise(s->irq); |
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if (!apic_get_irq_delivered()) {
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s->irq_coalesced++; |
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rtc_coalesced_timer_update(s); |
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} |
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} else
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#endif
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rtc_irq_raise(s->irq); |
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} |
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if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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/* Not square wave at all but we don't want 2048Hz interrupts!
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Must be seen as a pulse. */
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qemu_irq_raise(s->sqw_irq); |
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} |
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} |
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static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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RTCState *s = opaque; |
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if ((addr & 1) == 0) { |
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s->cmos_index = data & 0x7f;
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} else {
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#ifdef DEBUG_CMOS
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printf("cmos: write index=0x%02x val=0x%02x\n",
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s->cmos_index, data); |
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#endif
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switch(s->cmos_index) {
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case RTC_SECONDS_ALARM:
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case RTC_MINUTES_ALARM:
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case RTC_HOURS_ALARM:
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/* XXX: not supported */
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s->cmos_data[s->cmos_index] = data; |
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break;
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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s->cmos_data[s->cmos_index] = data; |
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/* if in set mode, do not update the time */
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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rtc_set_time(s); |
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} |
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break;
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case RTC_REG_A:
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/* UIP bit is read only */
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s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
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(s->cmos_data[RTC_REG_A] & REG_A_UIP); |
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rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
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break;
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case RTC_REG_B:
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if (data & REG_B_SET) {
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/* set mode: reset UIP mode */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
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data &= ~REG_B_UIE; |
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} else {
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/* if disabling set mode, update the time */
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if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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rtc_set_time(s); |
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} |
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} |
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s->cmos_data[RTC_REG_B] = data; |
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rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
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break;
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case RTC_REG_C:
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case RTC_REG_D:
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/* cannot write to them */
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break;
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default:
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s->cmos_data[s->cmos_index] = data; |
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break;
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} |
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} |
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} |
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static inline int to_bcd(RTCState *s, int a) |
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{ |
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return a;
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} else {
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return ((a / 10) << 4) | (a % 10); |
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} |
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} |
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static inline int from_bcd(RTCState *s, int a) |
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{ |
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return a;
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} else {
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return ((a >> 4) * 10) + (a & 0x0f); |
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} |
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} |
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static void rtc_set_time(RTCState *s) |
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{ |
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struct tm *tm = &s->current_tm;
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tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]); |
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tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]); |
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tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
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(s->cmos_data[RTC_HOURS] & 0x80)) {
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tm->tm_hour += 12;
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} |
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tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
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tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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} |
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static void rtc_copy_date(RTCState *s) |
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{ |
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const struct tm *tm = &s->current_tm; |
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int year;
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s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec); |
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s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min); |
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if (s->cmos_data[RTC_REG_B] & 0x02) { |
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/* 24 hour format */
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s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour); |
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} else {
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/* 12 hour format */
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s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
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if (tm->tm_hour >= 12) |
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s->cmos_data[RTC_HOURS] |= 0x80;
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} |
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s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1);
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s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday); |
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s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
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year = (tm->tm_year - s->base_year) % 100;
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if (year < 0) |
318 |
year += 100;
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s->cmos_data[RTC_YEAR] = to_bcd(s, year); |
320 |
} |
321 |
|
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/* month is between 0 and 11. */
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static int get_days_in_month(int month, int year) |
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{ |
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static const int days_tab[12] = { |
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31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
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}; |
328 |
int d;
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if ((unsigned )month >= 12) |
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return 31; |
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d = days_tab[month]; |
332 |
if (month == 1) { |
333 |
if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
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d++; |
335 |
} |
336 |
return d;
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} |
338 |
|
339 |
/* update 'tm' to the next second */
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static void rtc_next_second(struct tm *tm) |
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{ |
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int days_in_month;
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tm->tm_sec++; |
345 |
if ((unsigned)tm->tm_sec >= 60) { |
346 |
tm->tm_sec = 0;
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tm->tm_min++; |
348 |
if ((unsigned)tm->tm_min >= 60) { |
349 |
tm->tm_min = 0;
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tm->tm_hour++; |
351 |
if ((unsigned)tm->tm_hour >= 24) { |
352 |
tm->tm_hour = 0;
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/* next day */
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tm->tm_wday++; |
355 |
if ((unsigned)tm->tm_wday >= 7) |
356 |
tm->tm_wday = 0;
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days_in_month = get_days_in_month(tm->tm_mon, |
358 |
tm->tm_year + 1900);
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tm->tm_mday++; |
360 |
if (tm->tm_mday < 1) { |
361 |
tm->tm_mday = 1;
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362 |
} else if (tm->tm_mday > days_in_month) { |
363 |
tm->tm_mday = 1;
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364 |
tm->tm_mon++; |
365 |
if (tm->tm_mon >= 12) { |
366 |
tm->tm_mon = 0;
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367 |
tm->tm_year++; |
368 |
} |
369 |
} |
370 |
} |
371 |
} |
372 |
} |
373 |
} |
374 |
|
375 |
|
376 |
static void rtc_update_second(void *opaque) |
377 |
{ |
378 |
RTCState *s = opaque; |
379 |
int64_t delay; |
380 |
|
381 |
/* if the oscillator is not in normal operation, we do not update */
|
382 |
if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
383 |
s->next_second_time += get_ticks_per_sec(); |
384 |
qemu_mod_timer(s->second_timer, s->next_second_time); |
385 |
} else {
|
386 |
rtc_next_second(&s->current_tm); |
387 |
|
388 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
389 |
/* update in progress bit */
|
390 |
s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
391 |
} |
392 |
/* should be 244 us = 8 / 32768 seconds, but currently the
|
393 |
timers do not have the necessary resolution. */
|
394 |
delay = (get_ticks_per_sec() * 1) / 100; |
395 |
if (delay < 1) |
396 |
delay = 1;
|
397 |
qemu_mod_timer(s->second_timer2, |
398 |
s->next_second_time + delay); |
399 |
} |
400 |
} |
401 |
|
402 |
static void rtc_update_second2(void *opaque) |
403 |
{ |
404 |
RTCState *s = opaque; |
405 |
|
406 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
407 |
rtc_copy_date(s); |
408 |
} |
409 |
|
410 |
/* check alarm */
|
411 |
if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
412 |
if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
413 |
s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
414 |
((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
415 |
s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
416 |
((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
417 |
s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
418 |
|
419 |
s->cmos_data[RTC_REG_C] |= 0xa0;
|
420 |
rtc_irq_raise(s->irq); |
421 |
} |
422 |
} |
423 |
|
424 |
/* update ended interrupt */
|
425 |
s->cmos_data[RTC_REG_C] |= REG_C_UF; |
426 |
if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
|
427 |
s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
428 |
rtc_irq_raise(s->irq); |
429 |
} |
430 |
|
431 |
/* clear update in progress bit */
|
432 |
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
433 |
|
434 |
s->next_second_time += get_ticks_per_sec(); |
435 |
qemu_mod_timer(s->second_timer, s->next_second_time); |
436 |
} |
437 |
|
438 |
static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
439 |
{ |
440 |
RTCState *s = opaque; |
441 |
int ret;
|
442 |
if ((addr & 1) == 0) { |
443 |
return 0xff; |
444 |
} else {
|
445 |
switch(s->cmos_index) {
|
446 |
case RTC_SECONDS:
|
447 |
case RTC_MINUTES:
|
448 |
case RTC_HOURS:
|
449 |
case RTC_DAY_OF_WEEK:
|
450 |
case RTC_DAY_OF_MONTH:
|
451 |
case RTC_MONTH:
|
452 |
case RTC_YEAR:
|
453 |
ret = s->cmos_data[s->cmos_index]; |
454 |
break;
|
455 |
case RTC_REG_A:
|
456 |
ret = s->cmos_data[s->cmos_index]; |
457 |
break;
|
458 |
case RTC_REG_C:
|
459 |
ret = s->cmos_data[s->cmos_index]; |
460 |
qemu_irq_lower(s->irq); |
461 |
s->cmos_data[RTC_REG_C] = 0x00;
|
462 |
break;
|
463 |
default:
|
464 |
ret = s->cmos_data[s->cmos_index]; |
465 |
break;
|
466 |
} |
467 |
#ifdef DEBUG_CMOS
|
468 |
printf("cmos: read index=0x%02x val=0x%02x\n",
|
469 |
s->cmos_index, ret); |
470 |
#endif
|
471 |
return ret;
|
472 |
} |
473 |
} |
474 |
|
475 |
void rtc_set_memory(RTCState *s, int addr, int val) |
476 |
{ |
477 |
if (addr >= 0 && addr <= 127) |
478 |
s->cmos_data[addr] = val; |
479 |
} |
480 |
|
481 |
void rtc_set_date(RTCState *s, const struct tm *tm) |
482 |
{ |
483 |
s->current_tm = *tm; |
484 |
rtc_copy_date(s); |
485 |
} |
486 |
|
487 |
/* PC cmos mappings */
|
488 |
#define REG_IBM_CENTURY_BYTE 0x32 |
489 |
#define REG_IBM_PS2_CENTURY_BYTE 0x37 |
490 |
|
491 |
static void rtc_set_date_from_host(RTCState *s) |
492 |
{ |
493 |
struct tm tm;
|
494 |
int val;
|
495 |
|
496 |
/* set the CMOS date */
|
497 |
qemu_get_timedate(&tm, 0);
|
498 |
rtc_set_date(s, &tm); |
499 |
|
500 |
val = to_bcd(s, (tm.tm_year / 100) + 19); |
501 |
rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
502 |
rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); |
503 |
} |
504 |
|
505 |
static int rtc_post_load(void *opaque, int version_id) |
506 |
{ |
507 |
#ifdef TARGET_I386
|
508 |
RTCState *s = opaque; |
509 |
|
510 |
if (version_id >= 2) { |
511 |
if (rtc_td_hack) {
|
512 |
rtc_coalesced_timer_update(s); |
513 |
} |
514 |
} |
515 |
#endif
|
516 |
return 0; |
517 |
} |
518 |
|
519 |
static const VMStateDescription vmstate_rtc = { |
520 |
.name = "mc146818rtc",
|
521 |
.version_id = 2,
|
522 |
.minimum_version_id = 1,
|
523 |
.minimum_version_id_old = 1,
|
524 |
.post_load = rtc_post_load, |
525 |
.fields = (VMStateField []) { |
526 |
VMSTATE_BUFFER(cmos_data, RTCState), |
527 |
VMSTATE_UINT8(cmos_index, RTCState), |
528 |
VMSTATE_INT32(current_tm.tm_sec, RTCState), |
529 |
VMSTATE_INT32(current_tm.tm_min, RTCState), |
530 |
VMSTATE_INT32(current_tm.tm_hour, RTCState), |
531 |
VMSTATE_INT32(current_tm.tm_wday, RTCState), |
532 |
VMSTATE_INT32(current_tm.tm_mday, RTCState), |
533 |
VMSTATE_INT32(current_tm.tm_mon, RTCState), |
534 |
VMSTATE_INT32(current_tm.tm_year, RTCState), |
535 |
VMSTATE_TIMER(periodic_timer, RTCState), |
536 |
VMSTATE_INT64(next_periodic_time, RTCState), |
537 |
VMSTATE_INT64(next_second_time, RTCState), |
538 |
VMSTATE_TIMER(second_timer, RTCState), |
539 |
VMSTATE_TIMER(second_timer2, RTCState), |
540 |
VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
541 |
VMSTATE_UINT32_V(period, RTCState, 2),
|
542 |
VMSTATE_END_OF_LIST() |
543 |
} |
544 |
}; |
545 |
|
546 |
static void rtc_reset(void *opaque) |
547 |
{ |
548 |
RTCState *s = opaque; |
549 |
|
550 |
s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
551 |
s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); |
552 |
|
553 |
qemu_irq_lower(s->irq); |
554 |
|
555 |
#ifdef TARGET_I386
|
556 |
if (rtc_td_hack)
|
557 |
s->irq_coalesced = 0;
|
558 |
#endif
|
559 |
} |
560 |
|
561 |
static int rtc_initfn(ISADevice *dev) |
562 |
{ |
563 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
564 |
int base = 0x70; |
565 |
int isairq = 8; |
566 |
|
567 |
isa_init_irq(dev, &s->irq, isairq); |
568 |
|
569 |
s->cmos_data[RTC_REG_A] = 0x26;
|
570 |
s->cmos_data[RTC_REG_B] = 0x02;
|
571 |
s->cmos_data[RTC_REG_C] = 0x00;
|
572 |
s->cmos_data[RTC_REG_D] = 0x80;
|
573 |
|
574 |
rtc_set_date_from_host(s); |
575 |
|
576 |
s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); |
577 |
#ifdef TARGET_I386
|
578 |
if (rtc_td_hack)
|
579 |
s->coalesced_timer = |
580 |
qemu_new_timer(rtc_clock, rtc_coalesced_timer, s); |
581 |
#endif
|
582 |
s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); |
583 |
s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); |
584 |
|
585 |
s->next_second_time = |
586 |
qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; |
587 |
qemu_mod_timer(s->second_timer2, s->next_second_time); |
588 |
|
589 |
register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
590 |
register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
591 |
|
592 |
vmstate_register(base, &vmstate_rtc, s); |
593 |
qemu_register_reset(rtc_reset, s); |
594 |
return 0; |
595 |
} |
596 |
|
597 |
RTCState *rtc_init(int base_year)
|
598 |
{ |
599 |
ISADevice *dev; |
600 |
|
601 |
dev = isa_create("mc146818rtc");
|
602 |
qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
603 |
qdev_init_nofail(&dev->qdev); |
604 |
return DO_UPCAST(RTCState, dev, dev);
|
605 |
} |
606 |
|
607 |
static ISADeviceInfo mc146818rtc_info = {
|
608 |
.qdev.name = "mc146818rtc",
|
609 |
.qdev.size = sizeof(RTCState),
|
610 |
.qdev.no_user = 1,
|
611 |
.init = rtc_initfn, |
612 |
.qdev.props = (Property[]) { |
613 |
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), |
614 |
DEFINE_PROP_END_OF_LIST(), |
615 |
} |
616 |
}; |
617 |
|
618 |
static void mc146818rtc_register(void) |
619 |
{ |
620 |
isa_qdev_register(&mc146818rtc_info); |
621 |
} |
622 |
device_init(mc146818rtc_register) |
623 |
|
624 |
/* Memory mapped interface */
|
625 |
static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr) |
626 |
{ |
627 |
RTCState *s = opaque; |
628 |
|
629 |
return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF; |
630 |
} |
631 |
|
632 |
static void cmos_mm_writeb (void *opaque, |
633 |
target_phys_addr_t addr, uint32_t value) |
634 |
{ |
635 |
RTCState *s = opaque; |
636 |
|
637 |
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
|
638 |
} |
639 |
|
640 |
static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr) |
641 |
{ |
642 |
RTCState *s = opaque; |
643 |
uint32_t val; |
644 |
|
645 |
val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
646 |
#ifdef TARGET_WORDS_BIGENDIAN
|
647 |
val = bswap16(val); |
648 |
#endif
|
649 |
return val;
|
650 |
} |
651 |
|
652 |
static void cmos_mm_writew (void *opaque, |
653 |
target_phys_addr_t addr, uint32_t value) |
654 |
{ |
655 |
RTCState *s = opaque; |
656 |
#ifdef TARGET_WORDS_BIGENDIAN
|
657 |
value = bswap16(value); |
658 |
#endif
|
659 |
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
660 |
} |
661 |
|
662 |
static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr) |
663 |
{ |
664 |
RTCState *s = opaque; |
665 |
uint32_t val; |
666 |
|
667 |
val = cmos_ioport_read(s, addr >> s->it_shift); |
668 |
#ifdef TARGET_WORDS_BIGENDIAN
|
669 |
val = bswap32(val); |
670 |
#endif
|
671 |
return val;
|
672 |
} |
673 |
|
674 |
static void cmos_mm_writel (void *opaque, |
675 |
target_phys_addr_t addr, uint32_t value) |
676 |
{ |
677 |
RTCState *s = opaque; |
678 |
#ifdef TARGET_WORDS_BIGENDIAN
|
679 |
value = bswap32(value); |
680 |
#endif
|
681 |
cmos_ioport_write(s, addr >> s->it_shift, value); |
682 |
} |
683 |
|
684 |
static CPUReadMemoryFunc * const rtc_mm_read[] = { |
685 |
&cmos_mm_readb, |
686 |
&cmos_mm_readw, |
687 |
&cmos_mm_readl, |
688 |
}; |
689 |
|
690 |
static CPUWriteMemoryFunc * const rtc_mm_write[] = { |
691 |
&cmos_mm_writeb, |
692 |
&cmos_mm_writew, |
693 |
&cmos_mm_writel, |
694 |
}; |
695 |
|
696 |
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
|
697 |
int base_year)
|
698 |
{ |
699 |
RTCState *s; |
700 |
int io_memory;
|
701 |
|
702 |
s = qemu_mallocz(sizeof(RTCState));
|
703 |
|
704 |
s->irq = irq; |
705 |
s->cmos_data[RTC_REG_A] = 0x26;
|
706 |
s->cmos_data[RTC_REG_B] = 0x02;
|
707 |
s->cmos_data[RTC_REG_C] = 0x00;
|
708 |
s->cmos_data[RTC_REG_D] = 0x80;
|
709 |
|
710 |
s->base_year = base_year; |
711 |
rtc_set_date_from_host(s); |
712 |
|
713 |
s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); |
714 |
s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); |
715 |
s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); |
716 |
|
717 |
s->next_second_time = |
718 |
qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; |
719 |
qemu_mod_timer(s->second_timer2, s->next_second_time); |
720 |
|
721 |
io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s); |
722 |
cpu_register_physical_memory(base, 2 << it_shift, io_memory);
|
723 |
|
724 |
vmstate_register(base, &vmstate_rtc, s); |
725 |
qemu_register_reset(rtc_reset, s); |
726 |
return s;
|
727 |
} |