Archipelago » qemu

/*

 * QEMU PCI bus manager

 *

 * Copyright (c) 2004 Fabrice Bellard

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "hw.h"

#include "pci.h"

#include "monitor.h"

#include "net.h"

#include "sysemu.h"

#include "loader.h"

#include "qemu-objects.h"

//#define DEBUG_PCI

#ifdef DEBUG_PCI

# define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)

#else

# define PCI_DPRINTF(format, ...)       do { } while (0)

#endif

struct PCIBus {

    BusState qbus;

    int devfn_min;

    pci_set_irq_fn set_irq;

    pci_map_irq_fn map_irq;

    pci_hotplug_fn hotplug;

    DeviceState *hotplug_qdev;

    void *irq_opaque;

    PCIDevice *devices[256];

    PCIDevice *parent_dev;

    target_phys_addr_t mem_base;

    QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */

    QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */

    /* The bus IRQ state is the logical OR of the connected devices.

       Keep a count of the number of devices with raised IRQs.  */

    int nirq;

    int *irq_count;

};

static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);

static char *pcibus_get_dev_path(DeviceState *dev);

static struct BusInfo pci_bus_info = {

    .name       = "PCI",

    .size       = sizeof(PCIBus),

    .print_dev  = pcibus_dev_print,

    .get_dev_path = pcibus_get_dev_path,

    .props      = (Property[]) {

        DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),

        DEFINE_PROP_STRING("romfile", PCIDevice, romfile),

        DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),

        DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,

                        QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),

        DEFINE_PROP_END_OF_LIST()

    }

};

static void pci_update_mappings(PCIDevice *d);

static void pci_set_irq(void *opaque, int irq_num, int level);

static int pci_add_option_rom(PCIDevice *pdev);

static void pci_del_option_rom(PCIDevice *pdev);

static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;

static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;

struct PCIHostBus {

    int domain;

    struct PCIBus *bus;

    QLIST_ENTRY(PCIHostBus) next;

};

static QLIST_HEAD(, PCIHostBus) host_buses;

static const VMStateDescription vmstate_pcibus = {

    .name = "PCIBUS",

    .version_id = 1,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_INT32_EQUAL(nirq, PCIBus),

        VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),

        VMSTATE_END_OF_LIST()

    }

};

static int pci_bar(PCIDevice *d, int reg)

{

    uint8_t type;

    if (reg != PCI_ROM_SLOT)

        return PCI_BASE_ADDRESS_0 + reg * 4;

    type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;

    return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;

}

static inline int pci_irq_state(PCIDevice *d, int irq_num)

{

        return (d->irq_state >> irq_num) & 0x1;

}

static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)

{

        d->irq_state &= ~(0x1 << irq_num);

        d->irq_state |= level << irq_num;

}

static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)

{

    PCIBus *bus;

    for (;;) {

        bus = pci_dev->bus;

        irq_num = bus->map_irq(pci_dev, irq_num);

        if (bus->set_irq)

            break;

        pci_dev = bus->parent_dev;

    }

    bus->irq_count[irq_num] += change;

    bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);

}

/* Update interrupt status bit in config space on interrupt

 * state change. */

static void pci_update_irq_status(PCIDevice *dev)

{

    if (dev->irq_state) {

        dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;

    } else {

        dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;

    }

}

static void pci_device_reset(PCIDevice *dev)

{

    int r;

    dev->irq_state = 0;

    pci_update_irq_status(dev);

    dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |

                                  PCI_COMMAND_MASTER);

    dev->config[PCI_CACHE_LINE_SIZE] = 0x0;

    dev->config[PCI_INTERRUPT_LINE] = 0x0;

    for (r = 0; r < PCI_NUM_REGIONS; ++r) {

        if (!dev->io_regions[r].size) {

            continue;

        }

        pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);

    }

    pci_update_mappings(dev);

}

static void pci_bus_reset(void *opaque)

{

    PCIBus *bus = opaque;

    int i;

    for (i = 0; i < bus->nirq; i++) {

        bus->irq_count[i] = 0;

    }

    for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {

        if (bus->devices[i]) {

            pci_device_reset(bus->devices[i]);

        }

    }

}

static void pci_host_bus_register(int domain, PCIBus *bus)

{

    struct PCIHostBus *host;

    host = qemu_mallocz(sizeof(*host));

    host->domain = domain;

    host->bus = bus;

    QLIST_INSERT_HEAD(&host_buses, host, next);

}

PCIBus *pci_find_root_bus(int domain)

{

    struct PCIHostBus *host;

    QLIST_FOREACH(host, &host_buses, next) {

        if (host->domain == domain) {

            return host->bus;

        }

    }

    return NULL;

}

int pci_find_domain(const PCIBus *bus)

{

    PCIDevice *d;

    struct PCIHostBus *host;

    /* obtain root bus */

    while ((d = bus->parent_dev) != NULL) {

        bus = d->bus;

    }

    QLIST_FOREACH(host, &host_buses, next) {

        if (host->bus == bus) {

            return host->domain;

        }

    }

    abort();    /* should not be reached */

    return -1;

}

void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,

                         const char *name, int devfn_min)

{

    qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);

    assert(PCI_FUNC(devfn_min) == 0);

    bus->devfn_min = devfn_min;

    /* host bridge */

    QLIST_INIT(&bus->child);

    pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */

    vmstate_register(NULL, -1, &vmstate_pcibus, bus);

    qemu_register_reset(pci_bus_reset, bus);

}

PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)

{

    PCIBus *bus;

    bus = qemu_mallocz(sizeof(*bus));

    bus->qbus.qdev_allocated = 1;

    pci_bus_new_inplace(bus, parent, name, devfn_min);

    return bus;

}

void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,

                  void *irq_opaque, int nirq)

{

    bus->set_irq = set_irq;

    bus->map_irq = map_irq;

    bus->irq_opaque = irq_opaque;

    bus->nirq = nirq;

    bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));

}

void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)

{

    bus->qbus.allow_hotplug = 1;

    bus->hotplug = hotplug;

    bus->hotplug_qdev = qdev;

}

void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)

{

    bus->mem_base = base;

}

PCIBus *pci_register_bus(DeviceState *parent, const char *name,

                         pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,

                         void *irq_opaque, int devfn_min, int nirq)

{

    PCIBus *bus;

    bus = pci_bus_new(parent, name, devfn_min);

    pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);

    return bus;

}

static void pci_register_secondary_bus(PCIBus *parent,

                                       PCIBus *bus,

                                       PCIDevice *dev,

                                       pci_map_irq_fn map_irq,

                                       const char *name)

{

    qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);

    bus->map_irq = map_irq;

    bus->parent_dev = dev;

    QLIST_INIT(&bus->child);

    QLIST_INSERT_HEAD(&parent->child, bus, sibling);

}

static void pci_unregister_secondary_bus(PCIBus *bus)

{

    assert(QLIST_EMPTY(&bus->child));

    QLIST_REMOVE(bus, sibling);

}

int pci_bus_num(PCIBus *s)

{

    if (!s->parent_dev)

        return 0;       /* pci host bridge */

    return s->parent_dev->config[PCI_SECONDARY_BUS];

}

static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)

{

    PCIDevice *s = container_of(pv, PCIDevice, config);

    uint8_t *config;

    int i;

    assert(size == pci_config_size(s));

    config = qemu_malloc(size);

    qemu_get_buffer(f, config, size);

    for (i = 0; i < size; ++i) {

        if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {

            qemu_free(config);

            return -EINVAL;

        }

    }

    memcpy(s->config, config, size);

    pci_update_mappings(s);

    qemu_free(config);

    return 0;

}

/* just put buffer */

static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)

{

    const uint8_t **v = pv;

    assert(size == pci_config_size(container_of(pv, PCIDevice, config)));

    qemu_put_buffer(f, *v, size);

}

static VMStateInfo vmstate_info_pci_config = {

    .name = "pci config",

    .get  = get_pci_config_device,

    .put  = put_pci_config_device,

};

static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)

{

    PCIDevice *s = container_of(pv, PCIDevice, irq_state);

    uint32_t irq_state[PCI_NUM_PINS];

    int i;

    for (i = 0; i < PCI_NUM_PINS; ++i) {

        irq_state[i] = qemu_get_be32(f);

        if (irq_state[i] != 0x1 && irq_state[i] != 0) {

            fprintf(stderr, "irq state %d: must be 0 or 1.\n",

                    irq_state[i]);

            return -EINVAL;

        }

    }

    for (i = 0; i < PCI_NUM_PINS; ++i) {

        pci_set_irq_state(s, i, irq_state[i]);

    }

    return 0;

}

static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)

{

    int i;

    PCIDevice *s = container_of(pv, PCIDevice, irq_state);

    for (i = 0; i < PCI_NUM_PINS; ++i) {

        qemu_put_be32(f, pci_irq_state(s, i));

    }

}

static VMStateInfo vmstate_info_pci_irq_state = {

    .name = "pci irq state",

    .get  = get_pci_irq_state,

    .put  = put_pci_irq_state,

};

const VMStateDescription vmstate_pci_device = {

    .name = "PCIDevice",

    .version_id = 2,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_INT32_LE(version_id, PCIDevice),

        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,

                                   vmstate_info_pci_config,

                                   PCI_CONFIG_SPACE_SIZE),

        VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,

                                   vmstate_info_pci_irq_state,

                                   PCI_NUM_PINS * sizeof(int32_t)),

        VMSTATE_END_OF_LIST()

    }

};

const VMStateDescription vmstate_pcie_device = {

    .name = "PCIDevice",

    .version_id = 2,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_INT32_LE(version_id, PCIDevice),

        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,

                                   vmstate_info_pci_config,

                                   PCIE_CONFIG_SPACE_SIZE),

        VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,

                                   vmstate_info_pci_irq_state,

                                   PCI_NUM_PINS * sizeof(int32_t)),

        VMSTATE_END_OF_LIST()

    }

};

static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)

{

    return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;

}

void pci_device_save(PCIDevice *s, QEMUFile *f)

{

    /* Clear interrupt status bit: it is implicit

     * in irq_state which we are saving.

     * This makes us compatible with old devices

     * which never set or clear this bit. */

    s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;

    vmstate_save_state(f, pci_get_vmstate(s), s);

    /* Restore the interrupt status bit. */

    pci_update_irq_status(s);

}

int pci_device_load(PCIDevice *s, QEMUFile *f)

{

    int ret;

    ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);

    /* Restore the interrupt status bit. */

    pci_update_irq_status(s);

    return ret;

}

static void pci_set_default_subsystem_id(PCIDevice *pci_dev)

{

    pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,

                 pci_default_sub_vendor_id);

    pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,

                 pci_default_sub_device_id);

}

/*

 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error

 */

static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)

{

    const char *p;

    char *e;

    unsigned long val;

    unsigned long dom = 0, bus = 0;

    unsigned slot = 0;

    p = addr;

    val = strtoul(p, &e, 16);

    if (e == p)

        return -1;

    if (*e == ':') {

        bus = val;

        p = e + 1;

        val = strtoul(p, &e, 16);

        if (e == p)

            return -1;

        if (*e == ':') {

            dom = bus;

            bus = val;

            p = e + 1;

            val = strtoul(p, &e, 16);

            if (e == p)

                return -1;

        }

    }

    if (dom > 0xffff || bus > 0xff || val > 0x1f)

        return -1;

    slot = val;

    if (*e)

        return -1;

    /* Note: QEMU doesn't implement domains other than 0 */

    if (!pci_find_bus(pci_find_root_bus(dom), bus))

        return -1;

    *domp = dom;

    *busp = bus;

    *slotp = slot;

    return 0;

}

int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,

                     unsigned *slotp)

{

    /* strip legacy tag */

    if (!strncmp(addr, "pci_addr=", 9)) {

        addr += 9;

    }

    if (pci_parse_devaddr(addr, domp, busp, slotp)) {

        monitor_printf(mon, "Invalid pci address\n");

        return -1;

    }

    return 0;

}

PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)

{

    int dom, bus;

    unsigned slot;

    if (!devaddr) {

        *devfnp = -1;

        return pci_find_bus(pci_find_root_bus(0), 0);

    }

    if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {

        return NULL;

    }

    *devfnp = slot << 3;

    return pci_find_bus(pci_find_root_bus(dom), bus);

}

static void pci_init_cmask(PCIDevice *dev)

{

    pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);

    pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);

    dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;

    dev->cmask[PCI_REVISION_ID] = 0xff;

    dev->cmask[PCI_CLASS_PROG] = 0xff;

    pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);

    dev->cmask[PCI_HEADER_TYPE] = 0xff;

    dev->cmask[PCI_CAPABILITY_LIST] = 0xff;

}

static void pci_init_wmask(PCIDevice *dev)

{

    int config_size = pci_config_size(dev);

    dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;

    dev->wmask[PCI_INTERRUPT_LINE] = 0xff;

    pci_set_word(dev->wmask + PCI_COMMAND,

                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |

                 PCI_COMMAND_INTX_DISABLE);

    memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,

           config_size - PCI_CONFIG_HEADER_SIZE);

}

static void pci_init_wmask_bridge(PCIDevice *d)

{

    /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and

       PCI_SEC_LETENCY_TIMER */

    memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);

    /* base and limit */

    d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;

    d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;

    pci_set_word(d->wmask + PCI_MEMORY_BASE,

                 PCI_MEMORY_RANGE_MASK & 0xffff);

    pci_set_word(d->wmask + PCI_MEMORY_LIMIT,

                 PCI_MEMORY_RANGE_MASK & 0xffff);

    pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,

                 PCI_PREF_RANGE_MASK & 0xffff);

    pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,

                 PCI_PREF_RANGE_MASK & 0xffff);

    /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */

    memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);

    pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);

}

static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)

{

    uint8_t slot = PCI_SLOT(dev->devfn);

    uint8_t func;

    if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {

        dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;

    }

    /*

     * multifuction bit is interpreted in two ways as follows.

     *   - all functions must set the bit to 1.

     *     Example: Intel X53

     *   - function 0 must set the bit, but the rest function (> 0)

     *     is allowed to leave the bit to 0.

     *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,

     *

     * So OS (at least Linux) checks the bit of only function 0,

     * and doesn't see the bit of function > 0.

     *

     * The below check allows both interpretation.

     */

    if (PCI_FUNC(dev->devfn)) {

        PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];

        if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {

            /* function 0 should set multifunction bit */

            error_report("PCI: single function device can't be populated "

                         "in function %x.%x", slot, PCI_FUNC(dev->devfn));

            return -1;

        }

        return 0;

    }

    if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {

        return 0;

    }

    /* function 0 indicates single function, so function > 0 must be NULL */

    for (func = 1; func < PCI_FUNC_MAX; ++func) {

        if (bus->devices[PCI_DEVFN(slot, func)]) {

            error_report("PCI: %x.0 indicates single function, "

                         "but %x.%x is already populated.",

                         slot, slot, func);

            return -1;

        }

    }

    return 0;

}

static void pci_config_alloc(PCIDevice *pci_dev)

{

    int config_size = pci_config_size(pci_dev);

    pci_dev->config = qemu_mallocz(config_size);

    pci_dev->cmask = qemu_mallocz(config_size);

    pci_dev->wmask = qemu_mallocz(config_size);

    pci_dev->used = qemu_mallocz(config_size);

}

static void pci_config_free(PCIDevice *pci_dev)

{

    qemu_free(pci_dev->config);

    qemu_free(pci_dev->cmask);

    qemu_free(pci_dev->wmask);

    qemu_free(pci_dev->used);

}

/* -1 for devfn means auto assign */

static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,

                                         const char *name, int devfn,

                                         PCIConfigReadFunc *config_read,

                                         PCIConfigWriteFunc *config_write,

                                         bool is_bridge)

{

    if (devfn < 0) {

        for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);

            devfn += PCI_FUNC_MAX) {

            if (!bus->devices[devfn])

                goto found;

        }

        error_report("PCI: no slot/function available for %s, all in use", name);

        return NULL;

    found: ;

    } else if (bus->devices[devfn]) {

        error_report("PCI: slot %d function %d not available for %s, in use by %s",

                     PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);

        return NULL;

    }

    pci_dev->bus = bus;

    pci_dev->devfn = devfn;

    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);

    pci_dev->irq_state = 0;

    pci_config_alloc(pci_dev);

    if (!is_bridge) {

        pci_set_default_subsystem_id(pci_dev);

    }

    pci_init_cmask(pci_dev);

    pci_init_wmask(pci_dev);

    if (is_bridge) {

        pci_init_wmask_bridge(pci_dev);

    }

    if (pci_init_multifunction(bus, pci_dev)) {

        pci_config_free(pci_dev);

        return NULL;

    }

    if (!config_read)

        config_read = pci_default_read_config;

    if (!config_write)

        config_write = pci_default_write_config;

    pci_dev->config_read = config_read;

    pci_dev->config_write = config_write;

    bus->devices[devfn] = pci_dev;

    pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);

    pci_dev->version_id = 2; /* Current pci device vmstate version */

    return pci_dev;

}

static void do_pci_unregister_device(PCIDevice *pci_dev)

{

    qemu_free_irqs(pci_dev->irq);

    pci_dev->bus->devices[pci_dev->devfn] = NULL;

    pci_config_free(pci_dev);

}

PCIDevice *pci_register_device(PCIBus *bus, const char *name,

                               int instance_size, int devfn,

                               PCIConfigReadFunc *config_read,

                               PCIConfigWriteFunc *config_write)

{

    PCIDevice *pci_dev;

    pci_dev = qemu_mallocz(instance_size);

    pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,

                                     config_read, config_write,

                                     PCI_HEADER_TYPE_NORMAL);

    if (pci_dev == NULL) {

        hw_error("PCI: can't register device\n");

    }

    return pci_dev;

}

static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,

                                          target_phys_addr_t addr)

{

    return addr + bus->mem_base;

}

static void pci_unregister_io_regions(PCIDevice *pci_dev)

{

    PCIIORegion *r;

    int i;

    for(i = 0; i < PCI_NUM_REGIONS; i++) {

        r = &pci_dev->io_regions[i];

        if (!r->size || r->addr == PCI_BAR_UNMAPPED)

            continue;

        if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {

            isa_unassign_ioport(r->addr, r->filtered_size);

        } else {

            cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,

                                                         r->addr),

                                         r->filtered_size,

                                         IO_MEM_UNASSIGNED);

        }

    }

}

static int pci_unregister_device(DeviceState *dev)

{

    PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);

    PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);

    int ret = 0;

    if (info->exit)

        ret = info->exit(pci_dev);

    if (ret)

        return ret;

    pci_unregister_io_regions(pci_dev);

    pci_del_option_rom(pci_dev);

    do_pci_unregister_device(pci_dev);

    return 0;

}

void pci_register_bar(PCIDevice *pci_dev, int region_num,

                            pcibus_t size, int type,

                            PCIMapIORegionFunc *map_func)

{

    PCIIORegion *r;

    uint32_t addr;

    pcibus_t wmask;

    if ((unsigned int)region_num >= PCI_NUM_REGIONS)

        return;

    if (size & (size-1)) {

        fprintf(stderr, "ERROR: PCI region size must be pow2 "

                    "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);

        exit(1);

    }

    r = &pci_dev->io_regions[region_num];

    r->addr = PCI_BAR_UNMAPPED;

    r->size = size;

    r->filtered_size = size;

    r->type = type;

    r->map_func = map_func;

    wmask = ~(size - 1);

    addr = pci_bar(pci_dev, region_num);

    if (region_num == PCI_ROM_SLOT) {

        /* ROM enable bit is writeable */

        wmask |= PCI_ROM_ADDRESS_ENABLE;

    }

    pci_set_long(pci_dev->config + addr, type);

    if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&

        r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {

        pci_set_quad(pci_dev->wmask + addr, wmask);

        pci_set_quad(pci_dev->cmask + addr, ~0ULL);

    } else {

        pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);

        pci_set_long(pci_dev->cmask + addr, 0xffffffff);

    }

}

static uint32_t pci_config_get_io_base(PCIDevice *d,

                                       uint32_t base, uint32_t base_upper16)

{

    uint32_t val;

    val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;

    if (d->config[base] & PCI_IO_RANGE_TYPE_32) {

        val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;

    }

    return val;

}

static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)

{

    return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)

        << 16;

}

static pcibus_t pci_config_get_pref_base(PCIDevice *d,

                                         uint32_t base, uint32_t upper)

{

    pcibus_t tmp;

    pcibus_t val;

    tmp = (pcibus_t)pci_get_word(d->config + base);

    val = (tmp & PCI_PREF_RANGE_MASK) << 16;

    if (tmp & PCI_PREF_RANGE_TYPE_64) {

        val |= (pcibus_t)pci_get_long(d->config + upper) << 32;

    }

    return val;

}

static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)

{

    pcibus_t base;

    if (type & PCI_BASE_ADDRESS_SPACE_IO) {

        base = pci_config_get_io_base(bridge,

                                      PCI_IO_BASE, PCI_IO_BASE_UPPER16);

    } else {

        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {

            base = pci_config_get_pref_base(

                bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);

        } else {

            base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);

        }

    }

    return base;

}

static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)

{

    pcibus_t limit;

    if (type & PCI_BASE_ADDRESS_SPACE_IO) {

        limit = pci_config_get_io_base(bridge,

                                      PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);

        limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */

    } else {

        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {

            limit = pci_config_get_pref_base(

                bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);

        } else {

            limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);

        }

        limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */

    }

    return limit;

}

static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,

                              uint8_t type)

{

    pcibus_t base = *addr;

    pcibus_t limit = *addr + *size - 1;

    PCIDevice *br;

    for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {

        uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);

        if (type & PCI_BASE_ADDRESS_SPACE_IO) {

            if (!(cmd & PCI_COMMAND_IO)) {

                goto no_map;

            }

        } else {

            if (!(cmd & PCI_COMMAND_MEMORY)) {

                goto no_map;

            }

        }

        base = MAX(base, pci_bridge_get_base(br, type));

        limit = MIN(limit, pci_bridge_get_limit(br, type));

    }

    if (base > limit) {

        goto no_map;

    }

    *addr = base;

    *size = limit - base + 1;