root / target-ppc / kvm.c @ e1a068b2
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1 | d76d1650 | aurel32 | /*
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2 | d76d1650 | aurel32 | * PowerPC implementation of KVM hooks
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3 | d76d1650 | aurel32 | *
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4 | d76d1650 | aurel32 | * Copyright IBM Corp. 2007
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5 | d76d1650 | aurel32 | *
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6 | d76d1650 | aurel32 | * Authors:
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7 | d76d1650 | aurel32 | * Jerone Young <jyoung5@us.ibm.com>
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8 | d76d1650 | aurel32 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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9 | d76d1650 | aurel32 | * Hollis Blanchard <hollisb@us.ibm.com>
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10 | d76d1650 | aurel32 | *
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11 | d76d1650 | aurel32 | * This work is licensed under the terms of the GNU GPL, version 2 or later.
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12 | d76d1650 | aurel32 | * See the COPYING file in the top-level directory.
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13 | d76d1650 | aurel32 | *
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14 | d76d1650 | aurel32 | */
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15 | d76d1650 | aurel32 | |
16 | d76d1650 | aurel32 | #include <sys/types.h> |
17 | d76d1650 | aurel32 | #include <sys/ioctl.h> |
18 | d76d1650 | aurel32 | #include <sys/mman.h> |
19 | d76d1650 | aurel32 | |
20 | d76d1650 | aurel32 | #include <linux/kvm.h> |
21 | d76d1650 | aurel32 | |
22 | d76d1650 | aurel32 | #include "qemu-common.h" |
23 | d76d1650 | aurel32 | #include "qemu-timer.h" |
24 | d76d1650 | aurel32 | #include "sysemu.h" |
25 | d76d1650 | aurel32 | #include "kvm.h" |
26 | d76d1650 | aurel32 | #include "kvm_ppc.h" |
27 | d76d1650 | aurel32 | #include "cpu.h" |
28 | d76d1650 | aurel32 | #include "device_tree.h" |
29 | d76d1650 | aurel32 | |
30 | d76d1650 | aurel32 | //#define DEBUG_KVM
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31 | d76d1650 | aurel32 | |
32 | d76d1650 | aurel32 | #ifdef DEBUG_KVM
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33 | d76d1650 | aurel32 | #define dprintf(fmt, ...) \
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34 | d76d1650 | aurel32 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
35 | d76d1650 | aurel32 | #else
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36 | d76d1650 | aurel32 | #define dprintf(fmt, ...) \
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37 | d76d1650 | aurel32 | do { } while (0) |
38 | d76d1650 | aurel32 | #endif
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39 | d76d1650 | aurel32 | |
40 | c821c2bd | Alexander Graf | /* XXX We have a race condition where we actually have a level triggered
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41 | c821c2bd | Alexander Graf | * interrupt, but the infrastructure can't expose that yet, so the guest
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42 | c821c2bd | Alexander Graf | * takes but ignores it, goes to sleep and never gets notified that there's
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43 | c821c2bd | Alexander Graf | * still an interrupt pending.
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44 | c6a94ba5 | Alexander Graf | *
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45 | c821c2bd | Alexander Graf | * As a quick workaround, let's just wake up again 20 ms after we injected
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46 | c821c2bd | Alexander Graf | * an interrupt. That way we can assure that we're always reinjecting
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47 | c821c2bd | Alexander Graf | * interrupts in case the guest swallowed them.
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48 | c6a94ba5 | Alexander Graf | */
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49 | c6a94ba5 | Alexander Graf | static QEMUTimer *idle_timer;
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50 | c6a94ba5 | Alexander Graf | |
51 | c821c2bd | Alexander Graf | static void kvm_kick_env(void *env) |
52 | c6a94ba5 | Alexander Graf | { |
53 | c821c2bd | Alexander Graf | qemu_cpu_kick(env); |
54 | c6a94ba5 | Alexander Graf | } |
55 | c6a94ba5 | Alexander Graf | |
56 | d76d1650 | aurel32 | int kvm_arch_init(KVMState *s, int smp_cpus) |
57 | d76d1650 | aurel32 | { |
58 | d76d1650 | aurel32 | return 0; |
59 | d76d1650 | aurel32 | } |
60 | d76d1650 | aurel32 | |
61 | d76d1650 | aurel32 | int kvm_arch_init_vcpu(CPUState *cenv)
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62 | d76d1650 | aurel32 | { |
63 | 861bbc80 | Alexander Graf | int ret = 0; |
64 | 861bbc80 | Alexander Graf | struct kvm_sregs sregs;
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65 | 861bbc80 | Alexander Graf | |
66 | 861bbc80 | Alexander Graf | sregs.pvr = cenv->spr[SPR_PVR]; |
67 | 861bbc80 | Alexander Graf | ret = kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs); |
68 | 861bbc80 | Alexander Graf | |
69 | c821c2bd | Alexander Graf | idle_timer = qemu_new_timer(vm_clock, kvm_kick_env, cenv); |
70 | c821c2bd | Alexander Graf | |
71 | 861bbc80 | Alexander Graf | return ret;
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72 | d76d1650 | aurel32 | } |
73 | d76d1650 | aurel32 | |
74 | caa5af0f | Jan Kiszka | void kvm_arch_reset_vcpu(CPUState *env)
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75 | caa5af0f | Jan Kiszka | { |
76 | caa5af0f | Jan Kiszka | } |
77 | caa5af0f | Jan Kiszka | |
78 | ea375f9a | Jan Kiszka | int kvm_arch_put_registers(CPUState *env, int level) |
79 | d76d1650 | aurel32 | { |
80 | d76d1650 | aurel32 | struct kvm_regs regs;
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81 | d76d1650 | aurel32 | int ret;
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82 | d76d1650 | aurel32 | int i;
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83 | d76d1650 | aurel32 | |
84 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
85 | d76d1650 | aurel32 | if (ret < 0) |
86 | d76d1650 | aurel32 | return ret;
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87 | d76d1650 | aurel32 | |
88 | d76d1650 | aurel32 | regs.ctr = env->ctr; |
89 | d76d1650 | aurel32 | regs.lr = env->lr; |
90 | d76d1650 | aurel32 | regs.xer = env->xer; |
91 | d76d1650 | aurel32 | regs.msr = env->msr; |
92 | d76d1650 | aurel32 | regs.pc = env->nip; |
93 | d76d1650 | aurel32 | |
94 | d76d1650 | aurel32 | regs.srr0 = env->spr[SPR_SRR0]; |
95 | d76d1650 | aurel32 | regs.srr1 = env->spr[SPR_SRR1]; |
96 | d76d1650 | aurel32 | |
97 | d76d1650 | aurel32 | regs.sprg0 = env->spr[SPR_SPRG0]; |
98 | d76d1650 | aurel32 | regs.sprg1 = env->spr[SPR_SPRG1]; |
99 | d76d1650 | aurel32 | regs.sprg2 = env->spr[SPR_SPRG2]; |
100 | d76d1650 | aurel32 | regs.sprg3 = env->spr[SPR_SPRG3]; |
101 | d76d1650 | aurel32 | regs.sprg4 = env->spr[SPR_SPRG4]; |
102 | d76d1650 | aurel32 | regs.sprg5 = env->spr[SPR_SPRG5]; |
103 | d76d1650 | aurel32 | regs.sprg6 = env->spr[SPR_SPRG6]; |
104 | d76d1650 | aurel32 | regs.sprg7 = env->spr[SPR_SPRG7]; |
105 | d76d1650 | aurel32 | |
106 | d76d1650 | aurel32 | for (i = 0;i < 32; i++) |
107 | d76d1650 | aurel32 | regs.gpr[i] = env->gpr[i]; |
108 | d76d1650 | aurel32 | |
109 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
110 | d76d1650 | aurel32 | if (ret < 0) |
111 | d76d1650 | aurel32 | return ret;
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112 | d76d1650 | aurel32 | |
113 | d76d1650 | aurel32 | return ret;
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114 | d76d1650 | aurel32 | } |
115 | d76d1650 | aurel32 | |
116 | d76d1650 | aurel32 | int kvm_arch_get_registers(CPUState *env)
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117 | d76d1650 | aurel32 | { |
118 | d76d1650 | aurel32 | struct kvm_regs regs;
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119 | ba5e5090 | Alexander Graf | struct kvm_sregs sregs;
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120 | d76d1650 | aurel32 | uint32_t i, ret; |
121 | d76d1650 | aurel32 | |
122 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
123 | d76d1650 | aurel32 | if (ret < 0) |
124 | d76d1650 | aurel32 | return ret;
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125 | d76d1650 | aurel32 | |
126 | ba5e5090 | Alexander Graf | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
127 | ba5e5090 | Alexander Graf | if (ret < 0) |
128 | ba5e5090 | Alexander Graf | return ret;
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129 | ba5e5090 | Alexander Graf | |
130 | d76d1650 | aurel32 | env->ctr = regs.ctr; |
131 | d76d1650 | aurel32 | env->lr = regs.lr; |
132 | d76d1650 | aurel32 | env->xer = regs.xer; |
133 | d76d1650 | aurel32 | env->msr = regs.msr; |
134 | d76d1650 | aurel32 | env->nip = regs.pc; |
135 | d76d1650 | aurel32 | |
136 | d76d1650 | aurel32 | env->spr[SPR_SRR0] = regs.srr0; |
137 | d76d1650 | aurel32 | env->spr[SPR_SRR1] = regs.srr1; |
138 | d76d1650 | aurel32 | |
139 | d76d1650 | aurel32 | env->spr[SPR_SPRG0] = regs.sprg0; |
140 | d76d1650 | aurel32 | env->spr[SPR_SPRG1] = regs.sprg1; |
141 | d76d1650 | aurel32 | env->spr[SPR_SPRG2] = regs.sprg2; |
142 | d76d1650 | aurel32 | env->spr[SPR_SPRG3] = regs.sprg3; |
143 | d76d1650 | aurel32 | env->spr[SPR_SPRG4] = regs.sprg4; |
144 | d76d1650 | aurel32 | env->spr[SPR_SPRG5] = regs.sprg5; |
145 | d76d1650 | aurel32 | env->spr[SPR_SPRG6] = regs.sprg6; |
146 | d76d1650 | aurel32 | env->spr[SPR_SPRG7] = regs.sprg7; |
147 | d76d1650 | aurel32 | |
148 | d76d1650 | aurel32 | for (i = 0;i < 32; i++) |
149 | d76d1650 | aurel32 | env->gpr[i] = regs.gpr[i]; |
150 | d76d1650 | aurel32 | |
151 | ba5e5090 | Alexander Graf | #ifdef KVM_CAP_PPC_SEGSTATE
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152 | ba5e5090 | Alexander Graf | if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_SEGSTATE)) {
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153 | ba5e5090 | Alexander Graf | env->sdr1 = sregs.u.s.sdr1; |
154 | ba5e5090 | Alexander Graf | |
155 | ba5e5090 | Alexander Graf | /* Sync SLB */
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156 | 82c09f2f | Alexander Graf | #ifdef TARGET_PPC64
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157 | ba5e5090 | Alexander Graf | for (i = 0; i < 64; i++) { |
158 | ba5e5090 | Alexander Graf | ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe, |
159 | ba5e5090 | Alexander Graf | sregs.u.s.ppc64.slb[i].slbv); |
160 | ba5e5090 | Alexander Graf | } |
161 | 82c09f2f | Alexander Graf | #endif
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162 | ba5e5090 | Alexander Graf | |
163 | ba5e5090 | Alexander Graf | /* Sync SRs */
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164 | ba5e5090 | Alexander Graf | for (i = 0; i < 16; i++) { |
165 | ba5e5090 | Alexander Graf | env->sr[i] = sregs.u.s.ppc32.sr[i]; |
166 | ba5e5090 | Alexander Graf | } |
167 | ba5e5090 | Alexander Graf | |
168 | ba5e5090 | Alexander Graf | /* Sync BATs */
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169 | ba5e5090 | Alexander Graf | for (i = 0; i < 8; i++) { |
170 | ba5e5090 | Alexander Graf | env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; |
171 | ba5e5090 | Alexander Graf | env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; |
172 | ba5e5090 | Alexander Graf | env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; |
173 | ba5e5090 | Alexander Graf | env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; |
174 | ba5e5090 | Alexander Graf | } |
175 | ba5e5090 | Alexander Graf | } |
176 | ba5e5090 | Alexander Graf | #endif
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177 | ba5e5090 | Alexander Graf | |
178 | d76d1650 | aurel32 | return 0; |
179 | d76d1650 | aurel32 | } |
180 | d76d1650 | aurel32 | |
181 | 16415335 | Alexander Graf | #if defined(TARGET_PPCEMB)
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182 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC40x_INPUT_INT
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183 | 16415335 | Alexander Graf | #elif defined(TARGET_PPC64)
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184 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC970_INPUT_INT
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185 | 16415335 | Alexander Graf | #else
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186 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC6xx_INPUT_INT
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187 | 16415335 | Alexander Graf | #endif
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188 | 16415335 | Alexander Graf | |
189 | d76d1650 | aurel32 | int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
190 | d76d1650 | aurel32 | { |
191 | d76d1650 | aurel32 | int r;
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192 | d76d1650 | aurel32 | unsigned irq;
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193 | d76d1650 | aurel32 | |
194 | d76d1650 | aurel32 | /* PowerPC Qemu tracks the various core input pins (interrupt, critical
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195 | d76d1650 | aurel32 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
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196 | d76d1650 | aurel32 | if (run->ready_for_interrupt_injection &&
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197 | d76d1650 | aurel32 | (env->interrupt_request & CPU_INTERRUPT_HARD) && |
198 | 16415335 | Alexander Graf | (env->irq_input_state & (1<<PPC_INPUT_INT)))
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199 | d76d1650 | aurel32 | { |
200 | d76d1650 | aurel32 | /* For now KVM disregards the 'irq' argument. However, in the
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201 | d76d1650 | aurel32 | * future KVM could cache it in-kernel to avoid a heavyweight exit
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202 | d76d1650 | aurel32 | * when reading the UIC.
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203 | d76d1650 | aurel32 | */
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204 | d76d1650 | aurel32 | irq = -1U;
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205 | d76d1650 | aurel32 | |
206 | d76d1650 | aurel32 | dprintf("injected interrupt %d\n", irq);
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207 | d76d1650 | aurel32 | r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq); |
208 | d76d1650 | aurel32 | if (r < 0) |
209 | d76d1650 | aurel32 | printf("cpu %d fail inject %x\n", env->cpu_index, irq);
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210 | c821c2bd | Alexander Graf | |
211 | c821c2bd | Alexander Graf | /* Always wake up soon in case the interrupt was level based */
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212 | c821c2bd | Alexander Graf | qemu_mod_timer(idle_timer, qemu_get_clock(vm_clock) + |
213 | c821c2bd | Alexander Graf | (get_ticks_per_sec() / 50));
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214 | d76d1650 | aurel32 | } |
215 | d76d1650 | aurel32 | |
216 | d76d1650 | aurel32 | /* We don't know if there are more interrupts pending after this. However,
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217 | d76d1650 | aurel32 | * the guest will return to userspace in the course of handling this one
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218 | d76d1650 | aurel32 | * anyways, so we will get a chance to deliver the rest. */
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219 | d76d1650 | aurel32 | return 0; |
220 | d76d1650 | aurel32 | } |
221 | d76d1650 | aurel32 | |
222 | d76d1650 | aurel32 | int kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
223 | d76d1650 | aurel32 | { |
224 | d76d1650 | aurel32 | return 0; |
225 | d76d1650 | aurel32 | } |
226 | d76d1650 | aurel32 | |
227 | 0af691d7 | Marcelo Tosatti | int kvm_arch_process_irqchip_events(CPUState *env)
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228 | 0af691d7 | Marcelo Tosatti | { |
229 | 0af691d7 | Marcelo Tosatti | return 0; |
230 | 0af691d7 | Marcelo Tosatti | } |
231 | 0af691d7 | Marcelo Tosatti | |
232 | d76d1650 | aurel32 | static int kvmppc_handle_halt(CPUState *env) |
233 | d76d1650 | aurel32 | { |
234 | d76d1650 | aurel32 | if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
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235 | d76d1650 | aurel32 | env->halted = 1;
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236 | d76d1650 | aurel32 | env->exception_index = EXCP_HLT; |
237 | d76d1650 | aurel32 | } |
238 | d76d1650 | aurel32 | |
239 | d76d1650 | aurel32 | return 1; |
240 | d76d1650 | aurel32 | } |
241 | d76d1650 | aurel32 | |
242 | d76d1650 | aurel32 | /* map dcr access to existing qemu dcr emulation */
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243 | d76d1650 | aurel32 | static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data) |
244 | d76d1650 | aurel32 | { |
245 | d76d1650 | aurel32 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) |
246 | d76d1650 | aurel32 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
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247 | d76d1650 | aurel32 | |
248 | d76d1650 | aurel32 | return 1; |
249 | d76d1650 | aurel32 | } |
250 | d76d1650 | aurel32 | |
251 | d76d1650 | aurel32 | static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data) |
252 | d76d1650 | aurel32 | { |
253 | d76d1650 | aurel32 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) |
254 | d76d1650 | aurel32 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
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255 | d76d1650 | aurel32 | |
256 | d76d1650 | aurel32 | return 1; |
257 | d76d1650 | aurel32 | } |
258 | d76d1650 | aurel32 | |
259 | d76d1650 | aurel32 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
260 | d76d1650 | aurel32 | { |
261 | d76d1650 | aurel32 | int ret = 0; |
262 | d76d1650 | aurel32 | |
263 | d76d1650 | aurel32 | switch (run->exit_reason) {
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264 | d76d1650 | aurel32 | case KVM_EXIT_DCR:
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265 | d76d1650 | aurel32 | if (run->dcr.is_write) {
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266 | d76d1650 | aurel32 | dprintf("handle dcr write\n");
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267 | d76d1650 | aurel32 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); |
268 | d76d1650 | aurel32 | } else {
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269 | d76d1650 | aurel32 | dprintf("handle dcr read\n");
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270 | d76d1650 | aurel32 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); |
271 | d76d1650 | aurel32 | } |
272 | d76d1650 | aurel32 | break;
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273 | d76d1650 | aurel32 | case KVM_EXIT_HLT:
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274 | d76d1650 | aurel32 | dprintf("handle halt\n");
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275 | d76d1650 | aurel32 | ret = kvmppc_handle_halt(env); |
276 | d76d1650 | aurel32 | break;
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277 | d76d1650 | aurel32 | } |
278 | d76d1650 | aurel32 | |
279 | d76d1650 | aurel32 | return ret;
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280 | d76d1650 | aurel32 | } |
281 | d76d1650 | aurel32 | |
282 | dc333cd6 | Alexander Graf | static int read_cpuinfo(const char *field, char *value, int len) |
283 | dc333cd6 | Alexander Graf | { |
284 | dc333cd6 | Alexander Graf | FILE *f; |
285 | dc333cd6 | Alexander Graf | int ret = -1; |
286 | dc333cd6 | Alexander Graf | int field_len = strlen(field);
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287 | dc333cd6 | Alexander Graf | char line[512]; |
288 | dc333cd6 | Alexander Graf | |
289 | dc333cd6 | Alexander Graf | f = fopen("/proc/cpuinfo", "r"); |
290 | dc333cd6 | Alexander Graf | if (!f) {
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291 | dc333cd6 | Alexander Graf | return -1; |
292 | dc333cd6 | Alexander Graf | } |
293 | dc333cd6 | Alexander Graf | |
294 | dc333cd6 | Alexander Graf | do {
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295 | dc333cd6 | Alexander Graf | if(!fgets(line, sizeof(line), f)) { |
296 | dc333cd6 | Alexander Graf | break;
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297 | dc333cd6 | Alexander Graf | } |
298 | dc333cd6 | Alexander Graf | if (!strncmp(line, field, field_len)) {
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299 | dc333cd6 | Alexander Graf | strncpy(value, line, len); |
300 | dc333cd6 | Alexander Graf | ret = 0;
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301 | dc333cd6 | Alexander Graf | break;
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302 | dc333cd6 | Alexander Graf | } |
303 | dc333cd6 | Alexander Graf | } while(*line);
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304 | dc333cd6 | Alexander Graf | |
305 | dc333cd6 | Alexander Graf | fclose(f); |
306 | dc333cd6 | Alexander Graf | |
307 | dc333cd6 | Alexander Graf | return ret;
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308 | dc333cd6 | Alexander Graf | } |
309 | dc333cd6 | Alexander Graf | |
310 | dc333cd6 | Alexander Graf | uint32_t kvmppc_get_tbfreq(void)
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311 | dc333cd6 | Alexander Graf | { |
312 | dc333cd6 | Alexander Graf | char line[512]; |
313 | dc333cd6 | Alexander Graf | char *ns;
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314 | dc333cd6 | Alexander Graf | uint32_t retval = get_ticks_per_sec(); |
315 | dc333cd6 | Alexander Graf | |
316 | dc333cd6 | Alexander Graf | if (read_cpuinfo("timebase", line, sizeof(line))) { |
317 | dc333cd6 | Alexander Graf | return retval;
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318 | dc333cd6 | Alexander Graf | } |
319 | dc333cd6 | Alexander Graf | |
320 | dc333cd6 | Alexander Graf | if (!(ns = strchr(line, ':'))) { |
321 | dc333cd6 | Alexander Graf | return retval;
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322 | dc333cd6 | Alexander Graf | } |
323 | dc333cd6 | Alexander Graf | |
324 | dc333cd6 | Alexander Graf | ns++; |
325 | dc333cd6 | Alexander Graf | |
326 | dc333cd6 | Alexander Graf | retval = atoi(ns); |
327 | dc333cd6 | Alexander Graf | return retval;
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328 | dc333cd6 | Alexander Graf | } |
329 | 4513d923 | Gleb Natapov | |
330 | 4513d923 | Gleb Natapov | bool kvm_arch_stop_on_emulation_error(CPUState *env)
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331 | 4513d923 | Gleb Natapov | { |
332 | 4513d923 | Gleb Natapov | return true; |
333 | 4513d923 | Gleb Natapov | } |