root / hw / arm_sysctl.c @ e1cb9502
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1 | 5fafdf24 | ths | /*
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2 | e69954b9 | pbrook | * Status and system control registers for ARM RealView/Versatile boards.
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3 | e69954b9 | pbrook | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | e69954b9 | pbrook | * Written by Paul Brook
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6 | e69954b9 | pbrook | *
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7 | e69954b9 | pbrook | * This code is licenced under the GPL.
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8 | e69954b9 | pbrook | */
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9 | e69954b9 | pbrook | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 9596ebb7 | pbrook | #include "primecell.h" |
12 | 87ecb68b | pbrook | #include "sysemu.h" |
13 | e69954b9 | pbrook | |
14 | e69954b9 | pbrook | #define LOCK_VALUE 0xa05f |
15 | e69954b9 | pbrook | |
16 | e69954b9 | pbrook | typedef struct { |
17 | e69954b9 | pbrook | uint32_t base; |
18 | e69954b9 | pbrook | uint32_t sys_id; |
19 | e69954b9 | pbrook | uint32_t leds; |
20 | e69954b9 | pbrook | uint16_t lockval; |
21 | e69954b9 | pbrook | uint32_t cfgdata1; |
22 | e69954b9 | pbrook | uint32_t cfgdata2; |
23 | e69954b9 | pbrook | uint32_t flags; |
24 | e69954b9 | pbrook | uint32_t nvflags; |
25 | e69954b9 | pbrook | uint32_t resetlevel; |
26 | e69954b9 | pbrook | } arm_sysctl_state; |
27 | e69954b9 | pbrook | |
28 | e69954b9 | pbrook | static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) |
29 | e69954b9 | pbrook | { |
30 | e69954b9 | pbrook | arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
31 | e69954b9 | pbrook | |
32 | e69954b9 | pbrook | offset -= s->base; |
33 | e69954b9 | pbrook | switch (offset) {
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34 | e69954b9 | pbrook | case 0x00: /* ID */ |
35 | e69954b9 | pbrook | return s->sys_id;
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36 | e69954b9 | pbrook | case 0x04: /* SW */ |
37 | e69954b9 | pbrook | /* General purpose hardware switches.
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38 | e69954b9 | pbrook | We don't have a useful way of exposing these to the user. */
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39 | e69954b9 | pbrook | return 0; |
40 | e69954b9 | pbrook | case 0x08: /* LED */ |
41 | e69954b9 | pbrook | return s->leds;
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42 | e69954b9 | pbrook | case 0x20: /* LOCK */ |
43 | e69954b9 | pbrook | return s->lockval;
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44 | e69954b9 | pbrook | case 0x0c: /* OSC0 */ |
45 | e69954b9 | pbrook | case 0x10: /* OSC1 */ |
46 | e69954b9 | pbrook | case 0x14: /* OSC2 */ |
47 | e69954b9 | pbrook | case 0x18: /* OSC3 */ |
48 | e69954b9 | pbrook | case 0x1c: /* OSC4 */ |
49 | e69954b9 | pbrook | case 0x24: /* 100HZ */ |
50 | e69954b9 | pbrook | /* ??? Implement these. */
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51 | e69954b9 | pbrook | return 0; |
52 | e69954b9 | pbrook | case 0x28: /* CFGDATA1 */ |
53 | e69954b9 | pbrook | return s->cfgdata1;
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54 | e69954b9 | pbrook | case 0x2c: /* CFGDATA2 */ |
55 | e69954b9 | pbrook | return s->cfgdata2;
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56 | e69954b9 | pbrook | case 0x30: /* FLAGS */ |
57 | e69954b9 | pbrook | return s->flags;
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58 | e69954b9 | pbrook | case 0x38: /* NVFLAGS */ |
59 | e69954b9 | pbrook | return s->nvflags;
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60 | e69954b9 | pbrook | case 0x40: /* RESETCTL */ |
61 | e69954b9 | pbrook | return s->resetlevel;
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62 | e69954b9 | pbrook | case 0x44: /* PCICTL */ |
63 | e69954b9 | pbrook | return 1; |
64 | e69954b9 | pbrook | case 0x48: /* MCI */ |
65 | e69954b9 | pbrook | return 0; |
66 | e69954b9 | pbrook | case 0x4c: /* FLASH */ |
67 | e69954b9 | pbrook | return 0; |
68 | e69954b9 | pbrook | case 0x50: /* CLCD */ |
69 | e69954b9 | pbrook | return 0x1000; |
70 | e69954b9 | pbrook | case 0x54: /* CLCDSER */ |
71 | e69954b9 | pbrook | return 0; |
72 | e69954b9 | pbrook | case 0x58: /* BOOTCS */ |
73 | e69954b9 | pbrook | return 0; |
74 | e69954b9 | pbrook | case 0x5c: /* 24MHz */ |
75 | e69954b9 | pbrook | /* ??? not implemented. */
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76 | e69954b9 | pbrook | return 0; |
77 | e69954b9 | pbrook | case 0x60: /* MISC */ |
78 | e69954b9 | pbrook | return 0; |
79 | e69954b9 | pbrook | case 0x84: /* PROCID0 */ |
80 | e69954b9 | pbrook | /* ??? Don't know what the proper value for the core tile ID is. */
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81 | e69954b9 | pbrook | return 0x02000000; |
82 | e69954b9 | pbrook | case 0x88: /* PROCID1 */ |
83 | e69954b9 | pbrook | return 0xff000000; |
84 | e69954b9 | pbrook | case 0x64: /* DMAPSR0 */ |
85 | e69954b9 | pbrook | case 0x68: /* DMAPSR1 */ |
86 | e69954b9 | pbrook | case 0x6c: /* DMAPSR2 */ |
87 | e69954b9 | pbrook | case 0x70: /* IOSEL */ |
88 | e69954b9 | pbrook | case 0x74: /* PLDCTL */ |
89 | e69954b9 | pbrook | case 0x80: /* BUSID */ |
90 | e69954b9 | pbrook | case 0x8c: /* OSCRESET0 */ |
91 | e69954b9 | pbrook | case 0x90: /* OSCRESET1 */ |
92 | e69954b9 | pbrook | case 0x94: /* OSCRESET2 */ |
93 | e69954b9 | pbrook | case 0x98: /* OSCRESET3 */ |
94 | e69954b9 | pbrook | case 0x9c: /* OSCRESET4 */ |
95 | e69954b9 | pbrook | case 0xc0: /* SYS_TEST_OSC0 */ |
96 | e69954b9 | pbrook | case 0xc4: /* SYS_TEST_OSC1 */ |
97 | e69954b9 | pbrook | case 0xc8: /* SYS_TEST_OSC2 */ |
98 | e69954b9 | pbrook | case 0xcc: /* SYS_TEST_OSC3 */ |
99 | e69954b9 | pbrook | case 0xd0: /* SYS_TEST_OSC4 */ |
100 | e69954b9 | pbrook | return 0; |
101 | e69954b9 | pbrook | default:
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102 | e69954b9 | pbrook | printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset); |
103 | e69954b9 | pbrook | return 0; |
104 | e69954b9 | pbrook | } |
105 | e69954b9 | pbrook | } |
106 | e69954b9 | pbrook | |
107 | e69954b9 | pbrook | static void arm_sysctl_write(void *opaque, target_phys_addr_t offset, |
108 | e69954b9 | pbrook | uint32_t val) |
109 | e69954b9 | pbrook | { |
110 | e69954b9 | pbrook | arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
111 | e69954b9 | pbrook | offset -= s->base; |
112 | e69954b9 | pbrook | |
113 | e69954b9 | pbrook | switch (offset) {
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114 | e69954b9 | pbrook | case 0x08: /* LED */ |
115 | e69954b9 | pbrook | s->leds = val; |
116 | e69954b9 | pbrook | case 0x0c: /* OSC0 */ |
117 | e69954b9 | pbrook | case 0x10: /* OSC1 */ |
118 | e69954b9 | pbrook | case 0x14: /* OSC2 */ |
119 | e69954b9 | pbrook | case 0x18: /* OSC3 */ |
120 | e69954b9 | pbrook | case 0x1c: /* OSC4 */ |
121 | e69954b9 | pbrook | /* ??? */
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122 | e69954b9 | pbrook | break;
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123 | e69954b9 | pbrook | case 0x20: /* LOCK */ |
124 | e69954b9 | pbrook | if (val == LOCK_VALUE)
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125 | e69954b9 | pbrook | s->lockval = val; |
126 | e69954b9 | pbrook | else
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127 | e69954b9 | pbrook | s->lockval = val & 0x7fff;
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128 | e69954b9 | pbrook | break;
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129 | e69954b9 | pbrook | case 0x28: /* CFGDATA1 */ |
130 | e69954b9 | pbrook | /* ??? Need to implement this. */
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131 | e69954b9 | pbrook | s->cfgdata1 = val; |
132 | e69954b9 | pbrook | break;
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133 | e69954b9 | pbrook | case 0x2c: /* CFGDATA2 */ |
134 | e69954b9 | pbrook | /* ??? Need to implement this. */
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135 | e69954b9 | pbrook | s->cfgdata2 = val; |
136 | e69954b9 | pbrook | break;
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137 | e69954b9 | pbrook | case 0x30: /* FLAGSSET */ |
138 | e69954b9 | pbrook | s->flags |= val; |
139 | e69954b9 | pbrook | break;
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140 | e69954b9 | pbrook | case 0x34: /* FLAGSCLR */ |
141 | e69954b9 | pbrook | s->flags &= ~val; |
142 | e69954b9 | pbrook | break;
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143 | e69954b9 | pbrook | case 0x38: /* NVFLAGSSET */ |
144 | e69954b9 | pbrook | s->nvflags |= val; |
145 | e69954b9 | pbrook | break;
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146 | e69954b9 | pbrook | case 0x3c: /* NVFLAGSCLR */ |
147 | e69954b9 | pbrook | s->nvflags &= ~val; |
148 | e69954b9 | pbrook | break;
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149 | e69954b9 | pbrook | case 0x40: /* RESETCTL */ |
150 | e69954b9 | pbrook | if (s->lockval == LOCK_VALUE) {
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151 | e69954b9 | pbrook | s->resetlevel = val; |
152 | e69954b9 | pbrook | if (val & 0x100) |
153 | f3d6b95e | pbrook | qemu_system_reset_request (); |
154 | e69954b9 | pbrook | } |
155 | e69954b9 | pbrook | break;
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156 | e69954b9 | pbrook | case 0x44: /* PCICTL */ |
157 | e69954b9 | pbrook | /* nothing to do. */
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158 | e69954b9 | pbrook | break;
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159 | e69954b9 | pbrook | case 0x4c: /* FLASH */ |
160 | e69954b9 | pbrook | case 0x50: /* CLCD */ |
161 | e69954b9 | pbrook | case 0x54: /* CLCDSER */ |
162 | e69954b9 | pbrook | case 0x64: /* DMAPSR0 */ |
163 | e69954b9 | pbrook | case 0x68: /* DMAPSR1 */ |
164 | e69954b9 | pbrook | case 0x6c: /* DMAPSR2 */ |
165 | e69954b9 | pbrook | case 0x70: /* IOSEL */ |
166 | e69954b9 | pbrook | case 0x74: /* PLDCTL */ |
167 | e69954b9 | pbrook | case 0x80: /* BUSID */ |
168 | e69954b9 | pbrook | case 0x84: /* PROCID0 */ |
169 | e69954b9 | pbrook | case 0x88: /* PROCID1 */ |
170 | e69954b9 | pbrook | case 0x8c: /* OSCRESET0 */ |
171 | e69954b9 | pbrook | case 0x90: /* OSCRESET1 */ |
172 | e69954b9 | pbrook | case 0x94: /* OSCRESET2 */ |
173 | e69954b9 | pbrook | case 0x98: /* OSCRESET3 */ |
174 | e69954b9 | pbrook | case 0x9c: /* OSCRESET4 */ |
175 | e69954b9 | pbrook | break;
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176 | e69954b9 | pbrook | default:
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177 | e69954b9 | pbrook | printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset); |
178 | e69954b9 | pbrook | return;
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179 | e69954b9 | pbrook | } |
180 | e69954b9 | pbrook | } |
181 | e69954b9 | pbrook | |
182 | e69954b9 | pbrook | static CPUReadMemoryFunc *arm_sysctl_readfn[] = {
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183 | e69954b9 | pbrook | arm_sysctl_read, |
184 | e69954b9 | pbrook | arm_sysctl_read, |
185 | e69954b9 | pbrook | arm_sysctl_read |
186 | e69954b9 | pbrook | }; |
187 | e69954b9 | pbrook | |
188 | e69954b9 | pbrook | static CPUWriteMemoryFunc *arm_sysctl_writefn[] = {
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189 | e69954b9 | pbrook | arm_sysctl_write, |
190 | e69954b9 | pbrook | arm_sysctl_write, |
191 | e69954b9 | pbrook | arm_sysctl_write |
192 | e69954b9 | pbrook | }; |
193 | e69954b9 | pbrook | |
194 | e69954b9 | pbrook | void arm_sysctl_init(uint32_t base, uint32_t sys_id)
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195 | e69954b9 | pbrook | { |
196 | e69954b9 | pbrook | arm_sysctl_state *s; |
197 | e69954b9 | pbrook | int iomemtype;
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198 | e69954b9 | pbrook | |
199 | e69954b9 | pbrook | s = (arm_sysctl_state *)qemu_mallocz(sizeof(arm_sysctl_state));
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200 | e69954b9 | pbrook | if (!s)
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201 | e69954b9 | pbrook | return;
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202 | e69954b9 | pbrook | s->base = base; |
203 | e69954b9 | pbrook | s->sys_id = sys_id; |
204 | 9ee6e8bb | pbrook | /* The MPcore bootloader uses these flags to start secondary CPUs.
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205 | 9ee6e8bb | pbrook | We don't use a bootloader, so do this here. */
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206 | 9ee6e8bb | pbrook | s->flags = 3;
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207 | e69954b9 | pbrook | iomemtype = cpu_register_io_memory(0, arm_sysctl_readfn,
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208 | e69954b9 | pbrook | arm_sysctl_writefn, s); |
209 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
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210 | e69954b9 | pbrook | /* ??? Save/restore. */
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211 | e69954b9 | pbrook | } |