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/*
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* QEMU Sun4m & Sun4d & Sun4c System Emulator
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h" |
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#include "qemu-timer.h" |
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#include "sun4m.h" |
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#include "nvram.h" |
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#include "sparc32_dma.h" |
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#include "fdc.h" |
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#include "sysemu.h" |
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#include "net.h" |
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#include "boards.h" |
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#include "firmware_abi.h" |
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#include "scsi.h" |
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#include "pc.h" |
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#include "isa.h" |
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#include "fw_cfg.h" |
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#include "escc.h" |
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#include "qdev-addr.h" |
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#include "loader.h" |
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#include "elf.h" |
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//#define DEBUG_IRQ
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/*
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* Sun4m architecture was used in the following machines:
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*
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* SPARCserver 6xxMP/xx
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* SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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* SPARCclassic X (4/10)
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* SPARCstation LX/ZX (4/30)
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* SPARCstation Voyager
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* SPARCstation 10/xx, SPARCserver 10/xx
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* SPARCstation 5, SPARCserver 5
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* SPARCstation 20/xx, SPARCserver 20
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* SPARCstation 4
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*
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* Sun4d architecture was used in the following machines:
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*
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* SPARCcenter 2000
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* SPARCserver 1000
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*
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* Sun4c architecture was used in the following machines:
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* SPARCstation 1/1+, SPARCserver 1/1+
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* SPARCstation SLC
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* SPARCstation IPC
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* SPARCstation ELC
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* SPARCstation IPX
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*
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* See for example: http://www.sunhelp.org/faq/sunref1.html
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*/
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, ...) \
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define KERNEL_LOAD_ADDR 0x00004000 |
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#define CMDLINE_ADDR 0x007ff000 |
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#define INITRD_LOAD_ADDR 0x00800000 |
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#define PROM_SIZE_MAX (1024 * 1024) |
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#define PROM_VADDR 0xffd00000 |
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#define PROM_FILENAME "openbios-sparc32" |
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#define CFG_ADDR 0xd00000510ULL |
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#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
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#define MAX_CPUS 16 |
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#define MAX_PILS 16 |
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#define ESCC_CLOCK 4915200 |
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struct sun4m_hwdef {
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target_phys_addr_t iommu_base, slavio_base; |
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base, fd_base; |
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
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target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
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target_phys_addr_t ecc_base; |
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uint32_t ecc_version; |
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uint8_t nvram_machine_id; |
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uint16_t machine_id; |
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uint32_t iommu_version; |
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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#define MAX_IOUNITS 5 |
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struct sun4d_hwdef {
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target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
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target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base; |
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target_phys_addr_t espdma_base, esp_base; |
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target_phys_addr_t ledma_base, le_base; |
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target_phys_addr_t tcx_base; |
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target_phys_addr_t sbi_base; |
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uint8_t nvram_machine_id; |
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uint16_t machine_id; |
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uint32_t iounit_version; |
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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struct sun4c_hwdef {
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target_phys_addr_t iommu_base, slavio_base; |
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base, fd_base; |
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
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target_phys_addr_t tcx_base, aux1_base; |
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uint8_t nvram_machine_id; |
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uint16_t machine_id; |
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uint32_t iommu_version; |
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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int DMA_get_channel_mode (int nchan) |
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{ |
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return 0; |
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} |
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int DMA_read_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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int DMA_write_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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void DMA_hold_DREQ (int nchan) {} |
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void DMA_release_DREQ (int nchan) {} |
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void DMA_schedule(int nchan) {} |
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void DMA_init (int high_page_enable) {} |
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void DMA_register_channel (int nchan, |
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DMA_transfer_handler transfer_handler, |
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void *opaque)
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{ |
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} |
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static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
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{ |
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fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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return 0; |
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} |
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static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
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const char *boot_devices, ram_addr_t RAM_size, |
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uint32_t kernel_size, |
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int width, int height, int depth, |
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int nvram_machine_id, const char *arch) |
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{ |
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unsigned int i; |
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uint32_t start, end; |
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uint8_t image[0x1ff0];
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image)); |
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start = 0;
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM; |
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pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
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end = start + sizeof(struct OpenBIOS_nvpart_v1); |
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for (i = 0; i < nb_prom_envs; i++) |
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end = OpenBIOS_set_var(image, end, prom_envs[i]); |
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// End marker
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image[end++] = '\0';
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end = start + ((end - start + 15) & ~15); |
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OpenBIOS_finish_partition(part_header, end - start); |
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// free partition
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start = end; |
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE; |
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pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start); |
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
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nvram_machine_id); |
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for (i = 0; i < sizeof(image); i++) |
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m48t59_write(nvram, i, image[i]); |
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} |
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static DeviceState *slavio_intctl;
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void pic_info(Monitor *mon)
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{ |
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if (slavio_intctl)
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slavio_pic_info(mon, slavio_intctl); |
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} |
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void irq_info(Monitor *mon)
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{ |
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if (slavio_intctl)
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slavio_irq_info(mon, slavio_intctl); |
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} |
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void cpu_check_irqs(CPUState *env)
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{ |
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if (env->pil_in && (env->interrupt_index == 0 || |
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i; |
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for (i = 15; i > 0; i--) { |
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if (env->pil_in & (1 << i)) { |
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i; |
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if (old_interrupt != env->interrupt_index) {
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DPRINTF("Set CPU IRQ %d\n", i);
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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break;
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} |
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} |
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} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
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DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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static void cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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CPUState *env = opaque; |
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if (level) {
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DPRINTF("Raise CPU IRQ %d\n", irq);
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env->halted = 0;
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env->pil_in |= 1 << irq;
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cpu_check_irqs(env); |
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} else {
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DPRINTF("Lower CPU IRQ %d\n", irq);
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env->pil_in &= ~(1 << irq);
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cpu_check_irqs(env); |
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} |
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} |
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static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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} |
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static void main_cpu_reset(void *opaque) |
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{ |
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CPUState *env = opaque; |
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cpu_reset(env); |
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env->halted = 0;
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} |
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static void secondary_cpu_reset(void *opaque) |
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{ |
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CPUState *env = opaque; |
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cpu_reset(env); |
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env->halted = 1;
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} |
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static void cpu_halt_signal(void *opaque, int irq, int level) |
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{ |
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if (level && cpu_single_env)
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
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} |
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static unsigned long sun4m_load_kernel(const char *kernel_filename, |
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const char *initrd_filename, |
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ram_addr_t RAM_size) |
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{ |
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int linux_boot;
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unsigned int i; |
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long initrd_size, kernel_size;
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linux_boot = (kernel_filename != NULL);
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kernel_size = 0;
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if (linux_boot) {
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
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NULL, 1, ELF_MACHINE, 0); |
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if (kernel_size < 0) |
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kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
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RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
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TARGET_PAGE_SIZE); |
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if (kernel_size < 0) |
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kernel_size = load_image_targphys(kernel_filename, |
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KERNEL_LOAD_ADDR, |
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RAM_size - KERNEL_LOAD_ADDR); |
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if (kernel_size < 0) { |
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
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exit(1);
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} |
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/* load initrd */
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initrd_size = 0;
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if (initrd_filename) {
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initrd_size = load_image_targphys(initrd_filename, |
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INITRD_LOAD_ADDR, |
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RAM_size - INITRD_LOAD_ADDR); |
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if (initrd_size < 0) { |
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
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exit(1);
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} |
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} |
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if (initrd_size > 0) { |
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
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if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
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stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
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break;
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} |
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} |
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} |
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} |
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return kernel_size;
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} |
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static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
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{ |
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DeviceState *dev; |
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SysBusDevice *s; |
359 |
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dev = qdev_create(NULL, "iommu"); |
361 |
qdev_prop_set_uint32(dev, "version", version);
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qdev_init_nofail(dev); |
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s = sysbus_from_qdev(dev); |
364 |
sysbus_connect_irq(s, 0, irq);
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sysbus_mmio_map(s, 0, addr);
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return s;
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} |
369 |
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static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, |
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void *iommu, qemu_irq *dev_irq)
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{ |
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DeviceState *dev; |
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SysBusDevice *s; |
375 |
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dev = qdev_create(NULL, "sparc32_dma"); |
377 |
qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
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qdev_init_nofail(dev); |
379 |
s = sysbus_from_qdev(dev); |
380 |
sysbus_connect_irq(s, 0, parent_irq);
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*dev_irq = qdev_get_gpio_in(dev, 0);
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sysbus_mmio_map(s, 0, daddr);
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return s;
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} |
386 |
|
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static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, |
388 |
void *dma_opaque, qemu_irq irq)
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{ |
390 |
DeviceState *dev; |
391 |
SysBusDevice *s; |
392 |
qemu_irq reset; |
393 |
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qemu_check_nic_model(&nd_table[0], "lance"); |
395 |
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dev = qdev_create(NULL, "lance"); |
397 |
dev->nd = nd; |
398 |
qdev_prop_set_ptr(dev, "dma", dma_opaque);
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qdev_init_nofail(dev); |
400 |
s = sysbus_from_qdev(dev); |
401 |
sysbus_mmio_map(s, 0, leaddr);
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sysbus_connect_irq(s, 0, irq);
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reset = qdev_get_gpio_in(dev, 0);
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qdev_connect_gpio_out(dma_opaque, 0, reset);
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} |
406 |
|
407 |
static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
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target_phys_addr_t addrg, |
409 |
qemu_irq **parent_irq) |
410 |
{ |
411 |
DeviceState *dev; |
412 |
SysBusDevice *s; |
413 |
unsigned int i, j; |
414 |
|
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dev = qdev_create(NULL, "slavio_intctl"); |
416 |
qdev_init_nofail(dev); |
417 |
|
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s = sysbus_from_qdev(dev); |
419 |
|
420 |
for (i = 0; i < MAX_CPUS; i++) { |
421 |
for (j = 0; j < MAX_PILS; j++) { |
422 |
sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); |
423 |
} |
424 |
} |
425 |
sysbus_mmio_map(s, 0, addrg);
|
426 |
for (i = 0; i < MAX_CPUS; i++) { |
427 |
sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
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428 |
} |
429 |
|
430 |
return dev;
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431 |
} |
432 |
|
433 |
#define SYS_TIMER_OFFSET 0x10000ULL |
434 |
#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
435 |
|
436 |
static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, |
437 |
qemu_irq *cpu_irqs, unsigned int num_cpus) |
438 |
{ |
439 |
DeviceState *dev; |
440 |
SysBusDevice *s; |
441 |
unsigned int i; |
442 |
|
443 |
dev = qdev_create(NULL, "slavio_timer"); |
444 |
qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
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qdev_init_nofail(dev); |
446 |
s = sysbus_from_qdev(dev); |
447 |
sysbus_connect_irq(s, 0, master_irq);
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sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
|
449 |
|
450 |
for (i = 0; i < MAX_CPUS; i++) { |
451 |
sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
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452 |
sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
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} |
454 |
} |
455 |
|
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#define MISC_LEDS 0x01600000 |
457 |
#define MISC_CFG 0x01800000 |
458 |
#define MISC_DIAG 0x01a00000 |
459 |
#define MISC_MDM 0x01b00000 |
460 |
#define MISC_SYS 0x01f00000 |
461 |
|
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static void slavio_misc_init(target_phys_addr_t base, |
463 |
target_phys_addr_t aux1_base, |
464 |
target_phys_addr_t aux2_base, qemu_irq irq, |
465 |
qemu_irq fdc_tc) |
466 |
{ |
467 |
DeviceState *dev; |
468 |
SysBusDevice *s; |
469 |
|
470 |
dev = qdev_create(NULL, "slavio_misc"); |
471 |
qdev_init_nofail(dev); |
472 |
s = sysbus_from_qdev(dev); |
473 |
if (base) {
|
474 |
/* 8 bit registers */
|
475 |
/* Slavio control */
|
476 |
sysbus_mmio_map(s, 0, base + MISC_CFG);
|
477 |
/* Diagnostics */
|
478 |
sysbus_mmio_map(s, 1, base + MISC_DIAG);
|
479 |
/* Modem control */
|
480 |
sysbus_mmio_map(s, 2, base + MISC_MDM);
|
481 |
/* 16 bit registers */
|
482 |
/* ss600mp diag LEDs */
|
483 |
sysbus_mmio_map(s, 3, base + MISC_LEDS);
|
484 |
/* 32 bit registers */
|
485 |
/* System control */
|
486 |
sysbus_mmio_map(s, 4, base + MISC_SYS);
|
487 |
} |
488 |
if (aux1_base) {
|
489 |
/* AUX 1 (Misc System Functions) */
|
490 |
sysbus_mmio_map(s, 5, aux1_base);
|
491 |
} |
492 |
if (aux2_base) {
|
493 |
/* AUX 2 (Software Powerdown Control) */
|
494 |
sysbus_mmio_map(s, 6, aux2_base);
|
495 |
} |
496 |
sysbus_connect_irq(s, 0, irq);
|
497 |
sysbus_connect_irq(s, 1, fdc_tc);
|
498 |
qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
|
499 |
} |
500 |
|
501 |
static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
502 |
{ |
503 |
DeviceState *dev; |
504 |
SysBusDevice *s; |
505 |
|
506 |
dev = qdev_create(NULL, "eccmemctl"); |
507 |
qdev_prop_set_uint32(dev, "version", version);
|
508 |
qdev_init_nofail(dev); |
509 |
s = sysbus_from_qdev(dev); |
510 |
sysbus_connect_irq(s, 0, irq);
|
511 |
sysbus_mmio_map(s, 0, base);
|
512 |
if (version == 0) { // SS-600MP only |
513 |
sysbus_mmio_map(s, 1, base + 0x1000); |
514 |
} |
515 |
} |
516 |
|
517 |
static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) |
518 |
{ |
519 |
DeviceState *dev; |
520 |
SysBusDevice *s; |
521 |
|
522 |
dev = qdev_create(NULL, "apc"); |
523 |
qdev_init_nofail(dev); |
524 |
s = sysbus_from_qdev(dev); |
525 |
/* Power management (APC) XXX: not a Slavio device */
|
526 |
sysbus_mmio_map(s, 0, power_base);
|
527 |
sysbus_connect_irq(s, 0, cpu_halt);
|
528 |
} |
529 |
|
530 |
static void tcx_init(target_phys_addr_t addr, int vram_size, int width, |
531 |
int height, int depth) |
532 |
{ |
533 |
DeviceState *dev; |
534 |
SysBusDevice *s; |
535 |
|
536 |
dev = qdev_create(NULL, "SUNW,tcx"); |
537 |
qdev_prop_set_taddr(dev, "addr", addr);
|
538 |
qdev_prop_set_uint32(dev, "vram_size", vram_size);
|
539 |
qdev_prop_set_uint16(dev, "width", width);
|
540 |
qdev_prop_set_uint16(dev, "height", height);
|
541 |
qdev_prop_set_uint16(dev, "depth", depth);
|
542 |
qdev_init_nofail(dev); |
543 |
s = sysbus_from_qdev(dev); |
544 |
/* 8-bit plane */
|
545 |
sysbus_mmio_map(s, 0, addr + 0x00800000ULL); |
546 |
/* DAC */
|
547 |
sysbus_mmio_map(s, 1, addr + 0x00200000ULL); |
548 |
/* TEC (dummy) */
|
549 |
sysbus_mmio_map(s, 2, addr + 0x00700000ULL); |
550 |
/* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
|
551 |
sysbus_mmio_map(s, 3, addr + 0x00301000ULL); |
552 |
if (depth == 24) { |
553 |
/* 24-bit plane */
|
554 |
sysbus_mmio_map(s, 4, addr + 0x02000000ULL); |
555 |
/* Control plane */
|
556 |
sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); |
557 |
} else {
|
558 |
/* THC 8 bit (dummy) */
|
559 |
sysbus_mmio_map(s, 4, addr + 0x00300000ULL); |
560 |
} |
561 |
} |
562 |
|
563 |
/* NCR89C100/MACIO Internal ID register */
|
564 |
static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
565 |
|
566 |
static void idreg_init(target_phys_addr_t addr) |
567 |
{ |
568 |
DeviceState *dev; |
569 |
SysBusDevice *s; |
570 |
|
571 |
dev = qdev_create(NULL, "macio_idreg"); |
572 |
qdev_init_nofail(dev); |
573 |
s = sysbus_from_qdev(dev); |
574 |
|
575 |
sysbus_mmio_map(s, 0, addr);
|
576 |
cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
|
577 |
} |
578 |
|
579 |
static int idreg_init1(SysBusDevice *dev) |
580 |
{ |
581 |
ram_addr_t idreg_offset; |
582 |
|
583 |
idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
|
584 |
sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
|
585 |
return 0; |
586 |
} |
587 |
|
588 |
static SysBusDeviceInfo idreg_info = {
|
589 |
.init = idreg_init1, |
590 |
.qdev.name = "macio_idreg",
|
591 |
.qdev.size = sizeof(SysBusDevice),
|
592 |
}; |
593 |
|
594 |
static void idreg_register_devices(void) |
595 |
{ |
596 |
sysbus_register_withprop(&idreg_info); |
597 |
} |
598 |
|
599 |
device_init(idreg_register_devices); |
600 |
|
601 |
/* Boot PROM (OpenBIOS) */
|
602 |
static void prom_init(target_phys_addr_t addr, const char *bios_name) |
603 |
{ |
604 |
DeviceState *dev; |
605 |
SysBusDevice *s; |
606 |
char *filename;
|
607 |
int ret;
|
608 |
|
609 |
dev = qdev_create(NULL, "openprom"); |
610 |
qdev_init_nofail(dev); |
611 |
s = sysbus_from_qdev(dev); |
612 |
|
613 |
sysbus_mmio_map(s, 0, addr);
|
614 |
|
615 |
/* load boot prom */
|
616 |
if (bios_name == NULL) { |
617 |
bios_name = PROM_FILENAME; |
618 |
} |
619 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
620 |
if (filename) {
|
621 |
ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL, |
622 |
1, ELF_MACHINE, 0); |
623 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
624 |
ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
625 |
} |
626 |
qemu_free(filename); |
627 |
} else {
|
628 |
ret = -1;
|
629 |
} |
630 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
631 |
fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
632 |
exit(1);
|
633 |
} |
634 |
} |
635 |
|
636 |
static int prom_init1(SysBusDevice *dev) |
637 |
{ |
638 |
ram_addr_t prom_offset; |
639 |
|
640 |
prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
641 |
sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
642 |
return 0; |
643 |
} |
644 |
|
645 |
static SysBusDeviceInfo prom_info = {
|
646 |
.init = prom_init1, |
647 |
.qdev.name = "openprom",
|
648 |
.qdev.size = sizeof(SysBusDevice),
|
649 |
.qdev.props = (Property[]) { |
650 |
{/* end of property list */}
|
651 |
} |
652 |
}; |
653 |
|
654 |
static void prom_register_devices(void) |
655 |
{ |
656 |
sysbus_register_withprop(&prom_info); |
657 |
} |
658 |
|
659 |
device_init(prom_register_devices); |
660 |
|
661 |
typedef struct RamDevice |
662 |
{ |
663 |
SysBusDevice busdev; |
664 |
uint64_t size; |
665 |
} RamDevice; |
666 |
|
667 |
/* System RAM */
|
668 |
static int ram_init1(SysBusDevice *dev) |
669 |
{ |
670 |
ram_addr_t RAM_size, ram_offset; |
671 |
RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
672 |
|
673 |
RAM_size = d->size; |
674 |
|
675 |
ram_offset = qemu_ram_alloc(RAM_size); |
676 |
sysbus_init_mmio(dev, RAM_size, ram_offset); |
677 |
return 0; |
678 |
} |
679 |
|
680 |
static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, |
681 |
uint64_t max_mem) |
682 |
{ |
683 |
DeviceState *dev; |
684 |
SysBusDevice *s; |
685 |
RamDevice *d; |
686 |
|
687 |
/* allocate RAM */
|
688 |
if ((uint64_t)RAM_size > max_mem) {
|
689 |
fprintf(stderr, |
690 |
"qemu: Too much memory for this machine: %d, maximum %d\n",
|
691 |
(unsigned int)(RAM_size / (1024 * 1024)), |
692 |
(unsigned int)(max_mem / (1024 * 1024))); |
693 |
exit(1);
|
694 |
} |
695 |
dev = qdev_create(NULL, "memory"); |
696 |
s = sysbus_from_qdev(dev); |
697 |
|
698 |
d = FROM_SYSBUS(RamDevice, s); |
699 |
d->size = RAM_size; |
700 |
qdev_init_nofail(dev); |
701 |
|
702 |
sysbus_mmio_map(s, 0, addr);
|
703 |
} |
704 |
|
705 |
static SysBusDeviceInfo ram_info = {
|
706 |
.init = ram_init1, |
707 |
.qdev.name = "memory",
|
708 |
.qdev.size = sizeof(RamDevice),
|
709 |
.qdev.props = (Property[]) { |
710 |
DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
711 |
DEFINE_PROP_END_OF_LIST(), |
712 |
} |
713 |
}; |
714 |
|
715 |
static void ram_register_devices(void) |
716 |
{ |
717 |
sysbus_register_withprop(&ram_info); |
718 |
} |
719 |
|
720 |
device_init(ram_register_devices); |
721 |
|
722 |
static CPUState *cpu_devinit(const char *cpu_model, unsigned int id, |
723 |
uint64_t prom_addr, qemu_irq **cpu_irqs) |
724 |
{ |
725 |
CPUState *env; |
726 |
|
727 |
env = cpu_init(cpu_model); |
728 |
if (!env) {
|
729 |
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
730 |
exit(1);
|
731 |
} |
732 |
|
733 |
cpu_sparc_set_id(env, id); |
734 |
if (id == 0) { |
735 |
qemu_register_reset(main_cpu_reset, env); |
736 |
} else {
|
737 |
qemu_register_reset(secondary_cpu_reset, env); |
738 |
env->halted = 1;
|
739 |
} |
740 |
*cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
741 |
env->prom_addr = prom_addr; |
742 |
|
743 |
return env;
|
744 |
} |
745 |
|
746 |
static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
747 |
const char *boot_device, |
748 |
const char *kernel_filename, |
749 |
const char *kernel_cmdline, |
750 |
const char *initrd_filename, const char *cpu_model) |
751 |
{ |
752 |
CPUState *envs[MAX_CPUS]; |
753 |
unsigned int i; |
754 |
void *iommu, *espdma, *ledma, *nvram;
|
755 |
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
|
756 |
espdma_irq, ledma_irq; |
757 |
qemu_irq esp_reset; |
758 |
qemu_irq fdc_tc; |
759 |
qemu_irq *cpu_halt; |
760 |
unsigned long kernel_size; |
761 |
DriveInfo *fd[MAX_FD]; |
762 |
void *fw_cfg;
|
763 |
|
764 |
/* init CPUs */
|
765 |
if (!cpu_model)
|
766 |
cpu_model = hwdef->default_cpu_model; |
767 |
|
768 |
for(i = 0; i < smp_cpus; i++) { |
769 |
envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
770 |
} |
771 |
|
772 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
773 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
774 |
|
775 |
|
776 |
/* set up devices */
|
777 |
ram_init(0, RAM_size, hwdef->max_mem);
|
778 |
|
779 |
prom_init(hwdef->slavio_base, bios_name); |
780 |
|
781 |
slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
782 |
hwdef->intctl_base + 0x10000ULL,
|
783 |
cpu_irqs); |
784 |
|
785 |
for (i = 0; i < 32; i++) { |
786 |
slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
787 |
} |
788 |
for (i = 0; i < MAX_CPUS; i++) { |
789 |
slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
|
790 |
} |
791 |
|
792 |
if (hwdef->idreg_base) {
|
793 |
idreg_init(hwdef->idreg_base); |
794 |
} |
795 |
|
796 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
797 |
slavio_irq[30]);
|
798 |
|
799 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
|
800 |
iommu, &espdma_irq); |
801 |
|
802 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
803 |
slavio_irq[16], iommu, &ledma_irq);
|
804 |
|
805 |
if (graphic_depth != 8 && graphic_depth != 24) { |
806 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
807 |
exit (1);
|
808 |
} |
809 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
810 |
graphic_depth); |
811 |
|
812 |
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
813 |
|
814 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
815 |
|
816 |
slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
|
817 |
|
818 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
|
819 |
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
820 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
821 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
822 |
escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], |
823 |
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
824 |
|
825 |
cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
826 |
slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
827 |
slavio_irq[30], fdc_tc);
|
828 |
|
829 |
if (hwdef->apc_base) {
|
830 |
apc_init(hwdef->apc_base, cpu_halt[0]);
|
831 |
} |
832 |
|
833 |
if (hwdef->fd_base) {
|
834 |
/* there is zero or one floppy drive */
|
835 |
memset(fd, 0, sizeof(fd)); |
836 |
fd[0] = drive_get(IF_FLOPPY, 0, 0); |
837 |
sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
|
838 |
&fdc_tc); |
839 |
} |
840 |
|
841 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
842 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
843 |
exit(1);
|
844 |
} |
845 |
|
846 |
esp_reset = qdev_get_gpio_in(espdma, 0);
|
847 |
esp_init(hwdef->esp_base, 2,
|
848 |
espdma_memory_read, espdma_memory_write, |
849 |
espdma, espdma_irq, &esp_reset); |
850 |
|
851 |
|
852 |
if (hwdef->cs_base) {
|
853 |
sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
|
854 |
slavio_irq[5]);
|
855 |
} |
856 |
|
857 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
858 |
RAM_size); |
859 |
|
860 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
861 |
boot_device, RAM_size, kernel_size, graphic_width, |
862 |
graphic_height, graphic_depth, hwdef->nvram_machine_id, |
863 |
"Sun4m");
|
864 |
|
865 |
if (hwdef->ecc_base)
|
866 |
ecc_init(hwdef->ecc_base, slavio_irq[28],
|
867 |
hwdef->ecc_version); |
868 |
|
869 |
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
870 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
871 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
872 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
873 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
874 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
875 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
876 |
if (kernel_cmdline) {
|
877 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
878 |
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
879 |
} else {
|
880 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
881 |
} |
882 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
883 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
884 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
885 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
886 |
} |
887 |
|
888 |
enum {
|
889 |
ss2_id = 0,
|
890 |
ss5_id = 32,
|
891 |
vger_id, |
892 |
lx_id, |
893 |
ss4_id, |
894 |
scls_id, |
895 |
sbook_id, |
896 |
ss10_id = 64,
|
897 |
ss20_id, |
898 |
ss600mp_id, |
899 |
ss1000_id = 96,
|
900 |
ss2000_id, |
901 |
}; |
902 |
|
903 |
static const struct sun4m_hwdef sun4m_hwdefs[] = { |
904 |
/* SS-5 */
|
905 |
{ |
906 |
.iommu_base = 0x10000000,
|
907 |
.tcx_base = 0x50000000,
|
908 |
.cs_base = 0x6c000000,
|
909 |
.slavio_base = 0x70000000,
|
910 |
.ms_kb_base = 0x71000000,
|
911 |
.serial_base = 0x71100000,
|
912 |
.nvram_base = 0x71200000,
|
913 |
.fd_base = 0x71400000,
|
914 |
.counter_base = 0x71d00000,
|
915 |
.intctl_base = 0x71e00000,
|
916 |
.idreg_base = 0x78000000,
|
917 |
.dma_base = 0x78400000,
|
918 |
.esp_base = 0x78800000,
|
919 |
.le_base = 0x78c00000,
|
920 |
.apc_base = 0x6a000000,
|
921 |
.aux1_base = 0x71900000,
|
922 |
.aux2_base = 0x71910000,
|
923 |
.nvram_machine_id = 0x80,
|
924 |
.machine_id = ss5_id, |
925 |
.iommu_version = 0x05000000,
|
926 |
.max_mem = 0x10000000,
|
927 |
.default_cpu_model = "Fujitsu MB86904",
|
928 |
}, |
929 |
/* SS-10 */
|
930 |
{ |
931 |
.iommu_base = 0xfe0000000ULL,
|
932 |
.tcx_base = 0xe20000000ULL,
|
933 |
.slavio_base = 0xff0000000ULL,
|
934 |
.ms_kb_base = 0xff1000000ULL,
|
935 |
.serial_base = 0xff1100000ULL,
|
936 |
.nvram_base = 0xff1200000ULL,
|
937 |
.fd_base = 0xff1700000ULL,
|
938 |
.counter_base = 0xff1300000ULL,
|
939 |
.intctl_base = 0xff1400000ULL,
|
940 |
.idreg_base = 0xef0000000ULL,
|
941 |
.dma_base = 0xef0400000ULL,
|
942 |
.esp_base = 0xef0800000ULL,
|
943 |
.le_base = 0xef0c00000ULL,
|
944 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
945 |
.aux1_base = 0xff1800000ULL,
|
946 |
.aux2_base = 0xff1a01000ULL,
|
947 |
.ecc_base = 0xf00000000ULL,
|
948 |
.ecc_version = 0x10000000, // version 0, implementation 1 |
949 |
.nvram_machine_id = 0x72,
|
950 |
.machine_id = ss10_id, |
951 |
.iommu_version = 0x03000000,
|
952 |
.max_mem = 0xf00000000ULL,
|
953 |
.default_cpu_model = "TI SuperSparc II",
|
954 |
}, |
955 |
/* SS-600MP */
|
956 |
{ |
957 |
.iommu_base = 0xfe0000000ULL,
|
958 |
.tcx_base = 0xe20000000ULL,
|
959 |
.slavio_base = 0xff0000000ULL,
|
960 |
.ms_kb_base = 0xff1000000ULL,
|
961 |
.serial_base = 0xff1100000ULL,
|
962 |
.nvram_base = 0xff1200000ULL,
|
963 |
.counter_base = 0xff1300000ULL,
|
964 |
.intctl_base = 0xff1400000ULL,
|
965 |
.dma_base = 0xef0081000ULL,
|
966 |
.esp_base = 0xef0080000ULL,
|
967 |
.le_base = 0xef0060000ULL,
|
968 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
969 |
.aux1_base = 0xff1800000ULL,
|
970 |
.aux2_base = 0xff1a01000ULL, // XXX should not exist |
971 |
.ecc_base = 0xf00000000ULL,
|
972 |
.ecc_version = 0x00000000, // version 0, implementation 0 |
973 |
.nvram_machine_id = 0x71,
|
974 |
.machine_id = ss600mp_id, |
975 |
.iommu_version = 0x01000000,
|
976 |
.max_mem = 0xf00000000ULL,
|
977 |
.default_cpu_model = "TI SuperSparc II",
|
978 |
}, |
979 |
/* SS-20 */
|
980 |
{ |
981 |
.iommu_base = 0xfe0000000ULL,
|
982 |
.tcx_base = 0xe20000000ULL,
|
983 |
.slavio_base = 0xff0000000ULL,
|
984 |
.ms_kb_base = 0xff1000000ULL,
|
985 |
.serial_base = 0xff1100000ULL,
|
986 |
.nvram_base = 0xff1200000ULL,
|
987 |
.fd_base = 0xff1700000ULL,
|
988 |
.counter_base = 0xff1300000ULL,
|
989 |
.intctl_base = 0xff1400000ULL,
|
990 |
.idreg_base = 0xef0000000ULL,
|
991 |
.dma_base = 0xef0400000ULL,
|
992 |
.esp_base = 0xef0800000ULL,
|
993 |
.le_base = 0xef0c00000ULL,
|
994 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
995 |
.aux1_base = 0xff1800000ULL,
|
996 |
.aux2_base = 0xff1a01000ULL,
|
997 |
.ecc_base = 0xf00000000ULL,
|
998 |
.ecc_version = 0x20000000, // version 0, implementation 2 |
999 |
.nvram_machine_id = 0x72,
|
1000 |
.machine_id = ss20_id, |
1001 |
.iommu_version = 0x13000000,
|
1002 |
.max_mem = 0xf00000000ULL,
|
1003 |
.default_cpu_model = "TI SuperSparc II",
|
1004 |
}, |
1005 |
/* Voyager */
|
1006 |
{ |
1007 |
.iommu_base = 0x10000000,
|
1008 |
.tcx_base = 0x50000000,
|
1009 |
.slavio_base = 0x70000000,
|
1010 |
.ms_kb_base = 0x71000000,
|
1011 |
.serial_base = 0x71100000,
|
1012 |
.nvram_base = 0x71200000,
|
1013 |
.fd_base = 0x71400000,
|
1014 |
.counter_base = 0x71d00000,
|
1015 |
.intctl_base = 0x71e00000,
|
1016 |
.idreg_base = 0x78000000,
|
1017 |
.dma_base = 0x78400000,
|
1018 |
.esp_base = 0x78800000,
|
1019 |
.le_base = 0x78c00000,
|
1020 |
.apc_base = 0x71300000, // pmc |
1021 |
.aux1_base = 0x71900000,
|
1022 |
.aux2_base = 0x71910000,
|
1023 |
.nvram_machine_id = 0x80,
|
1024 |
.machine_id = vger_id, |
1025 |
.iommu_version = 0x05000000,
|
1026 |
.max_mem = 0x10000000,
|
1027 |
.default_cpu_model = "Fujitsu MB86904",
|
1028 |
}, |
1029 |
/* LX */
|
1030 |
{ |
1031 |
.iommu_base = 0x10000000,
|
1032 |
.tcx_base = 0x50000000,
|
1033 |
.slavio_base = 0x70000000,
|
1034 |
.ms_kb_base = 0x71000000,
|
1035 |
.serial_base = 0x71100000,
|
1036 |
.nvram_base = 0x71200000,
|
1037 |
.fd_base = 0x71400000,
|
1038 |
.counter_base = 0x71d00000,
|
1039 |
.intctl_base = 0x71e00000,
|
1040 |
.idreg_base = 0x78000000,
|
1041 |
.dma_base = 0x78400000,
|
1042 |
.esp_base = 0x78800000,
|
1043 |
.le_base = 0x78c00000,
|
1044 |
.aux1_base = 0x71900000,
|
1045 |
.aux2_base = 0x71910000,
|
1046 |
.nvram_machine_id = 0x80,
|
1047 |
.machine_id = lx_id, |
1048 |
.iommu_version = 0x04000000,
|
1049 |
.max_mem = 0x10000000,
|
1050 |
.default_cpu_model = "TI MicroSparc I",
|
1051 |
}, |
1052 |
/* SS-4 */
|
1053 |
{ |
1054 |
.iommu_base = 0x10000000,
|
1055 |
.tcx_base = 0x50000000,
|
1056 |
.cs_base = 0x6c000000,
|
1057 |
.slavio_base = 0x70000000,
|
1058 |
.ms_kb_base = 0x71000000,
|
1059 |
.serial_base = 0x71100000,
|
1060 |
.nvram_base = 0x71200000,
|
1061 |
.fd_base = 0x71400000,
|
1062 |
.counter_base = 0x71d00000,
|
1063 |
.intctl_base = 0x71e00000,
|
1064 |
.idreg_base = 0x78000000,
|
1065 |
.dma_base = 0x78400000,
|
1066 |
.esp_base = 0x78800000,
|
1067 |
.le_base = 0x78c00000,
|
1068 |
.apc_base = 0x6a000000,
|
1069 |
.aux1_base = 0x71900000,
|
1070 |
.aux2_base = 0x71910000,
|
1071 |
.nvram_machine_id = 0x80,
|
1072 |
.machine_id = ss4_id, |
1073 |
.iommu_version = 0x05000000,
|
1074 |
.max_mem = 0x10000000,
|
1075 |
.default_cpu_model = "Fujitsu MB86904",
|
1076 |
}, |
1077 |
/* SPARCClassic */
|
1078 |
{ |
1079 |
.iommu_base = 0x10000000,
|
1080 |
.tcx_base = 0x50000000,
|
1081 |
.slavio_base = 0x70000000,
|
1082 |
.ms_kb_base = 0x71000000,
|
1083 |
.serial_base = 0x71100000,
|
1084 |
.nvram_base = 0x71200000,
|
1085 |
.fd_base = 0x71400000,
|
1086 |
.counter_base = 0x71d00000,
|
1087 |
.intctl_base = 0x71e00000,
|
1088 |
.idreg_base = 0x78000000,
|
1089 |
.dma_base = 0x78400000,
|
1090 |
.esp_base = 0x78800000,
|
1091 |
.le_base = 0x78c00000,
|
1092 |
.apc_base = 0x6a000000,
|
1093 |
.aux1_base = 0x71900000,
|
1094 |
.aux2_base = 0x71910000,
|
1095 |
.nvram_machine_id = 0x80,
|
1096 |
.machine_id = scls_id, |
1097 |
.iommu_version = 0x05000000,
|
1098 |
.max_mem = 0x10000000,
|
1099 |
.default_cpu_model = "TI MicroSparc I",
|
1100 |
}, |
1101 |
/* SPARCbook */
|
1102 |
{ |
1103 |
.iommu_base = 0x10000000,
|
1104 |
.tcx_base = 0x50000000, // XXX |
1105 |
.slavio_base = 0x70000000,
|
1106 |
.ms_kb_base = 0x71000000,
|
1107 |
.serial_base = 0x71100000,
|
1108 |
.nvram_base = 0x71200000,
|
1109 |
.fd_base = 0x71400000,
|
1110 |
.counter_base = 0x71d00000,
|
1111 |
.intctl_base = 0x71e00000,
|
1112 |
.idreg_base = 0x78000000,
|
1113 |
.dma_base = 0x78400000,
|
1114 |
.esp_base = 0x78800000,
|
1115 |
.le_base = 0x78c00000,
|
1116 |
.apc_base = 0x6a000000,
|
1117 |
.aux1_base = 0x71900000,
|
1118 |
.aux2_base = 0x71910000,
|
1119 |
.nvram_machine_id = 0x80,
|
1120 |
.machine_id = sbook_id, |
1121 |
.iommu_version = 0x05000000,
|
1122 |
.max_mem = 0x10000000,
|
1123 |
.default_cpu_model = "TI MicroSparc I",
|
1124 |
}, |
1125 |
}; |
1126 |
|
1127 |
/* SPARCstation 5 hardware initialisation */
|
1128 |
static void ss5_init(ram_addr_t RAM_size, |
1129 |
const char *boot_device, |
1130 |
const char *kernel_filename, const char *kernel_cmdline, |
1131 |
const char *initrd_filename, const char *cpu_model) |
1132 |
{ |
1133 |
sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1134 |
kernel_cmdline, initrd_filename, cpu_model); |
1135 |
} |
1136 |
|
1137 |
/* SPARCstation 10 hardware initialisation */
|
1138 |
static void ss10_init(ram_addr_t RAM_size, |
1139 |
const char *boot_device, |
1140 |
const char *kernel_filename, const char *kernel_cmdline, |
1141 |
const char *initrd_filename, const char *cpu_model) |
1142 |
{ |
1143 |
sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1144 |
kernel_cmdline, initrd_filename, cpu_model); |
1145 |
} |
1146 |
|
1147 |
/* SPARCserver 600MP hardware initialisation */
|
1148 |
static void ss600mp_init(ram_addr_t RAM_size, |
1149 |
const char *boot_device, |
1150 |
const char *kernel_filename, |
1151 |
const char *kernel_cmdline, |
1152 |
const char *initrd_filename, const char *cpu_model) |
1153 |
{ |
1154 |
sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
|
1155 |
kernel_cmdline, initrd_filename, cpu_model); |
1156 |
} |
1157 |
|
1158 |
/* SPARCstation 20 hardware initialisation */
|
1159 |
static void ss20_init(ram_addr_t RAM_size, |
1160 |
const char *boot_device, |
1161 |
const char *kernel_filename, const char *kernel_cmdline, |
1162 |
const char *initrd_filename, const char *cpu_model) |
1163 |
{ |
1164 |
sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
|
1165 |
kernel_cmdline, initrd_filename, cpu_model); |
1166 |
} |
1167 |
|
1168 |
/* SPARCstation Voyager hardware initialisation */
|
1169 |
static void vger_init(ram_addr_t RAM_size, |
1170 |
const char *boot_device, |
1171 |
const char *kernel_filename, const char *kernel_cmdline, |
1172 |
const char *initrd_filename, const char *cpu_model) |
1173 |
{ |
1174 |
sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
|
1175 |
kernel_cmdline, initrd_filename, cpu_model); |
1176 |
} |
1177 |
|
1178 |
/* SPARCstation LX hardware initialisation */
|
1179 |
static void ss_lx_init(ram_addr_t RAM_size, |
1180 |
const char *boot_device, |
1181 |
const char *kernel_filename, const char *kernel_cmdline, |
1182 |
const char *initrd_filename, const char *cpu_model) |
1183 |
{ |
1184 |
sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
|
1185 |
kernel_cmdline, initrd_filename, cpu_model); |
1186 |
} |
1187 |
|
1188 |
/* SPARCstation 4 hardware initialisation */
|
1189 |
static void ss4_init(ram_addr_t RAM_size, |
1190 |
const char *boot_device, |
1191 |
const char *kernel_filename, const char *kernel_cmdline, |
1192 |
const char *initrd_filename, const char *cpu_model) |
1193 |
{ |
1194 |
sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
|
1195 |
kernel_cmdline, initrd_filename, cpu_model); |
1196 |
} |
1197 |
|
1198 |
/* SPARCClassic hardware initialisation */
|
1199 |
static void scls_init(ram_addr_t RAM_size, |
1200 |
const char *boot_device, |
1201 |
const char *kernel_filename, const char *kernel_cmdline, |
1202 |
const char *initrd_filename, const char *cpu_model) |
1203 |
{ |
1204 |
sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
|
1205 |
kernel_cmdline, initrd_filename, cpu_model); |
1206 |
} |
1207 |
|
1208 |
/* SPARCbook hardware initialisation */
|
1209 |
static void sbook_init(ram_addr_t RAM_size, |
1210 |
const char *boot_device, |
1211 |
const char *kernel_filename, const char *kernel_cmdline, |
1212 |
const char *initrd_filename, const char *cpu_model) |
1213 |
{ |
1214 |
sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
|
1215 |
kernel_cmdline, initrd_filename, cpu_model); |
1216 |
} |
1217 |
|
1218 |
static QEMUMachine ss5_machine = {
|
1219 |
.name = "SS-5",
|
1220 |
.desc = "Sun4m platform, SPARCstation 5",
|
1221 |
.init = ss5_init, |
1222 |
.use_scsi = 1,
|
1223 |
.is_default = 1,
|
1224 |
}; |
1225 |
|
1226 |
static QEMUMachine ss10_machine = {
|
1227 |
.name = "SS-10",
|
1228 |
.desc = "Sun4m platform, SPARCstation 10",
|
1229 |
.init = ss10_init, |
1230 |
.use_scsi = 1,
|
1231 |
.max_cpus = 4,
|
1232 |
}; |
1233 |
|
1234 |
static QEMUMachine ss600mp_machine = {
|
1235 |
.name = "SS-600MP",
|
1236 |
.desc = "Sun4m platform, SPARCserver 600MP",
|
1237 |
.init = ss600mp_init, |
1238 |
.use_scsi = 1,
|
1239 |
.max_cpus = 4,
|
1240 |
}; |
1241 |
|
1242 |
static QEMUMachine ss20_machine = {
|
1243 |
.name = "SS-20",
|
1244 |
.desc = "Sun4m platform, SPARCstation 20",
|
1245 |
.init = ss20_init, |
1246 |
.use_scsi = 1,
|
1247 |
.max_cpus = 4,
|
1248 |
}; |
1249 |
|
1250 |
static QEMUMachine voyager_machine = {
|
1251 |
.name = "Voyager",
|
1252 |
.desc = "Sun4m platform, SPARCstation Voyager",
|
1253 |
.init = vger_init, |
1254 |
.use_scsi = 1,
|
1255 |
}; |
1256 |
|
1257 |
static QEMUMachine ss_lx_machine = {
|
1258 |
.name = "LX",
|
1259 |
.desc = "Sun4m platform, SPARCstation LX",
|
1260 |
.init = ss_lx_init, |
1261 |
.use_scsi = 1,
|
1262 |
}; |
1263 |
|
1264 |
static QEMUMachine ss4_machine = {
|
1265 |
.name = "SS-4",
|
1266 |
.desc = "Sun4m platform, SPARCstation 4",
|
1267 |
.init = ss4_init, |
1268 |
.use_scsi = 1,
|
1269 |
}; |
1270 |
|
1271 |
static QEMUMachine scls_machine = {
|
1272 |
.name = "SPARCClassic",
|
1273 |
.desc = "Sun4m platform, SPARCClassic",
|
1274 |
.init = scls_init, |
1275 |
.use_scsi = 1,
|
1276 |
}; |
1277 |
|
1278 |
static QEMUMachine sbook_machine = {
|
1279 |
.name = "SPARCbook",
|
1280 |
.desc = "Sun4m platform, SPARCbook",
|
1281 |
.init = sbook_init, |
1282 |
.use_scsi = 1,
|
1283 |
}; |
1284 |
|
1285 |
static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1286 |
/* SS-1000 */
|
1287 |
{ |
1288 |
.iounit_bases = { |
1289 |
0xfe0200000ULL,
|
1290 |
0xfe1200000ULL,
|
1291 |
0xfe2200000ULL,
|
1292 |
0xfe3200000ULL,
|
1293 |
-1,
|
1294 |
}, |
1295 |
.tcx_base = 0x820000000ULL,
|
1296 |
.slavio_base = 0xf00000000ULL,
|
1297 |
.ms_kb_base = 0xf00240000ULL,
|
1298 |
.serial_base = 0xf00200000ULL,
|
1299 |
.nvram_base = 0xf00280000ULL,
|
1300 |
.counter_base = 0xf00300000ULL,
|
1301 |
.espdma_base = 0x800081000ULL,
|
1302 |
.esp_base = 0x800080000ULL,
|
1303 |
.ledma_base = 0x800040000ULL,
|
1304 |
.le_base = 0x800060000ULL,
|
1305 |
.sbi_base = 0xf02800000ULL,
|
1306 |
.nvram_machine_id = 0x80,
|
1307 |
.machine_id = ss1000_id, |
1308 |
.iounit_version = 0x03000000,
|
1309 |
.max_mem = 0xf00000000ULL,
|
1310 |
.default_cpu_model = "TI SuperSparc II",
|
1311 |
}, |
1312 |
/* SS-2000 */
|
1313 |
{ |
1314 |
.iounit_bases = { |
1315 |
0xfe0200000ULL,
|
1316 |
0xfe1200000ULL,
|
1317 |
0xfe2200000ULL,
|
1318 |
0xfe3200000ULL,
|
1319 |
0xfe4200000ULL,
|
1320 |
}, |
1321 |
.tcx_base = 0x820000000ULL,
|
1322 |
.slavio_base = 0xf00000000ULL,
|
1323 |
.ms_kb_base = 0xf00240000ULL,
|
1324 |
.serial_base = 0xf00200000ULL,
|
1325 |
.nvram_base = 0xf00280000ULL,
|
1326 |
.counter_base = 0xf00300000ULL,
|
1327 |
.espdma_base = 0x800081000ULL,
|
1328 |
.esp_base = 0x800080000ULL,
|
1329 |
.ledma_base = 0x800040000ULL,
|
1330 |
.le_base = 0x800060000ULL,
|
1331 |
.sbi_base = 0xf02800000ULL,
|
1332 |
.nvram_machine_id = 0x80,
|
1333 |
.machine_id = ss2000_id, |
1334 |
.iounit_version = 0x03000000,
|
1335 |
.max_mem = 0xf00000000ULL,
|
1336 |
.default_cpu_model = "TI SuperSparc II",
|
1337 |
}, |
1338 |
}; |
1339 |
|
1340 |
static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
|
1341 |
{ |
1342 |
DeviceState *dev; |
1343 |
SysBusDevice *s; |
1344 |
unsigned int i; |
1345 |
|
1346 |
dev = qdev_create(NULL, "sbi"); |
1347 |
qdev_init_nofail(dev); |
1348 |
|
1349 |
s = sysbus_from_qdev(dev); |
1350 |
|
1351 |
for (i = 0; i < MAX_CPUS; i++) { |
1352 |
sysbus_connect_irq(s, i, *parent_irq[i]); |
1353 |
} |
1354 |
|
1355 |
sysbus_mmio_map(s, 0, addr);
|
1356 |
|
1357 |
return dev;
|
1358 |
} |
1359 |
|
1360 |
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1361 |
const char *boot_device, |
1362 |
const char *kernel_filename, |
1363 |
const char *kernel_cmdline, |
1364 |
const char *initrd_filename, const char *cpu_model) |
1365 |
{ |
1366 |
CPUState *envs[MAX_CPUS]; |
1367 |
unsigned int i; |
1368 |
void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
|
1369 |
qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
|
1370 |
espdma_irq, ledma_irq; |
1371 |
qemu_irq esp_reset; |
1372 |
unsigned long kernel_size; |
1373 |
void *fw_cfg;
|
1374 |
DeviceState *dev; |
1375 |
|
1376 |
/* init CPUs */
|
1377 |
if (!cpu_model)
|
1378 |
cpu_model = hwdef->default_cpu_model; |
1379 |
|
1380 |
for(i = 0; i < smp_cpus; i++) { |
1381 |
envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
1382 |
} |
1383 |
|
1384 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
1385 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1386 |
|
1387 |
/* set up devices */
|
1388 |
ram_init(0, RAM_size, hwdef->max_mem);
|
1389 |
|
1390 |
prom_init(hwdef->slavio_base, bios_name); |
1391 |
|
1392 |
dev = sbi_init(hwdef->sbi_base, cpu_irqs); |
1393 |
|
1394 |
for (i = 0; i < 32; i++) { |
1395 |
sbi_irq[i] = qdev_get_gpio_in(dev, i); |
1396 |
} |
1397 |
for (i = 0; i < MAX_CPUS; i++) { |
1398 |
sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
|
1399 |
} |
1400 |
|
1401 |
for (i = 0; i < MAX_IOUNITS; i++) |
1402 |
if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1403 |
iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1404 |
hwdef->iounit_version, |
1405 |
sbi_irq[0]);
|
1406 |
|
1407 |
espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
|
1408 |
iounits[0], &espdma_irq);
|
1409 |
|
1410 |
ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
|
1411 |
iounits[0], &ledma_irq);
|
1412 |
|
1413 |
if (graphic_depth != 8 && graphic_depth != 24) { |
1414 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1415 |
exit (1);
|
1416 |
} |
1417 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1418 |
graphic_depth); |
1419 |
|
1420 |
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1421 |
|
1422 |
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
1423 |
|
1424 |
slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
|
1425 |
|
1426 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
|
1427 |
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1428 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1429 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1430 |
escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12], |
1431 |
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
1432 |
|
1433 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
1434 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
1435 |
exit(1);
|
1436 |
} |
1437 |
|
1438 |
esp_reset = qdev_get_gpio_in(espdma, 0);
|
1439 |
esp_init(hwdef->esp_base, 2,
|
1440 |
espdma_memory_read, espdma_memory_write, |
1441 |
espdma, espdma_irq, &esp_reset); |
1442 |
|
1443 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1444 |
RAM_size); |
1445 |
|
1446 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1447 |
boot_device, RAM_size, kernel_size, graphic_width, |
1448 |
graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1449 |
"Sun4d");
|
1450 |
|
1451 |
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1452 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1453 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1454 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1455 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1456 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1457 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1458 |
if (kernel_cmdline) {
|
1459 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1460 |
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
1461 |
} else {
|
1462 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1463 |
} |
1464 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1465 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1466 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1467 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1468 |
} |
1469 |
|
1470 |
/* SPARCserver 1000 hardware initialisation */
|
1471 |
static void ss1000_init(ram_addr_t RAM_size, |
1472 |
const char *boot_device, |
1473 |
const char *kernel_filename, const char *kernel_cmdline, |
1474 |
const char *initrd_filename, const char *cpu_model) |
1475 |
{ |
1476 |
sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1477 |
kernel_cmdline, initrd_filename, cpu_model); |
1478 |
} |
1479 |
|
1480 |
/* SPARCcenter 2000 hardware initialisation */
|
1481 |
static void ss2000_init(ram_addr_t RAM_size, |
1482 |
const char *boot_device, |
1483 |
const char *kernel_filename, const char *kernel_cmdline, |
1484 |
const char *initrd_filename, const char *cpu_model) |
1485 |
{ |
1486 |
sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1487 |
kernel_cmdline, initrd_filename, cpu_model); |
1488 |
} |
1489 |
|
1490 |
static QEMUMachine ss1000_machine = {
|
1491 |
.name = "SS-1000",
|
1492 |
.desc = "Sun4d platform, SPARCserver 1000",
|
1493 |
.init = ss1000_init, |
1494 |
.use_scsi = 1,
|
1495 |
.max_cpus = 8,
|
1496 |
}; |
1497 |
|
1498 |
static QEMUMachine ss2000_machine = {
|
1499 |
.name = "SS-2000",
|
1500 |
.desc = "Sun4d platform, SPARCcenter 2000",
|
1501 |
.init = ss2000_init, |
1502 |
.use_scsi = 1,
|
1503 |
.max_cpus = 20,
|
1504 |
}; |
1505 |
|
1506 |
static const struct sun4c_hwdef sun4c_hwdefs[] = { |
1507 |
/* SS-2 */
|
1508 |
{ |
1509 |
.iommu_base = 0xf8000000,
|
1510 |
.tcx_base = 0xfe000000,
|
1511 |
.slavio_base = 0xf6000000,
|
1512 |
.intctl_base = 0xf5000000,
|
1513 |
.counter_base = 0xf3000000,
|
1514 |
.ms_kb_base = 0xf0000000,
|
1515 |
.serial_base = 0xf1000000,
|
1516 |
.nvram_base = 0xf2000000,
|
1517 |
.fd_base = 0xf7200000,
|
1518 |
.dma_base = 0xf8400000,
|
1519 |
.esp_base = 0xf8800000,
|
1520 |
.le_base = 0xf8c00000,
|
1521 |
.aux1_base = 0xf7400003,
|
1522 |
.nvram_machine_id = 0x55,
|
1523 |
.machine_id = ss2_id, |
1524 |
.max_mem = 0x10000000,
|
1525 |
.default_cpu_model = "Cypress CY7C601",
|
1526 |
}, |
1527 |
}; |
1528 |
|
1529 |
static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
|
1530 |
qemu_irq *parent_irq) |
1531 |
{ |
1532 |
DeviceState *dev; |
1533 |
SysBusDevice *s; |
1534 |
unsigned int i; |
1535 |
|
1536 |
dev = qdev_create(NULL, "sun4c_intctl"); |
1537 |
qdev_init_nofail(dev); |
1538 |
|
1539 |
s = sysbus_from_qdev(dev); |
1540 |
|
1541 |
for (i = 0; i < MAX_PILS; i++) { |
1542 |
sysbus_connect_irq(s, i, parent_irq[i]); |
1543 |
} |
1544 |
sysbus_mmio_map(s, 0, addr);
|
1545 |
|
1546 |
return dev;
|
1547 |
} |
1548 |
|
1549 |
static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
1550 |
const char *boot_device, |
1551 |
const char *kernel_filename, |
1552 |
const char *kernel_cmdline, |
1553 |
const char *initrd_filename, const char *cpu_model) |
1554 |
{ |
1555 |
CPUState *env; |
1556 |
void *iommu, *espdma, *ledma, *nvram;
|
1557 |
qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
|
1558 |
qemu_irq esp_reset; |
1559 |
qemu_irq fdc_tc; |
1560 |
unsigned long kernel_size; |
1561 |
DriveInfo *fd[MAX_FD]; |
1562 |
void *fw_cfg;
|
1563 |
DeviceState *dev; |
1564 |
unsigned int i; |
1565 |
|
1566 |
/* init CPU */
|
1567 |
if (!cpu_model)
|
1568 |
cpu_model = hwdef->default_cpu_model; |
1569 |
|
1570 |
env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
|
1571 |
|
1572 |
/* set up devices */
|
1573 |
ram_init(0, RAM_size, hwdef->max_mem);
|
1574 |
|
1575 |
prom_init(hwdef->slavio_base, bios_name); |
1576 |
|
1577 |
dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs); |
1578 |
|
1579 |
for (i = 0; i < 8; i++) { |
1580 |
slavio_irq[i] = qdev_get_gpio_in(dev, i); |
1581 |
} |
1582 |
|
1583 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
1584 |
slavio_irq[1]);
|
1585 |
|
1586 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
|
1587 |
iommu, &espdma_irq); |
1588 |
|
1589 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
1590 |
slavio_irq[3], iommu, &ledma_irq);
|
1591 |
|
1592 |
if (graphic_depth != 8 && graphic_depth != 24) { |
1593 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1594 |
exit (1);
|
1595 |
} |
1596 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1597 |
graphic_depth); |
1598 |
|
1599 |
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1600 |
|
1601 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2); |
1602 |
|
1603 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
|
1604 |
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1605 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1606 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1607 |
escc_init(hwdef->serial_base, slavio_irq[1],
|
1608 |
slavio_irq[1], serial_hds[0], serial_hds[1], |
1609 |
ESCC_CLOCK, 1);
|
1610 |
|
1611 |
slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc); |
1612 |
|
1613 |
if (hwdef->fd_base != (target_phys_addr_t)-1) { |
1614 |
/* there is zero or one floppy drive */
|
1615 |
memset(fd, 0, sizeof(fd)); |
1616 |
fd[0] = drive_get(IF_FLOPPY, 0, 0); |
1617 |
sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
|
1618 |
&fdc_tc); |
1619 |
} |
1620 |
|
1621 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
1622 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
1623 |
exit(1);
|
1624 |
} |
1625 |
|
1626 |
esp_reset = qdev_get_gpio_in(espdma, 0);
|
1627 |
esp_init(hwdef->esp_base, 2,
|
1628 |
espdma_memory_read, espdma_memory_write, |
1629 |
espdma, espdma_irq, &esp_reset); |
1630 |
|
1631 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1632 |
RAM_size); |
1633 |
|
1634 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1635 |
boot_device, RAM_size, kernel_size, graphic_width, |
1636 |
graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1637 |
"Sun4c");
|
1638 |
|
1639 |
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1640 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1641 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1642 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1643 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1644 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1645 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1646 |
if (kernel_cmdline) {
|
1647 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1648 |
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
1649 |
} else {
|
1650 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1651 |
} |
1652 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1653 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1654 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1655 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1656 |
} |
1657 |
|
1658 |
/* SPARCstation 2 hardware initialisation */
|
1659 |
static void ss2_init(ram_addr_t RAM_size, |
1660 |
const char *boot_device, |
1661 |
const char *kernel_filename, const char *kernel_cmdline, |
1662 |
const char *initrd_filename, const char *cpu_model) |
1663 |
{ |
1664 |
sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1665 |
kernel_cmdline, initrd_filename, cpu_model); |
1666 |
} |
1667 |
|
1668 |
static QEMUMachine ss2_machine = {
|
1669 |
.name = "SS-2",
|
1670 |
.desc = "Sun4c platform, SPARCstation 2",
|
1671 |
.init = ss2_init, |
1672 |
.use_scsi = 1,
|
1673 |
}; |
1674 |
|
1675 |
static void ss2_machine_init(void) |
1676 |
{ |
1677 |
qemu_register_machine(&ss5_machine); |
1678 |
qemu_register_machine(&ss10_machine); |
1679 |
qemu_register_machine(&ss600mp_machine); |
1680 |
qemu_register_machine(&ss20_machine); |
1681 |
qemu_register_machine(&voyager_machine); |
1682 |
qemu_register_machine(&ss_lx_machine); |
1683 |
qemu_register_machine(&ss4_machine); |
1684 |
qemu_register_machine(&scls_machine); |
1685 |
qemu_register_machine(&sbook_machine); |
1686 |
qemu_register_machine(&ss1000_machine); |
1687 |
qemu_register_machine(&ss2000_machine); |
1688 |
qemu_register_machine(&ss2_machine); |
1689 |
} |
1690 |
|
1691 |
machine_init(ss2_machine_init); |