target-ppc: keep only the table version for mfrom
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6007 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use accessors to access fp_status exception_flags
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6006 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix compilation with PRECISE_EMULATION
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6004 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix compilation with CONFIG_SOFTFLOAT
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6003 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove remaining warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5991 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove unneeded include
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5990 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: rework exception code
... also remove two warnings.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove dead code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5988 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: enable SPE and Altivec in user mode
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5965 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: initialize MSR appropriately in user-mode
Mask the initial MSR with the mask from the PowerPC CPU definition.
Noticed by Nathan Froyd.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5964 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: kill a warning
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5952 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: cleanup op_helper.c after TCG conversion
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5951 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: enable access type in MMU
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5950 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: memory load/store rework
Rework the memory load/store:- Unify load/store functions for 32-bit and 64-bit CPU- Don't swap values twice for bit-reverse load/store functions in little endian mode.- On a 64-bit CPU in 32-bit mode, do the address truncation for...
target-ppc: kill a few warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5941 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: disable single stepping
... which left was enabled by mistake.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5918 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Fix use of uninitialized TCG variable in tlbiva
Silences a warning about possible unitialized use of t0.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5915 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SPR accesses to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5909 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5896 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SLB/TLB instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert dcr load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5893 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert msr load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5892 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert POWER bridge instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5891 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert POWER shift instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5882 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: add functions to load/store SPR
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5881 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove unused file op_mem_access.h
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5838 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use ldl/ldub/stl/stub for load/store in op_helper.c
Should not give any performance penality given cpu_mmu_index() isan inline function returning a value from env.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5837 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert PPC 440 instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5836 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert return from interrupt instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5832 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert external load/store instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5831 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert load/store with reservation instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5830 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert lscbx instruction to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5829 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert load/store string instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5828 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert icbi instruction to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5827 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert dcbz instruction to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5826 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert load/store multiple instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5825 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert wait instruction to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5824 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert mfrom instruction to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5823 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove dead code from op.c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5822 c046a42c-6fe2-441c-8c8c-71466251a162
Common cpu_loop_exit prototype
All archs use the same cpu_loop_exit, so move the prototype in a commonheader. i386 was carrying a __hidden attribute, but that was empty forthis arch anyway.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-ppc: convert software TLB instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5819 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert POWER2 load/store instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5805 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SPE load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5804 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: simplify evsplati and evsplatfi
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5803 c046a42c-6fe2-441c-8c8c-71466251a162
Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying thecode and also fixing a use after release issue incpu_break/watchpoint_remove_all.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
target-ppc: convert trap instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5788 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert altivec load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5787 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert FPU load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5786 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix access_type usage
Write env->access_type before a load/store operation instead of relyingon the name of the dyngen operation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5785 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: include the instruction name in load/store handlers name
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5784 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SPE FP ops to TCG
Including a few bug fixes:- Don't clear high part for instruction with 32-bit destination- Fix efscmp* and etstcmp* return value
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5783 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove declaration of removed function from op_helper.h
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5781 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert exceptions generation to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5772 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix TCG type errors introduced in r5754
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5756 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert fp ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5754 c046a42c-6fe2-441c-8c8c-71466251a162
Refactor and enhance break/watchpoint API (Jan Kiszka)
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow thesucceeding enhancements this series comes with.
First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switchingto dynamically allocated data structures that are kept in linked lists....
Refactor translation block CPU state handling (Jan Kiszka)
This patch refactors the way the CPU state is handled that is associatedwith a TB. The basic motivation is to move more arch specific code outof generic files. Specifically the long #ifdef clutter in tb_find_fast()...
Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
as macros should be avoided when possible.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix regression introduced by commit 5729
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5733 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
Attached patch fixes a series of this warningwhen compiling on NetBSD:
warning: array subscript has type 'char'
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5727 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert most SPE integer instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5668 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix TCG argument
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5661 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Remove a few TCG temp variable leaks
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5660 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fixes for gen_op_neg()
- Rename to gen_op_arith_neg for consistency with other functions.- Correctly free TCG temp variable.- Fix the return value in 64-bit mode in case of overflow.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5659 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: gen_op_arith_divw() & gen_op_arith_divd fixes
gen_op_arith_divw():- "deoptimize" gen_op_arith_divw to make it more readable.- Correctly free TCG temp variable
gen_op_arith_divd():- Call the right function.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-ppc: optimize mullw and make the code more readable
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5657 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: indentation fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5656 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix tcg fatal error on i386 host
It looks like the i386 runs out of registers for allocation dueto too many global registers allocated by the ppc target.
Here is a quick and dirty fix that seems to solve the problem.This should be considered as temporary....
target-ppc: fix flags computation for tcg_gen_qemu_st
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5644 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use the new rotr/rotri instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5608 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use the new subfi wrapper
(...and fix rldnm)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5600 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: simplify slw, srw, sld, srd
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5597 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: be more consistent with temp variables naming
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5596 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix srw on 64-bit targets
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5595 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: optimize popcntb
Suggested by Andrzej Zaborowski.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5592 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert 405 MAC instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5591 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert arithmetic functions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5590 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: xer access prototypes no more used & implemented
Revision 5500 of the qemu repository removed all code usingppc_load_xer & ppc_store_xer as well as their implementation.
Another patch fixes it's usage in kvm-userspace for powerpc, but I think...
target-ppc: fix XER accesses on 64-bit targets
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5588 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use consistent names for variables
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5557 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5556 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert rotation instructions to TCG
Also fix rlwimi and rldimi for corner cases.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5555 c046a42c-6fe2-441c-8c8c-71466251a162
Fix typos in PPC TCG conversion.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5521 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert branch related instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5508 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert logical instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5506 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert crf related instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5505 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use the new TCG logical operations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5503 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Convert XER accesses to TCG
Define XER bits as a single register and access them individually toavoid defining 5 32-bit registers (TCG doesn't permit to map 8-bitregisters).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
PPC: fix dcbi instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5495 c046a42c-6fe2-441c-8c8c-71466251a162
PPC: convert SPE logical instructions to TCG
(Nathan Froyd)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5494 c046a42c-6fe2-441c-8c8c-71466251a162
ppc: convert integer load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5493 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix a TCG local variable creation
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5492 c046a42c-6fe2-441c-8c8c-71466251a162
PPC: convert SPE effective address computation to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5491 c046a42c-6fe2-441c-8c8c-71466251a162
PPC: convert effective address computation to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5490 c046a42c-6fe2-441c-8c8c-71466251a162
ppc: fix crash in ppc system single step support
There was a bogus case where two system debug ops get generated. Thispatch removes the broken system debug op. This was a left over aftermaking some changes to correctly generate debug ops on branchoperations inside gen_goto_tb();...
target-ppc: fix computation of XER.{CA, OV} in addme, subfme
(Jocelyn Mayer)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5380 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix mullw/mullwo
Based on patch by Julian Seward.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5379 c046a42c-6fe2-441c-8c8c-71466251a162
Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162