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/*
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 * OpenRISC Programmable Interrupt Controller support.
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 *
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 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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 *                         Feng Gao <gf91597@gmail.com>
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "hw/hw.h"
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#include "cpu.h"
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/* OpenRISC pic handler */
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static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
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{
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    OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
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    CPUState *cs = CPU(cpu);
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    int i;
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    uint32_t irq_bit = 1 << irq;
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    if (irq > 31 || irq < 0) {
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        return;
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    }
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    if (level) {
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        cpu->env.picsr |= irq_bit;
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    } else {
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        cpu->env.picsr &= ~irq_bit;
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    }
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    for (i = 0; i < 32; i++) {
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        if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) {
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            cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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        } else {
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            cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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            cpu->env.picsr &= ~(1 << i);
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        }
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    }
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}
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void cpu_openrisc_pic_init(OpenRISCCPU *cpu)
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{
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    int i;
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    qemu_irq *qi;
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    qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, cpu, NR_IRQS);
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    for (i = 0; i < NR_IRQS; i++) {
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        cpu->env.irq[i] = qi[i];
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    }
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}