Revision e3a4e4b6 hw/cirrus_vga.c
| b/hw/cirrus_vga.c | ||
|---|---|---|
| 800 | 800 |
s->cirrus_blt_srcpitch, |
| 801 | 801 |
s->cirrus_blt_dstaddr, |
| 802 | 802 |
s->cirrus_blt_srcaddr, |
| 803 |
s->sr[0x2f]);
|
|
| 803 |
s->gr[0x2f]);
|
|
| 804 | 804 |
#endif |
| 805 | 805 |
|
| 806 | 806 |
switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
|
| ... | ... | |
| 1042 | 1042 |
else |
| 1043 | 1043 |
offset <<= 12; |
| 1044 | 1044 |
|
| 1045 |
if (s->vram_size <= offset) |
|
| 1045 |
if (s->real_vram_size <= offset)
|
|
| 1046 | 1046 |
limit = 0; |
| 1047 | 1047 |
else |
| 1048 |
limit = s->vram_size - offset; |
|
| 1048 |
limit = s->real_vram_size - offset;
|
|
| 1049 | 1049 |
|
| 1050 | 1050 |
if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
|
| 1051 | 1051 |
if (limit > 0x8000) {
|
| ... | ... | |
| 1213 | 1213 |
#endif |
| 1214 | 1214 |
break; |
| 1215 | 1215 |
case 0x17: // Configuration Readback and Extended Control |
| 1216 |
s->sr[reg_index] = reg_value;
|
|
| 1216 |
s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
|
|
| 1217 | 1217 |
cirrus_update_memory_access(s); |
| 1218 | 1218 |
break; |
| 1219 | 1219 |
default: |
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