root / hw / omap_dma.c @ e3b42536
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1 | b4e3104b | balrog | /*
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2 | b4e3104b | balrog | * TI OMAP DMA gigacell.
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3 | b4e3104b | balrog | *
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4 | b4e3104b | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 | b4e3104b | balrog | * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
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6 | b4e3104b | balrog | *
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7 | b4e3104b | balrog | * This program is free software; you can redistribute it and/or
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8 | b4e3104b | balrog | * modify it under the terms of the GNU General Public License as
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9 | b4e3104b | balrog | * published by the Free Software Foundation; either version 2 of
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10 | b4e3104b | balrog | * the License, or (at your option) any later version.
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11 | b4e3104b | balrog | *
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12 | b4e3104b | balrog | * This program is distributed in the hope that it will be useful,
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13 | b4e3104b | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | b4e3104b | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | b4e3104b | balrog | * GNU General Public License for more details.
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16 | b4e3104b | balrog | *
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17 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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18 | fad6cb1a | aurel32 | * with this program; if not, write to the Free Software Foundation, Inc.,
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19 | fad6cb1a | aurel32 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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20 | b4e3104b | balrog | */
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21 | b4e3104b | balrog | #include "qemu-common.h" |
22 | b4e3104b | balrog | #include "qemu-timer.h" |
23 | b4e3104b | balrog | #include "omap.h" |
24 | b4e3104b | balrog | #include "irq.h" |
25 | afbb5194 | balrog | #include "soc_dma.h" |
26 | b4e3104b | balrog | |
27 | b4e3104b | balrog | struct omap_dma_channel_s {
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28 | b4e3104b | balrog | /* transfer data */
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29 | b4e3104b | balrog | int burst[2]; |
30 | b4e3104b | balrog | int pack[2]; |
31 | 827df9f3 | balrog | int endian[2]; |
32 | 827df9f3 | balrog | int endian_lock[2]; |
33 | 827df9f3 | balrog | int translate[2]; |
34 | b4e3104b | balrog | enum omap_dma_port port[2]; |
35 | b4e3104b | balrog | target_phys_addr_t addr[2];
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36 | b4e3104b | balrog | omap_dma_addressing_t mode[2];
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37 | 827df9f3 | balrog | uint32_t elements; |
38 | b4e3104b | balrog | uint16_t frames; |
39 | 827df9f3 | balrog | int32_t frame_index[2];
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40 | b4e3104b | balrog | int16_t element_index[2];
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41 | b4e3104b | balrog | int data_type;
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42 | b4e3104b | balrog | |
43 | b4e3104b | balrog | /* transfer type */
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44 | b4e3104b | balrog | int transparent_copy;
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45 | b4e3104b | balrog | int constant_fill;
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46 | b4e3104b | balrog | uint32_t color; |
47 | 827df9f3 | balrog | int prefetch;
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48 | b4e3104b | balrog | |
49 | b4e3104b | balrog | /* auto init and linked channel data */
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50 | b4e3104b | balrog | int end_prog;
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51 | b4e3104b | balrog | int repeat;
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52 | b4e3104b | balrog | int auto_init;
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53 | b4e3104b | balrog | int link_enabled;
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54 | b4e3104b | balrog | int link_next_ch;
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55 | b4e3104b | balrog | |
56 | b4e3104b | balrog | /* interruption data */
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57 | b4e3104b | balrog | int interrupts;
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58 | b4e3104b | balrog | int status;
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59 | 827df9f3 | balrog | int cstatus;
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60 | b4e3104b | balrog | |
61 | b4e3104b | balrog | /* state data */
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62 | b4e3104b | balrog | int active;
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63 | b4e3104b | balrog | int enable;
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64 | b4e3104b | balrog | int sync;
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65 | 827df9f3 | balrog | int src_sync;
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66 | b4e3104b | balrog | int pending_request;
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67 | b4e3104b | balrog | int waiting_end_prog;
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68 | b4e3104b | balrog | uint16_t cpc; |
69 | afbb5194 | balrog | int set_update;
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70 | b4e3104b | balrog | |
71 | b4e3104b | balrog | /* sync type */
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72 | b4e3104b | balrog | int fs;
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73 | b4e3104b | balrog | int bs;
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74 | b4e3104b | balrog | |
75 | b4e3104b | balrog | /* compatibility */
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76 | b4e3104b | balrog | int omap_3_1_compatible_disable;
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77 | b4e3104b | balrog | |
78 | b4e3104b | balrog | qemu_irq irq; |
79 | b4e3104b | balrog | struct omap_dma_channel_s *sibling;
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80 | b4e3104b | balrog | |
81 | b4e3104b | balrog | struct omap_dma_reg_set_s {
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82 | b4e3104b | balrog | target_phys_addr_t src, dest; |
83 | b4e3104b | balrog | int frame;
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84 | b4e3104b | balrog | int element;
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85 | 827df9f3 | balrog | int pck_element;
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86 | b4e3104b | balrog | int frame_delta[2]; |
87 | b4e3104b | balrog | int elem_delta[2]; |
88 | b4e3104b | balrog | int frames;
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89 | b4e3104b | balrog | int elements;
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90 | 827df9f3 | balrog | int pck_elements;
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91 | b4e3104b | balrog | } active_set; |
92 | b4e3104b | balrog | |
93 | afbb5194 | balrog | struct soc_dma_ch_s *dma;
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94 | afbb5194 | balrog | |
95 | b4e3104b | balrog | /* unused parameters */
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96 | 827df9f3 | balrog | int write_mode;
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97 | b4e3104b | balrog | int priority;
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98 | b4e3104b | balrog | int interleave_disabled;
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99 | b4e3104b | balrog | int type;
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100 | 827df9f3 | balrog | int suspend;
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101 | 827df9f3 | balrog | int buf_disable;
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102 | b4e3104b | balrog | }; |
103 | b4e3104b | balrog | |
104 | b4e3104b | balrog | struct omap_dma_s {
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105 | afbb5194 | balrog | struct soc_dma_s *dma;
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106 | afbb5194 | balrog | |
107 | b4e3104b | balrog | struct omap_mpu_state_s *mpu;
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108 | b4e3104b | balrog | omap_clk clk; |
109 | 827df9f3 | balrog | qemu_irq irq[4];
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110 | 827df9f3 | balrog | void (*intr_update)(struct omap_dma_s *s); |
111 | b4e3104b | balrog | enum omap_dma_model model;
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112 | b4e3104b | balrog | int omap_3_1_mapping_disabled;
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113 | b4e3104b | balrog | |
114 | 827df9f3 | balrog | uint32_t gcr; |
115 | 827df9f3 | balrog | uint32_t ocp; |
116 | 827df9f3 | balrog | uint32_t caps[5];
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117 | 827df9f3 | balrog | uint32_t irqen[4];
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118 | 827df9f3 | balrog | uint32_t irqstat[4];
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119 | b4e3104b | balrog | |
120 | b4e3104b | balrog | int chans;
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121 | 827df9f3 | balrog | struct omap_dma_channel_s ch[32]; |
122 | b4e3104b | balrog | struct omap_dma_lcd_channel_s lcd_ch;
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123 | b4e3104b | balrog | }; |
124 | b4e3104b | balrog | |
125 | b4e3104b | balrog | /* Interrupts */
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126 | b4e3104b | balrog | #define TIMEOUT_INTR (1 << 0) |
127 | b4e3104b | balrog | #define EVENT_DROP_INTR (1 << 1) |
128 | b4e3104b | balrog | #define HALF_FRAME_INTR (1 << 2) |
129 | b4e3104b | balrog | #define END_FRAME_INTR (1 << 3) |
130 | b4e3104b | balrog | #define LAST_FRAME_INTR (1 << 4) |
131 | b4e3104b | balrog | #define END_BLOCK_INTR (1 << 5) |
132 | b4e3104b | balrog | #define SYNC (1 << 6) |
133 | 827df9f3 | balrog | #define END_PKT_INTR (1 << 7) |
134 | 827df9f3 | balrog | #define TRANS_ERR_INTR (1 << 8) |
135 | 827df9f3 | balrog | #define MISALIGN_INTR (1 << 11) |
136 | b4e3104b | balrog | |
137 | 827df9f3 | balrog | static inline void omap_dma_interrupts_update(struct omap_dma_s *s) |
138 | b4e3104b | balrog | { |
139 | 827df9f3 | balrog | return s->intr_update(s);
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140 | b4e3104b | balrog | } |
141 | b4e3104b | balrog | |
142 | afbb5194 | balrog | static void omap_dma_channel_load(struct omap_dma_channel_s *ch) |
143 | b4e3104b | balrog | { |
144 | b4e3104b | balrog | struct omap_dma_reg_set_s *a = &ch->active_set;
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145 | afbb5194 | balrog | int i, normal;
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146 | b4e3104b | balrog | int omap_3_1 = !ch->omap_3_1_compatible_disable;
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147 | b4e3104b | balrog | |
148 | b4e3104b | balrog | /*
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149 | b4e3104b | balrog | * TODO: verify address ranges and alignment
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150 | b4e3104b | balrog | * TODO: port endianness
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151 | b4e3104b | balrog | */
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152 | b4e3104b | balrog | |
153 | b4e3104b | balrog | a->src = ch->addr[0];
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154 | b4e3104b | balrog | a->dest = ch->addr[1];
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155 | b4e3104b | balrog | a->frames = ch->frames; |
156 | b4e3104b | balrog | a->elements = ch->elements; |
157 | 827df9f3 | balrog | a->pck_elements = ch->frame_index[!ch->src_sync]; |
158 | b4e3104b | balrog | a->frame = 0;
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159 | b4e3104b | balrog | a->element = 0;
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160 | 827df9f3 | balrog | a->pck_element = 0;
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161 | b4e3104b | balrog | |
162 | b4e3104b | balrog | if (unlikely(!ch->elements || !ch->frames)) {
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163 | b4e3104b | balrog | printf("%s: bad DMA request\n", __FUNCTION__);
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164 | b4e3104b | balrog | return;
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165 | b4e3104b | balrog | } |
166 | b4e3104b | balrog | |
167 | b4e3104b | balrog | for (i = 0; i < 2; i ++) |
168 | b4e3104b | balrog | switch (ch->mode[i]) {
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169 | b4e3104b | balrog | case constant:
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170 | b4e3104b | balrog | a->elem_delta[i] = 0;
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171 | b4e3104b | balrog | a->frame_delta[i] = 0;
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172 | b4e3104b | balrog | break;
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173 | b4e3104b | balrog | case post_incremented:
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174 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type; |
175 | b4e3104b | balrog | a->frame_delta[i] = 0;
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176 | b4e3104b | balrog | break;
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177 | b4e3104b | balrog | case single_index:
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178 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type + |
179 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i] - 1; |
180 | b4e3104b | balrog | a->frame_delta[i] = 0;
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181 | b4e3104b | balrog | break;
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182 | b4e3104b | balrog | case double_index:
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183 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type + |
184 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i] - 1; |
185 | b4e3104b | balrog | a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
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186 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i];
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187 | b4e3104b | balrog | break;
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188 | b4e3104b | balrog | default:
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189 | b4e3104b | balrog | break;
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190 | b4e3104b | balrog | } |
191 | afbb5194 | balrog | |
192 | afbb5194 | balrog | normal = !ch->transparent_copy && !ch->constant_fill && |
193 | afbb5194 | balrog | /* FIFO is big-endian so either (ch->endian[n] == 1) OR
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194 | afbb5194 | balrog | * (ch->endian_lock[n] == 1) mean no endianism conversion. */
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195 | afbb5194 | balrog | (ch->endian[0] | ch->endian_lock[0]) == |
196 | afbb5194 | balrog | (ch->endian[1] | ch->endian_lock[1]); |
197 | afbb5194 | balrog | for (i = 0; i < 2; i ++) { |
198 | afbb5194 | balrog | /* TODO: for a->frame_delta[i] > 0 still use the fast path, just
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199 | afbb5194 | balrog | * limit min_elems in omap_dma_transfer_setup to the nearest frame
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200 | afbb5194 | balrog | * end. */
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201 | afbb5194 | balrog | if (!a->elem_delta[i] && normal &&
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202 | afbb5194 | balrog | (a->frames == 1 || !a->frame_delta[i]))
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203 | afbb5194 | balrog | ch->dma->type[i] = soc_dma_access_const; |
204 | afbb5194 | balrog | else if (a->elem_delta[i] == ch->data_type && normal && |
205 | afbb5194 | balrog | (a->frames == 1 || !a->frame_delta[i]))
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206 | afbb5194 | balrog | ch->dma->type[i] = soc_dma_access_linear; |
207 | afbb5194 | balrog | else
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208 | afbb5194 | balrog | ch->dma->type[i] = soc_dma_access_other; |
209 | afbb5194 | balrog | |
210 | afbb5194 | balrog | ch->dma->vaddr[i] = ch->addr[i]; |
211 | afbb5194 | balrog | } |
212 | afbb5194 | balrog | soc_dma_ch_update(ch->dma); |
213 | b4e3104b | balrog | } |
214 | b4e3104b | balrog | |
215 | b4e3104b | balrog | static void omap_dma_activate_channel(struct omap_dma_s *s, |
216 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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217 | b4e3104b | balrog | { |
218 | b4e3104b | balrog | if (!ch->active) {
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219 | afbb5194 | balrog | if (ch->set_update) {
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220 | afbb5194 | balrog | /* It's not clear when the active set is supposed to be
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221 | afbb5194 | balrog | * loaded from registers. We're already loading it when the
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222 | afbb5194 | balrog | * channel is enabled, and for some guests this is not enough
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223 | afbb5194 | balrog | * but that may be also because of a race condition (no
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224 | afbb5194 | balrog | * delays in qemu) in the guest code, which we're just
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225 | afbb5194 | balrog | * working around here. */
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226 | afbb5194 | balrog | omap_dma_channel_load(ch); |
227 | afbb5194 | balrog | ch->set_update = 0;
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228 | afbb5194 | balrog | } |
229 | afbb5194 | balrog | |
230 | b4e3104b | balrog | ch->active = 1;
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231 | afbb5194 | balrog | soc_dma_set_request(ch->dma, 1);
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232 | b4e3104b | balrog | if (ch->sync)
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233 | b4e3104b | balrog | ch->status |= SYNC; |
234 | b4e3104b | balrog | } |
235 | b4e3104b | balrog | } |
236 | b4e3104b | balrog | |
237 | b4e3104b | balrog | static void omap_dma_deactivate_channel(struct omap_dma_s *s, |
238 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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239 | b4e3104b | balrog | { |
240 | b4e3104b | balrog | /* Update cpc */
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241 | b4e3104b | balrog | ch->cpc = ch->active_set.dest & 0xffff;
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242 | b4e3104b | balrog | |
243 | 827df9f3 | balrog | if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
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244 | b4e3104b | balrog | /* Don't deactivate the channel */
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245 | b4e3104b | balrog | ch->pending_request = 0;
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246 | 827df9f3 | balrog | return;
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247 | b4e3104b | balrog | } |
248 | b4e3104b | balrog | |
249 | b4e3104b | balrog | /* Don't deactive the channel if it is synchronized and the DMA request is
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250 | b4e3104b | balrog | active */
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251 | afbb5194 | balrog | if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync))) |
252 | b4e3104b | balrog | return;
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253 | b4e3104b | balrog | |
254 | b4e3104b | balrog | if (ch->active) {
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255 | b4e3104b | balrog | ch->active = 0;
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256 | b4e3104b | balrog | ch->status &= ~SYNC; |
257 | afbb5194 | balrog | soc_dma_set_request(ch->dma, 0);
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258 | b4e3104b | balrog | } |
259 | b4e3104b | balrog | } |
260 | b4e3104b | balrog | |
261 | b4e3104b | balrog | static void omap_dma_enable_channel(struct omap_dma_s *s, |
262 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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263 | b4e3104b | balrog | { |
264 | b4e3104b | balrog | if (!ch->enable) {
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265 | b4e3104b | balrog | ch->enable = 1;
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266 | b4e3104b | balrog | ch->waiting_end_prog = 0;
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267 | afbb5194 | balrog | omap_dma_channel_load(ch); |
268 | 827df9f3 | balrog | /* TODO: theoretically if ch->sync && ch->prefetch &&
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269 | afbb5194 | balrog | * !s->dma->drqbmp[ch->sync], we should also activate and fetch
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270 | afbb5194 | balrog | * from source and then stall until signalled. */
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271 | afbb5194 | balrog | if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync))) |
272 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
273 | b4e3104b | balrog | } |
274 | b4e3104b | balrog | } |
275 | b4e3104b | balrog | |
276 | b4e3104b | balrog | static void omap_dma_disable_channel(struct omap_dma_s *s, |
277 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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278 | b4e3104b | balrog | { |
279 | b4e3104b | balrog | if (ch->enable) {
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280 | b4e3104b | balrog | ch->enable = 0;
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281 | b4e3104b | balrog | /* Discard any pending request */
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282 | b4e3104b | balrog | ch->pending_request = 0;
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283 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
284 | b4e3104b | balrog | } |
285 | b4e3104b | balrog | } |
286 | b4e3104b | balrog | |
287 | b4e3104b | balrog | static void omap_dma_channel_end_prog(struct omap_dma_s *s, |
288 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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289 | b4e3104b | balrog | { |
290 | b4e3104b | balrog | if (ch->waiting_end_prog) {
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291 | b4e3104b | balrog | ch->waiting_end_prog = 0;
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292 | b4e3104b | balrog | if (!ch->sync || ch->pending_request) {
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293 | b4e3104b | balrog | ch->pending_request = 0;
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294 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
295 | b4e3104b | balrog | } |
296 | b4e3104b | balrog | } |
297 | b4e3104b | balrog | } |
298 | b4e3104b | balrog | |
299 | 827df9f3 | balrog | static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s) |
300 | 827df9f3 | balrog | { |
301 | 827df9f3 | balrog | struct omap_dma_channel_s *ch = s->ch;
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302 | 827df9f3 | balrog | |
303 | 827df9f3 | balrog | /* First three interrupts are shared between two channels each. */
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304 | 827df9f3 | balrog | if (ch[0].status | ch[6].status) |
305 | 827df9f3 | balrog | qemu_irq_raise(ch[0].irq);
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306 | 827df9f3 | balrog | if (ch[1].status | ch[7].status) |
307 | 827df9f3 | balrog | qemu_irq_raise(ch[1].irq);
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308 | 827df9f3 | balrog | if (ch[2].status | ch[8].status) |
309 | 827df9f3 | balrog | qemu_irq_raise(ch[2].irq);
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310 | 827df9f3 | balrog | if (ch[3].status) |
311 | 827df9f3 | balrog | qemu_irq_raise(ch[3].irq);
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312 | 827df9f3 | balrog | if (ch[4].status) |
313 | 827df9f3 | balrog | qemu_irq_raise(ch[4].irq);
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314 | 827df9f3 | balrog | if (ch[5].status) |
315 | 827df9f3 | balrog | qemu_irq_raise(ch[5].irq);
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316 | 827df9f3 | balrog | } |
317 | 827df9f3 | balrog | |
318 | 827df9f3 | balrog | static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s) |
319 | 827df9f3 | balrog | { |
320 | 827df9f3 | balrog | struct omap_dma_channel_s *ch = s->ch;
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321 | 827df9f3 | balrog | int i;
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322 | 827df9f3 | balrog | |
323 | 827df9f3 | balrog | for (i = s->chans; i; ch ++, i --)
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324 | 827df9f3 | balrog | if (ch->status)
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325 | 827df9f3 | balrog | qemu_irq_raise(ch->irq); |
326 | 827df9f3 | balrog | } |
327 | 827df9f3 | balrog | |
328 | b4e3104b | balrog | static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) |
329 | b4e3104b | balrog | { |
330 | b4e3104b | balrog | s->omap_3_1_mapping_disabled = 0;
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331 | b4e3104b | balrog | s->chans = 9;
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332 | 827df9f3 | balrog | s->intr_update = omap_dma_interrupts_3_1_update; |
333 | b4e3104b | balrog | } |
334 | b4e3104b | balrog | |
335 | b4e3104b | balrog | static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) |
336 | b4e3104b | balrog | { |
337 | b4e3104b | balrog | s->omap_3_1_mapping_disabled = 1;
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338 | b4e3104b | balrog | s->chans = 16;
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339 | 827df9f3 | balrog | s->intr_update = omap_dma_interrupts_3_2_update; |
340 | b4e3104b | balrog | } |
341 | b4e3104b | balrog | |
342 | b4e3104b | balrog | static void omap_dma_process_request(struct omap_dma_s *s, int request) |
343 | b4e3104b | balrog | { |
344 | b4e3104b | balrog | int channel;
|
345 | b4e3104b | balrog | int drop_event = 0; |
346 | b4e3104b | balrog | struct omap_dma_channel_s *ch = s->ch;
|
347 | b4e3104b | balrog | |
348 | b4e3104b | balrog | for (channel = 0; channel < s->chans; channel ++, ch ++) { |
349 | b4e3104b | balrog | if (ch->enable && ch->sync == request) {
|
350 | b4e3104b | balrog | if (!ch->active)
|
351 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
352 | b4e3104b | balrog | else if (!ch->pending_request) |
353 | b4e3104b | balrog | ch->pending_request = 1;
|
354 | b4e3104b | balrog | else {
|
355 | b4e3104b | balrog | /* Request collision */
|
356 | b4e3104b | balrog | /* Second request received while processing other request */
|
357 | b4e3104b | balrog | ch->status |= EVENT_DROP_INTR; |
358 | b4e3104b | balrog | drop_event = 1;
|
359 | b4e3104b | balrog | } |
360 | b4e3104b | balrog | } |
361 | b4e3104b | balrog | } |
362 | b4e3104b | balrog | |
363 | b4e3104b | balrog | if (drop_event)
|
364 | b4e3104b | balrog | omap_dma_interrupts_update(s); |
365 | b4e3104b | balrog | } |
366 | b4e3104b | balrog | |
367 | afbb5194 | balrog | static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma) |
368 | b4e3104b | balrog | { |
369 | b4e3104b | balrog | uint8_t value[4];
|
370 | afbb5194 | balrog | struct omap_dma_channel_s *ch = dma->opaque;
|
371 | afbb5194 | balrog | struct omap_dma_reg_set_s *a = &ch->active_set;
|
372 | afbb5194 | balrog | int bytes = dma->bytes;
|
373 | afbb5194 | balrog | #ifdef MULTI_REQ
|
374 | afbb5194 | balrog | uint16_t status = ch->status; |
375 | afbb5194 | balrog | #endif
|
376 | b4e3104b | balrog | |
377 | afbb5194 | balrog | do {
|
378 | afbb5194 | balrog | /* Transfer a single element */
|
379 | afbb5194 | balrog | /* FIXME: check the endianness */
|
380 | afbb5194 | balrog | if (!ch->constant_fill)
|
381 | afbb5194 | balrog | cpu_physical_memory_read(a->src, value, ch->data_type); |
382 | afbb5194 | balrog | else
|
383 | afbb5194 | balrog | *(uint32_t *) value = ch->color; |
384 | afbb5194 | balrog | |
385 | afbb5194 | balrog | if (!ch->transparent_copy || *(uint32_t *) value != ch->color)
|
386 | afbb5194 | balrog | cpu_physical_memory_write(a->dest, value, ch->data_type); |
387 | afbb5194 | balrog | |
388 | afbb5194 | balrog | a->src += a->elem_delta[0];
|
389 | afbb5194 | balrog | a->dest += a->elem_delta[1];
|
390 | afbb5194 | balrog | a->element ++; |
391 | afbb5194 | balrog | |
392 | afbb5194 | balrog | #ifndef MULTI_REQ
|
393 | afbb5194 | balrog | if (a->element == a->elements) {
|
394 | afbb5194 | balrog | /* End of Frame */
|
395 | afbb5194 | balrog | a->element = 0;
|
396 | afbb5194 | balrog | a->src += a->frame_delta[0];
|
397 | afbb5194 | balrog | a->dest += a->frame_delta[1];
|
398 | afbb5194 | balrog | a->frame ++; |
399 | afbb5194 | balrog | |
400 | afbb5194 | balrog | /* If the channel is async, update cpc */
|
401 | afbb5194 | balrog | if (!ch->sync)
|
402 | afbb5194 | balrog | ch->cpc = a->dest & 0xffff;
|
403 | afbb5194 | balrog | } |
404 | afbb5194 | balrog | } while ((bytes -= ch->data_type));
|
405 | afbb5194 | balrog | #else
|
406 | afbb5194 | balrog | /* If the channel is element synchronized, deactivate it */
|
407 | afbb5194 | balrog | if (ch->sync && !ch->fs && !ch->bs)
|
408 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
409 | afbb5194 | balrog | |
410 | afbb5194 | balrog | /* If it is the last frame, set the LAST_FRAME interrupt */
|
411 | afbb5194 | balrog | if (a->element == 1 && a->frame == a->frames - 1) |
412 | afbb5194 | balrog | if (ch->interrupts & LAST_FRAME_INTR)
|
413 | afbb5194 | balrog | ch->status |= LAST_FRAME_INTR; |
414 | afbb5194 | balrog | |
415 | afbb5194 | balrog | /* If the half of the frame was reached, set the HALF_FRAME
|
416 | afbb5194 | balrog | interrupt */
|
417 | afbb5194 | balrog | if (a->element == (a->elements >> 1)) |
418 | afbb5194 | balrog | if (ch->interrupts & HALF_FRAME_INTR)
|
419 | afbb5194 | balrog | ch->status |= HALF_FRAME_INTR; |
420 | afbb5194 | balrog | |
421 | afbb5194 | balrog | if (ch->fs && ch->bs) {
|
422 | afbb5194 | balrog | a->pck_element ++; |
423 | afbb5194 | balrog | /* Check if a full packet has beed transferred. */
|
424 | afbb5194 | balrog | if (a->pck_element == a->pck_elements) {
|
425 | afbb5194 | balrog | a->pck_element = 0;
|
426 | afbb5194 | balrog | |
427 | afbb5194 | balrog | /* Set the END_PKT interrupt */
|
428 | afbb5194 | balrog | if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)
|
429 | afbb5194 | balrog | ch->status |= END_PKT_INTR; |
430 | afbb5194 | balrog | |
431 | afbb5194 | balrog | /* If the channel is packet-synchronized, deactivate it */
|
432 | afbb5194 | balrog | if (ch->sync)
|
433 | afbb5194 | balrog | omap_dma_deactivate_channel(s, ch); |
434 | afbb5194 | balrog | } |
435 | b4e3104b | balrog | } |
436 | b4e3104b | balrog | |
437 | afbb5194 | balrog | if (a->element == a->elements) {
|
438 | afbb5194 | balrog | /* End of Frame */
|
439 | afbb5194 | balrog | a->element = 0;
|
440 | afbb5194 | balrog | a->src += a->frame_delta[0];
|
441 | afbb5194 | balrog | a->dest += a->frame_delta[1];
|
442 | afbb5194 | balrog | a->frame ++; |
443 | afbb5194 | balrog | |
444 | afbb5194 | balrog | /* If the channel is frame synchronized, deactivate it */
|
445 | afbb5194 | balrog | if (ch->sync && ch->fs && !ch->bs)
|
446 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
447 | b4e3104b | balrog | |
448 | afbb5194 | balrog | /* If the channel is async, update cpc */
|
449 | afbb5194 | balrog | if (!ch->sync)
|
450 | afbb5194 | balrog | ch->cpc = a->dest & 0xffff;
|
451 | afbb5194 | balrog | |
452 | afbb5194 | balrog | /* Set the END_FRAME interrupt */
|
453 | afbb5194 | balrog | if (ch->interrupts & END_FRAME_INTR)
|
454 | afbb5194 | balrog | ch->status |= END_FRAME_INTR; |
455 | afbb5194 | balrog | |
456 | afbb5194 | balrog | if (a->frame == a->frames) {
|
457 | afbb5194 | balrog | /* End of Block */
|
458 | afbb5194 | balrog | /* Disable the channel */
|
459 | afbb5194 | balrog | |
460 | afbb5194 | balrog | if (ch->omap_3_1_compatible_disable) {
|
461 | afbb5194 | balrog | omap_dma_disable_channel(s, ch); |
462 | afbb5194 | balrog | if (ch->link_enabled)
|
463 | afbb5194 | balrog | omap_dma_enable_channel(s, |
464 | afbb5194 | balrog | &s->ch[ch->link_next_ch]); |
465 | afbb5194 | balrog | } else {
|
466 | afbb5194 | balrog | if (!ch->auto_init)
|
467 | afbb5194 | balrog | omap_dma_disable_channel(s, ch); |
468 | afbb5194 | balrog | else if (ch->repeat || ch->end_prog) |
469 | afbb5194 | balrog | omap_dma_channel_load(ch); |
470 | afbb5194 | balrog | else {
|
471 | afbb5194 | balrog | ch->waiting_end_prog = 1;
|
472 | 827df9f3 | balrog | omap_dma_deactivate_channel(s, ch); |
473 | afbb5194 | balrog | } |
474 | 827df9f3 | balrog | } |
475 | afbb5194 | balrog | |
476 | afbb5194 | balrog | if (ch->interrupts & END_BLOCK_INTR)
|
477 | afbb5194 | balrog | ch->status |= END_BLOCK_INTR; |
478 | 827df9f3 | balrog | } |
479 | afbb5194 | balrog | } |
480 | afbb5194 | balrog | } while (status == ch->status && ch->active);
|
481 | 827df9f3 | balrog | |
482 | afbb5194 | balrog | omap_dma_interrupts_update(s); |
483 | afbb5194 | balrog | #endif
|
484 | afbb5194 | balrog | } |
485 | b4e3104b | balrog | |
486 | afbb5194 | balrog | enum {
|
487 | afbb5194 | balrog | omap_dma_intr_element_sync, |
488 | afbb5194 | balrog | omap_dma_intr_last_frame, |
489 | afbb5194 | balrog | omap_dma_intr_half_frame, |
490 | afbb5194 | balrog | omap_dma_intr_frame, |
491 | afbb5194 | balrog | omap_dma_intr_frame_sync, |
492 | afbb5194 | balrog | omap_dma_intr_packet, |
493 | afbb5194 | balrog | omap_dma_intr_packet_sync, |
494 | afbb5194 | balrog | omap_dma_intr_block, |
495 | afbb5194 | balrog | __omap_dma_intr_last, |
496 | afbb5194 | balrog | }; |
497 | b4e3104b | balrog | |
498 | afbb5194 | balrog | static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma) |
499 | afbb5194 | balrog | { |
500 | afbb5194 | balrog | struct omap_dma_port_if_s *src_p, *dest_p;
|
501 | afbb5194 | balrog | struct omap_dma_reg_set_s *a;
|
502 | afbb5194 | balrog | struct omap_dma_channel_s *ch = dma->opaque;
|
503 | afbb5194 | balrog | struct omap_dma_s *s = dma->dma->opaque;
|
504 | afbb5194 | balrog | int frames, min_elems, elements[__omap_dma_intr_last];
|
505 | b4e3104b | balrog | |
506 | afbb5194 | balrog | a = &ch->active_set; |
507 | b4e3104b | balrog | |
508 | afbb5194 | balrog | src_p = &s->mpu->port[ch->port[0]];
|
509 | afbb5194 | balrog | dest_p = &s->mpu->port[ch->port[1]];
|
510 | afbb5194 | balrog | if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
|
511 | afbb5194 | balrog | (!dest_p->addr_valid(s->mpu, a->dest))) { |
512 | afbb5194 | balrog | #if 0
|
513 | afbb5194 | balrog | /* Bus time-out */
|
514 | afbb5194 | balrog | if (ch->interrupts & TIMEOUT_INTR)
|
515 | afbb5194 | balrog | ch->status |= TIMEOUT_INTR;
|
516 | afbb5194 | balrog | omap_dma_deactivate_channel(s, ch);
|
517 | afbb5194 | balrog | continue;
|
518 | afbb5194 | balrog | #endif
|
519 | afbb5194 | balrog | printf("%s: Bus time-out in DMA%i operation\n",
|
520 | afbb5194 | balrog | __FUNCTION__, dma->num); |
521 | afbb5194 | balrog | } |
522 | b4e3104b | balrog | |
523 | afbb5194 | balrog | min_elems = INT_MAX; |
524 | afbb5194 | balrog | |
525 | afbb5194 | balrog | /* Check all the conditions that terminate the transfer starting
|
526 | afbb5194 | balrog | * with those that can occur the soonest. */
|
527 | afbb5194 | balrog | #define INTR_CHECK(cond, id, nelements) \
|
528 | afbb5194 | balrog | if (cond) { \
|
529 | afbb5194 | balrog | elements[id] = nelements; \ |
530 | afbb5194 | balrog | if (elements[id] < min_elems) \
|
531 | afbb5194 | balrog | min_elems = elements[id]; \ |
532 | afbb5194 | balrog | } else \
|
533 | afbb5194 | balrog | elements[id] = INT_MAX; |
534 | afbb5194 | balrog | |
535 | afbb5194 | balrog | /* Elements */
|
536 | afbb5194 | balrog | INTR_CHECK( |
537 | afbb5194 | balrog | ch->sync && !ch->fs && !ch->bs, |
538 | afbb5194 | balrog | omap_dma_intr_element_sync, |
539 | afbb5194 | balrog | 1)
|
540 | afbb5194 | balrog | |
541 | afbb5194 | balrog | /* Frames */
|
542 | afbb5194 | balrog | /* TODO: for transfers where entire frames can be read and written
|
543 | afbb5194 | balrog | * using memcpy() but a->frame_delta is non-zero, try to still do
|
544 | afbb5194 | balrog | * transfers using soc_dma but limit min_elems to a->elements - ...
|
545 | afbb5194 | balrog | * See also the TODO in omap_dma_channel_load. */
|
546 | afbb5194 | balrog | INTR_CHECK( |
547 | afbb5194 | balrog | (ch->interrupts & LAST_FRAME_INTR) && |
548 | afbb5194 | balrog | ((a->frame < a->frames - 1) || !a->element),
|
549 | afbb5194 | balrog | omap_dma_intr_last_frame, |
550 | afbb5194 | balrog | (a->frames - a->frame - 2) * a->elements +
|
551 | afbb5194 | balrog | (a->elements - a->element + 1))
|
552 | afbb5194 | balrog | INTR_CHECK( |
553 | afbb5194 | balrog | ch->interrupts & HALF_FRAME_INTR, |
554 | afbb5194 | balrog | omap_dma_intr_half_frame, |
555 | afbb5194 | balrog | (a->elements >> 1) +
|
556 | afbb5194 | balrog | (a->element >= (a->elements >> 1) ? a->elements : 0) - |
557 | afbb5194 | balrog | a->element) |
558 | afbb5194 | balrog | INTR_CHECK( |
559 | afbb5194 | balrog | ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR), |
560 | afbb5194 | balrog | omap_dma_intr_frame, |
561 | afbb5194 | balrog | a->elements - a->element) |
562 | afbb5194 | balrog | INTR_CHECK( |
563 | afbb5194 | balrog | ch->sync && ch->fs && !ch->bs, |
564 | afbb5194 | balrog | omap_dma_intr_frame_sync, |
565 | afbb5194 | balrog | a->elements - a->element) |
566 | afbb5194 | balrog | |
567 | afbb5194 | balrog | /* Packets */
|
568 | afbb5194 | balrog | INTR_CHECK( |
569 | afbb5194 | balrog | ch->fs && ch->bs && |
570 | afbb5194 | balrog | (ch->interrupts & END_PKT_INTR) && !ch->src_sync, |
571 | afbb5194 | balrog | omap_dma_intr_packet, |
572 | afbb5194 | balrog | a->pck_elements - a->pck_element) |
573 | afbb5194 | balrog | INTR_CHECK( |
574 | afbb5194 | balrog | ch->fs && ch->bs && ch->sync, |
575 | afbb5194 | balrog | omap_dma_intr_packet_sync, |
576 | afbb5194 | balrog | a->pck_elements - a->pck_element) |
577 | afbb5194 | balrog | |
578 | afbb5194 | balrog | /* Blocks */
|
579 | afbb5194 | balrog | INTR_CHECK( |
580 | afbb5194 | balrog | 1,
|
581 | afbb5194 | balrog | omap_dma_intr_block, |
582 | afbb5194 | balrog | (a->frames - a->frame - 1) * a->elements +
|
583 | afbb5194 | balrog | (a->elements - a->element)) |
584 | afbb5194 | balrog | |
585 | afbb5194 | balrog | dma->bytes = min_elems * ch->data_type; |
586 | afbb5194 | balrog | |
587 | afbb5194 | balrog | /* Set appropriate interrupts and/or deactivate channels */
|
588 | afbb5194 | balrog | |
589 | afbb5194 | balrog | #ifdef MULTI_REQ
|
590 | afbb5194 | balrog | /* TODO: should all of this only be done if dma->update, and otherwise
|
591 | afbb5194 | balrog | * inside omap_dma_transfer_generic below - check what's faster. */
|
592 | afbb5194 | balrog | if (dma->update) {
|
593 | afbb5194 | balrog | #endif
|
594 | b4e3104b | balrog | |
595 | afbb5194 | balrog | /* If the channel is element synchronized, deactivate it */
|
596 | afbb5194 | balrog | if (min_elems == elements[omap_dma_intr_element_sync])
|
597 | afbb5194 | balrog | omap_dma_deactivate_channel(s, ch); |
598 | afbb5194 | balrog | |
599 | afbb5194 | balrog | /* If it is the last frame, set the LAST_FRAME interrupt */
|
600 | afbb5194 | balrog | if (min_elems == elements[omap_dma_intr_last_frame])
|
601 | afbb5194 | balrog | ch->status |= LAST_FRAME_INTR; |
602 | afbb5194 | balrog | |
603 | afbb5194 | balrog | /* If exactly half of the frame was reached, set the HALF_FRAME
|
604 | afbb5194 | balrog | interrupt */
|
605 | afbb5194 | balrog | if (min_elems == elements[omap_dma_intr_half_frame])
|
606 | afbb5194 | balrog | ch->status |= HALF_FRAME_INTR; |
607 | afbb5194 | balrog | |
608 | afbb5194 | balrog | /* If a full packet has been transferred, set the END_PKT interrupt */
|
609 | afbb5194 | balrog | if (min_elems == elements[omap_dma_intr_packet])
|
610 | afbb5194 | balrog | ch->status |= END_PKT_INTR; |
611 | afbb5194 | balrog | |
612 | afbb5194 | balrog | /* If the channel is packet-synchronized, deactivate it */
|
613 | afbb5194 | balrog | if (min_elems == elements[omap_dma_intr_packet_sync])
|
614 | afbb5194 | balrog | omap_dma_deactivate_channel(s, ch); |
615 | afbb5194 | balrog | |
616 | afbb5194 | balrog | /* If the channel is frame synchronized, deactivate it */
|
617 | afbb5194 | balrog | if (min_elems == elements[omap_dma_intr_frame_sync])
|
618 | afbb5194 | balrog | omap_dma_deactivate_channel(s, ch); |
619 | afbb5194 | balrog | |
620 | afbb5194 | balrog | /* Set the END_FRAME interrupt */
|
621 | afbb5194 | balrog | if (min_elems == elements[omap_dma_intr_frame])
|
622 | afbb5194 | balrog | ch->status |= END_FRAME_INTR; |
623 | afbb5194 | balrog | |
624 | afbb5194 | balrog | if (min_elems == elements[omap_dma_intr_block]) {
|
625 | afbb5194 | balrog | /* End of Block */
|
626 | afbb5194 | balrog | /* Disable the channel */
|
627 | afbb5194 | balrog | |
628 | afbb5194 | balrog | if (ch->omap_3_1_compatible_disable) {
|
629 | afbb5194 | balrog | omap_dma_disable_channel(s, ch); |
630 | afbb5194 | balrog | if (ch->link_enabled)
|
631 | afbb5194 | balrog | omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]); |
632 | afbb5194 | balrog | } else {
|
633 | afbb5194 | balrog | if (!ch->auto_init)
|
634 | afbb5194 | balrog | omap_dma_disable_channel(s, ch); |
635 | afbb5194 | balrog | else if (ch->repeat || ch->end_prog) |
636 | afbb5194 | balrog | omap_dma_channel_load(ch); |
637 | afbb5194 | balrog | else {
|
638 | afbb5194 | balrog | ch->waiting_end_prog = 1;
|
639 | afbb5194 | balrog | omap_dma_deactivate_channel(s, ch); |
640 | b4e3104b | balrog | } |
641 | b4e3104b | balrog | } |
642 | afbb5194 | balrog | |
643 | afbb5194 | balrog | if (ch->interrupts & END_BLOCK_INTR)
|
644 | afbb5194 | balrog | ch->status |= END_BLOCK_INTR; |
645 | afbb5194 | balrog | } |
646 | afbb5194 | balrog | |
647 | afbb5194 | balrog | /* Update packet number */
|
648 | afbb5194 | balrog | if (ch->fs && ch->bs) {
|
649 | afbb5194 | balrog | a->pck_element += min_elems; |
650 | afbb5194 | balrog | a->pck_element %= a->pck_elements; |
651 | afbb5194 | balrog | } |
652 | afbb5194 | balrog | |
653 | afbb5194 | balrog | /* TODO: check if we really need to update anything here or perhaps we
|
654 | afbb5194 | balrog | * can skip part of this. */
|
655 | afbb5194 | balrog | #ifndef MULTI_REQ
|
656 | afbb5194 | balrog | if (dma->update) {
|
657 | afbb5194 | balrog | #endif
|
658 | afbb5194 | balrog | a->element += min_elems; |
659 | afbb5194 | balrog | |
660 | afbb5194 | balrog | frames = a->element / a->elements; |
661 | afbb5194 | balrog | a->element = a->element % a->elements; |
662 | afbb5194 | balrog | a->frame += frames; |
663 | afbb5194 | balrog | a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0]; |
664 | afbb5194 | balrog | a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1]; |
665 | afbb5194 | balrog | |
666 | afbb5194 | balrog | /* If the channel is async, update cpc */
|
667 | afbb5194 | balrog | if (!ch->sync && frames)
|
668 | afbb5194 | balrog | ch->cpc = a->dest & 0xffff;
|
669 | d4066479 | balrog | |
670 | d4066479 | balrog | /* TODO: if the destination port is IMIF or EMIFF, set the dirty
|
671 | d4066479 | balrog | * bits on it. */
|
672 | b4e3104b | balrog | } |
673 | b4e3104b | balrog | |
674 | b4e3104b | balrog | omap_dma_interrupts_update(s); |
675 | b4e3104b | balrog | } |
676 | b4e3104b | balrog | |
677 | afbb5194 | balrog | void omap_dma_reset(struct soc_dma_s *dma) |
678 | b4e3104b | balrog | { |
679 | b4e3104b | balrog | int i;
|
680 | afbb5194 | balrog | struct omap_dma_s *s = dma->opaque;
|
681 | b4e3104b | balrog | |
682 | afbb5194 | balrog | soc_dma_reset(s->dma); |
683 | 827df9f3 | balrog | if (s->model < omap_dma_4)
|
684 | 827df9f3 | balrog | s->gcr = 0x0004;
|
685 | 827df9f3 | balrog | else
|
686 | 827df9f3 | balrog | s->gcr = 0x00010010;
|
687 | 827df9f3 | balrog | s->ocp = 0x00000000;
|
688 | 827df9f3 | balrog | memset(&s->irqstat, 0, sizeof(s->irqstat)); |
689 | 827df9f3 | balrog | memset(&s->irqen, 0, sizeof(s->irqen)); |
690 | b4e3104b | balrog | s->lcd_ch.src = emiff; |
691 | b4e3104b | balrog | s->lcd_ch.condition = 0;
|
692 | b4e3104b | balrog | s->lcd_ch.interrupts = 0;
|
693 | b4e3104b | balrog | s->lcd_ch.dual = 0;
|
694 | 827df9f3 | balrog | if (s->model < omap_dma_4)
|
695 | 827df9f3 | balrog | omap_dma_enable_3_1_mapping(s); |
696 | b4e3104b | balrog | for (i = 0; i < s->chans; i ++) { |
697 | 827df9f3 | balrog | s->ch[i].suspend = 0;
|
698 | 827df9f3 | balrog | s->ch[i].prefetch = 0;
|
699 | 827df9f3 | balrog | s->ch[i].buf_disable = 0;
|
700 | 827df9f3 | balrog | s->ch[i].src_sync = 0;
|
701 | b4e3104b | balrog | memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); |
702 | b4e3104b | balrog | memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); |
703 | b4e3104b | balrog | memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); |
704 | b4e3104b | balrog | memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); |
705 | b4e3104b | balrog | memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); |
706 | 827df9f3 | balrog | memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian)); |
707 | 827df9f3 | balrog | memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock)); |
708 | 827df9f3 | balrog | memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate)); |
709 | 827df9f3 | balrog | s->ch[i].write_mode = 0;
|
710 | 827df9f3 | balrog | s->ch[i].data_type = 0;
|
711 | 827df9f3 | balrog | s->ch[i].transparent_copy = 0;
|
712 | 827df9f3 | balrog | s->ch[i].constant_fill = 0;
|
713 | 827df9f3 | balrog | s->ch[i].color = 0x00000000;
|
714 | 827df9f3 | balrog | s->ch[i].end_prog = 0;
|
715 | 827df9f3 | balrog | s->ch[i].repeat = 0;
|
716 | 827df9f3 | balrog | s->ch[i].auto_init = 0;
|
717 | 827df9f3 | balrog | s->ch[i].link_enabled = 0;
|
718 | 827df9f3 | balrog | if (s->model < omap_dma_4)
|
719 | 827df9f3 | balrog | s->ch[i].interrupts = 0x0003;
|
720 | 827df9f3 | balrog | else
|
721 | 827df9f3 | balrog | s->ch[i].interrupts = 0x0000;
|
722 | 827df9f3 | balrog | s->ch[i].status = 0;
|
723 | 827df9f3 | balrog | s->ch[i].cstatus = 0;
|
724 | 827df9f3 | balrog | s->ch[i].active = 0;
|
725 | 827df9f3 | balrog | s->ch[i].enable = 0;
|
726 | 827df9f3 | balrog | s->ch[i].sync = 0;
|
727 | 827df9f3 | balrog | s->ch[i].pending_request = 0;
|
728 | 827df9f3 | balrog | s->ch[i].waiting_end_prog = 0;
|
729 | 827df9f3 | balrog | s->ch[i].cpc = 0x0000;
|
730 | 827df9f3 | balrog | s->ch[i].fs = 0;
|
731 | 827df9f3 | balrog | s->ch[i].bs = 0;
|
732 | 827df9f3 | balrog | s->ch[i].omap_3_1_compatible_disable = 0;
|
733 | b4e3104b | balrog | memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); |
734 | 827df9f3 | balrog | s->ch[i].priority = 0;
|
735 | 827df9f3 | balrog | s->ch[i].interleave_disabled = 0;
|
736 | 827df9f3 | balrog | s->ch[i].type = 0;
|
737 | b4e3104b | balrog | } |
738 | b4e3104b | balrog | } |
739 | b4e3104b | balrog | |
740 | b4e3104b | balrog | static int omap_dma_ch_reg_read(struct omap_dma_s *s, |
741 | b4e3104b | balrog | struct omap_dma_channel_s *ch, int reg, uint16_t *value) |
742 | b4e3104b | balrog | { |
743 | b4e3104b | balrog | switch (reg) {
|
744 | b4e3104b | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
745 | b4e3104b | balrog | *value = (ch->burst[1] << 14) | |
746 | b4e3104b | balrog | (ch->pack[1] << 13) | |
747 | b4e3104b | balrog | (ch->port[1] << 9) | |
748 | b4e3104b | balrog | (ch->burst[0] << 7) | |
749 | b4e3104b | balrog | (ch->pack[0] << 6) | |
750 | b4e3104b | balrog | (ch->port[0] << 2) | |
751 | b4e3104b | balrog | (ch->data_type >> 1);
|
752 | b4e3104b | balrog | break;
|
753 | b4e3104b | balrog | |
754 | b4e3104b | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
755 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1)
|
756 | b4e3104b | balrog | *value = 0 << 10; /* FIFO_FLUSH reads as 0 */ |
757 | b4e3104b | balrog | else
|
758 | b4e3104b | balrog | *value = ch->omap_3_1_compatible_disable << 10;
|
759 | b4e3104b | balrog | *value |= (ch->mode[1] << 14) | |
760 | b4e3104b | balrog | (ch->mode[0] << 12) | |
761 | b4e3104b | balrog | (ch->end_prog << 11) |
|
762 | b4e3104b | balrog | (ch->repeat << 9) |
|
763 | b4e3104b | balrog | (ch->auto_init << 8) |
|
764 | b4e3104b | balrog | (ch->enable << 7) |
|
765 | b4e3104b | balrog | (ch->priority << 6) |
|
766 | b4e3104b | balrog | (ch->fs << 5) | ch->sync;
|
767 | b4e3104b | balrog | break;
|
768 | b4e3104b | balrog | |
769 | b4e3104b | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
770 | b4e3104b | balrog | *value = ch->interrupts; |
771 | b4e3104b | balrog | break;
|
772 | b4e3104b | balrog | |
773 | b4e3104b | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
774 | b4e3104b | balrog | *value = ch->status; |
775 | b4e3104b | balrog | ch->status &= SYNC; |
776 | b4e3104b | balrog | if (!ch->omap_3_1_compatible_disable && ch->sibling) {
|
777 | b4e3104b | balrog | *value |= (ch->sibling->status & 0x3f) << 6; |
778 | b4e3104b | balrog | ch->sibling->status &= SYNC; |
779 | b4e3104b | balrog | } |
780 | b4e3104b | balrog | qemu_irq_lower(ch->irq); |
781 | b4e3104b | balrog | break;
|
782 | b4e3104b | balrog | |
783 | b4e3104b | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
784 | b4e3104b | balrog | *value = ch->addr[0] & 0x0000ffff; |
785 | b4e3104b | balrog | break;
|
786 | b4e3104b | balrog | |
787 | b4e3104b | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
788 | b4e3104b | balrog | *value = ch->addr[0] >> 16; |
789 | b4e3104b | balrog | break;
|
790 | b4e3104b | balrog | |
791 | b4e3104b | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
792 | b4e3104b | balrog | *value = ch->addr[1] & 0x0000ffff; |
793 | b4e3104b | balrog | break;
|
794 | b4e3104b | balrog | |
795 | b4e3104b | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
796 | b4e3104b | balrog | *value = ch->addr[1] >> 16; |
797 | b4e3104b | balrog | break;
|
798 | b4e3104b | balrog | |
799 | b4e3104b | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
800 | b4e3104b | balrog | *value = ch->elements; |
801 | b4e3104b | balrog | break;
|
802 | b4e3104b | balrog | |
803 | b4e3104b | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
804 | b4e3104b | balrog | *value = ch->frames; |
805 | b4e3104b | balrog | break;
|
806 | b4e3104b | balrog | |
807 | b4e3104b | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
808 | b4e3104b | balrog | *value = ch->frame_index[0];
|
809 | b4e3104b | balrog | break;
|
810 | b4e3104b | balrog | |
811 | b4e3104b | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
812 | b4e3104b | balrog | *value = ch->element_index[0];
|
813 | b4e3104b | balrog | break;
|
814 | b4e3104b | balrog | |
815 | b4e3104b | balrog | case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ |
816 | b4e3104b | balrog | if (ch->omap_3_1_compatible_disable)
|
817 | b4e3104b | balrog | *value = ch->active_set.src & 0xffff; /* CSAC */ |
818 | b4e3104b | balrog | else
|
819 | b4e3104b | balrog | *value = ch->cpc; |
820 | b4e3104b | balrog | break;
|
821 | b4e3104b | balrog | |
822 | b4e3104b | balrog | case 0x1a: /* DMA_CDAC */ |
823 | b4e3104b | balrog | *value = ch->active_set.dest & 0xffff; /* CDAC */ |
824 | b4e3104b | balrog | break;
|
825 | b4e3104b | balrog | |
826 | b4e3104b | balrog | case 0x1c: /* DMA_CDEI */ |
827 | b4e3104b | balrog | *value = ch->element_index[1];
|
828 | b4e3104b | balrog | break;
|
829 | b4e3104b | balrog | |
830 | b4e3104b | balrog | case 0x1e: /* DMA_CDFI */ |
831 | b4e3104b | balrog | *value = ch->frame_index[1];
|
832 | b4e3104b | balrog | break;
|
833 | b4e3104b | balrog | |
834 | b4e3104b | balrog | case 0x20: /* DMA_COLOR_L */ |
835 | b4e3104b | balrog | *value = ch->color & 0xffff;
|
836 | b4e3104b | balrog | break;
|
837 | b4e3104b | balrog | |
838 | b4e3104b | balrog | case 0x22: /* DMA_COLOR_U */ |
839 | b4e3104b | balrog | *value = ch->color >> 16;
|
840 | b4e3104b | balrog | break;
|
841 | b4e3104b | balrog | |
842 | b4e3104b | balrog | case 0x24: /* DMA_CCR2 */ |
843 | b4e3104b | balrog | *value = (ch->bs << 2) |
|
844 | b4e3104b | balrog | (ch->transparent_copy << 1) |
|
845 | b4e3104b | balrog | ch->constant_fill; |
846 | b4e3104b | balrog | break;
|
847 | b4e3104b | balrog | |
848 | b4e3104b | balrog | case 0x28: /* DMA_CLNK_CTRL */ |
849 | b4e3104b | balrog | *value = (ch->link_enabled << 15) |
|
850 | b4e3104b | balrog | (ch->link_next_ch & 0xf);
|
851 | b4e3104b | balrog | break;
|
852 | b4e3104b | balrog | |
853 | b4e3104b | balrog | case 0x2a: /* DMA_LCH_CTRL */ |
854 | b4e3104b | balrog | *value = (ch->interleave_disabled << 15) |
|
855 | b4e3104b | balrog | ch->type; |
856 | b4e3104b | balrog | break;
|
857 | b4e3104b | balrog | |
858 | b4e3104b | balrog | default:
|
859 | b4e3104b | balrog | return 1; |
860 | b4e3104b | balrog | } |
861 | b4e3104b | balrog | return 0; |
862 | b4e3104b | balrog | } |
863 | b4e3104b | balrog | |
864 | b4e3104b | balrog | static int omap_dma_ch_reg_write(struct omap_dma_s *s, |
865 | b4e3104b | balrog | struct omap_dma_channel_s *ch, int reg, uint16_t value) |
866 | b4e3104b | balrog | { |
867 | b4e3104b | balrog | switch (reg) {
|
868 | b4e3104b | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
869 | b4e3104b | balrog | ch->burst[1] = (value & 0xc000) >> 14; |
870 | b4e3104b | balrog | ch->pack[1] = (value & 0x2000) >> 13; |
871 | b4e3104b | balrog | ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); |
872 | b4e3104b | balrog | ch->burst[0] = (value & 0x0180) >> 7; |
873 | b4e3104b | balrog | ch->pack[0] = (value & 0x0040) >> 6; |
874 | b4e3104b | balrog | ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); |
875 | 827df9f3 | balrog | ch->data_type = 1 << (value & 3); |
876 | 827df9f3 | balrog | if (ch->port[0] >= __omap_dma_port_last) |
877 | b4e3104b | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
878 | b4e3104b | balrog | ch->port[0]);
|
879 | 827df9f3 | balrog | if (ch->port[1] >= __omap_dma_port_last) |
880 | b4e3104b | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
881 | b4e3104b | balrog | ch->port[1]);
|
882 | b4e3104b | balrog | if ((value & 3) == 3) |
883 | b4e3104b | balrog | printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
|
884 | b4e3104b | balrog | break;
|
885 | b4e3104b | balrog | |
886 | b4e3104b | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
887 | b4e3104b | balrog | ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
888 | b4e3104b | balrog | ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
889 | b4e3104b | balrog | ch->end_prog = (value & 0x0800) >> 11; |
890 | 827df9f3 | balrog | if (s->model >= omap_dma_3_2)
|
891 | b4e3104b | balrog | ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
892 | b4e3104b | balrog | ch->repeat = (value & 0x0200) >> 9; |
893 | b4e3104b | balrog | ch->auto_init = (value & 0x0100) >> 8; |
894 | b4e3104b | balrog | ch->priority = (value & 0x0040) >> 6; |
895 | b4e3104b | balrog | ch->fs = (value & 0x0020) >> 5; |
896 | b4e3104b | balrog | ch->sync = value & 0x001f;
|
897 | b4e3104b | balrog | |
898 | b4e3104b | balrog | if (value & 0x0080) |
899 | b4e3104b | balrog | omap_dma_enable_channel(s, ch); |
900 | b4e3104b | balrog | else
|
901 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
902 | b4e3104b | balrog | |
903 | b4e3104b | balrog | if (ch->end_prog)
|
904 | b4e3104b | balrog | omap_dma_channel_end_prog(s, ch); |
905 | b4e3104b | balrog | |
906 | b4e3104b | balrog | break;
|
907 | b4e3104b | balrog | |
908 | b4e3104b | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
909 | 827df9f3 | balrog | ch->interrupts = value & 0x3f;
|
910 | b4e3104b | balrog | break;
|
911 | b4e3104b | balrog | |
912 | b4e3104b | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
913 | b4e3104b | balrog | OMAP_RO_REG((target_phys_addr_t) reg); |
914 | b4e3104b | balrog | break;
|
915 | b4e3104b | balrog | |
916 | b4e3104b | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
917 | b4e3104b | balrog | ch->addr[0] &= 0xffff0000; |
918 | b4e3104b | balrog | ch->addr[0] |= value;
|
919 | b4e3104b | balrog | break;
|
920 | b4e3104b | balrog | |
921 | b4e3104b | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
922 | b4e3104b | balrog | ch->addr[0] &= 0x0000ffff; |
923 | b4e3104b | balrog | ch->addr[0] |= (uint32_t) value << 16; |
924 | b4e3104b | balrog | break;
|
925 | b4e3104b | balrog | |
926 | b4e3104b | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
927 | b4e3104b | balrog | ch->addr[1] &= 0xffff0000; |
928 | b4e3104b | balrog | ch->addr[1] |= value;
|
929 | b4e3104b | balrog | break;
|
930 | b4e3104b | balrog | |
931 | b4e3104b | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
932 | b4e3104b | balrog | ch->addr[1] &= 0x0000ffff; |
933 | b4e3104b | balrog | ch->addr[1] |= (uint32_t) value << 16; |
934 | b4e3104b | balrog | break;
|
935 | b4e3104b | balrog | |
936 | b4e3104b | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
937 | b4e3104b | balrog | ch->elements = value; |
938 | b4e3104b | balrog | break;
|
939 | b4e3104b | balrog | |
940 | b4e3104b | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
941 | b4e3104b | balrog | ch->frames = value; |
942 | b4e3104b | balrog | break;
|
943 | b4e3104b | balrog | |
944 | b4e3104b | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
945 | b4e3104b | balrog | ch->frame_index[0] = (int16_t) value;
|
946 | b4e3104b | balrog | break;
|
947 | b4e3104b | balrog | |
948 | b4e3104b | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
949 | b4e3104b | balrog | ch->element_index[0] = (int16_t) value;
|
950 | b4e3104b | balrog | break;
|
951 | b4e3104b | balrog | |
952 | b4e3104b | balrog | case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ |
953 | b4e3104b | balrog | OMAP_RO_REG((target_phys_addr_t) reg); |
954 | b4e3104b | balrog | break;
|
955 | b4e3104b | balrog | |
956 | b4e3104b | balrog | case 0x1c: /* DMA_CDEI */ |
957 | b4e3104b | balrog | ch->element_index[1] = (int16_t) value;
|
958 | b4e3104b | balrog | break;
|
959 | b4e3104b | balrog | |
960 | b4e3104b | balrog | case 0x1e: /* DMA_CDFI */ |
961 | b4e3104b | balrog | ch->frame_index[1] = (int16_t) value;
|
962 | b4e3104b | balrog | break;
|
963 | b4e3104b | balrog | |
964 | b4e3104b | balrog | case 0x20: /* DMA_COLOR_L */ |
965 | b4e3104b | balrog | ch->color &= 0xffff0000;
|
966 | b4e3104b | balrog | ch->color |= value; |
967 | b4e3104b | balrog | break;
|
968 | b4e3104b | balrog | |
969 | b4e3104b | balrog | case 0x22: /* DMA_COLOR_U */ |
970 | b4e3104b | balrog | ch->color &= 0xffff;
|
971 | b4e3104b | balrog | ch->color |= value << 16;
|
972 | b4e3104b | balrog | break;
|
973 | b4e3104b | balrog | |
974 | b4e3104b | balrog | case 0x24: /* DMA_CCR2 */ |
975 | 827df9f3 | balrog | ch->bs = (value >> 2) & 0x1; |
976 | b4e3104b | balrog | ch->transparent_copy = (value >> 1) & 0x1; |
977 | b4e3104b | balrog | ch->constant_fill = value & 0x1;
|
978 | b4e3104b | balrog | break;
|
979 | b4e3104b | balrog | |
980 | b4e3104b | balrog | case 0x28: /* DMA_CLNK_CTRL */ |
981 | b4e3104b | balrog | ch->link_enabled = (value >> 15) & 0x1; |
982 | b4e3104b | balrog | if (value & (1 << 14)) { /* Stop_Lnk */ |
983 | b4e3104b | balrog | ch->link_enabled = 0;
|
984 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
985 | b4e3104b | balrog | } |
986 | b4e3104b | balrog | ch->link_next_ch = value & 0x1f;
|
987 | b4e3104b | balrog | break;
|
988 | b4e3104b | balrog | |
989 | b4e3104b | balrog | case 0x2a: /* DMA_LCH_CTRL */ |
990 | b4e3104b | balrog | ch->interleave_disabled = (value >> 15) & 0x1; |
991 | b4e3104b | balrog | ch->type = value & 0xf;
|
992 | b4e3104b | balrog | break;
|
993 | b4e3104b | balrog | |
994 | b4e3104b | balrog | default:
|
995 | b4e3104b | balrog | return 1; |
996 | b4e3104b | balrog | } |
997 | b4e3104b | balrog | return 0; |
998 | b4e3104b | balrog | } |
999 | b4e3104b | balrog | |
1000 | b4e3104b | balrog | static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, |
1001 | b4e3104b | balrog | uint16_t value) |
1002 | b4e3104b | balrog | { |
1003 | b4e3104b | balrog | switch (offset) {
|
1004 | b4e3104b | balrog | case 0xbc0: /* DMA_LCD_CSDP */ |
1005 | b4e3104b | balrog | s->brust_f2 = (value >> 14) & 0x3; |
1006 | b4e3104b | balrog | s->pack_f2 = (value >> 13) & 0x1; |
1007 | b4e3104b | balrog | s->data_type_f2 = (1 << ((value >> 11) & 0x3)); |
1008 | b4e3104b | balrog | s->brust_f1 = (value >> 7) & 0x3; |
1009 | b4e3104b | balrog | s->pack_f1 = (value >> 6) & 0x1; |
1010 | b4e3104b | balrog | s->data_type_f1 = (1 << ((value >> 0) & 0x3)); |
1011 | b4e3104b | balrog | break;
|
1012 | b4e3104b | balrog | |
1013 | b4e3104b | balrog | case 0xbc2: /* DMA_LCD_CCR */ |
1014 | b4e3104b | balrog | s->mode_f2 = (value >> 14) & 0x3; |
1015 | b4e3104b | balrog | s->mode_f1 = (value >> 12) & 0x3; |
1016 | b4e3104b | balrog | s->end_prog = (value >> 11) & 0x1; |
1017 | b4e3104b | balrog | s->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
1018 | b4e3104b | balrog | s->repeat = (value >> 9) & 0x1; |
1019 | b4e3104b | balrog | s->auto_init = (value >> 8) & 0x1; |
1020 | b4e3104b | balrog | s->running = (value >> 7) & 0x1; |
1021 | b4e3104b | balrog | s->priority = (value >> 6) & 0x1; |
1022 | b4e3104b | balrog | s->bs = (value >> 4) & 0x1; |
1023 | b4e3104b | balrog | break;
|
1024 | b4e3104b | balrog | |
1025 | b4e3104b | balrog | case 0xbc4: /* DMA_LCD_CTRL */ |
1026 | b4e3104b | balrog | s->dst = (value >> 8) & 0x1; |
1027 | b4e3104b | balrog | s->src = ((value >> 6) & 0x3) << 1; |
1028 | b4e3104b | balrog | s->condition = 0;
|
1029 | b4e3104b | balrog | /* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
1030 | b4e3104b | balrog | s->interrupts = (value >> 1) & 1; |
1031 | b4e3104b | balrog | s->dual = value & 1;
|
1032 | b4e3104b | balrog | break;
|
1033 | b4e3104b | balrog | |
1034 | b4e3104b | balrog | case 0xbc8: /* TOP_B1_L */ |
1035 | b4e3104b | balrog | s->src_f1_top &= 0xffff0000;
|
1036 | b4e3104b | balrog | s->src_f1_top |= 0x0000ffff & value;
|
1037 | b4e3104b | balrog | break;
|
1038 | b4e3104b | balrog | |
1039 | b4e3104b | balrog | case 0xbca: /* TOP_B1_U */ |
1040 | b4e3104b | balrog | s->src_f1_top &= 0x0000ffff;
|
1041 | b4e3104b | balrog | s->src_f1_top |= value << 16;
|
1042 | b4e3104b | balrog | break;
|
1043 | b4e3104b | balrog | |
1044 | b4e3104b | balrog | case 0xbcc: /* BOT_B1_L */ |
1045 | b4e3104b | balrog | s->src_f1_bottom &= 0xffff0000;
|
1046 | b4e3104b | balrog | s->src_f1_bottom |= 0x0000ffff & value;
|
1047 | b4e3104b | balrog | break;
|
1048 | b4e3104b | balrog | |
1049 | b4e3104b | balrog | case 0xbce: /* BOT_B1_U */ |
1050 | b4e3104b | balrog | s->src_f1_bottom &= 0x0000ffff;
|
1051 | b4e3104b | balrog | s->src_f1_bottom |= (uint32_t) value << 16;
|
1052 | b4e3104b | balrog | break;
|
1053 | b4e3104b | balrog | |
1054 | b4e3104b | balrog | case 0xbd0: /* TOP_B2_L */ |
1055 | b4e3104b | balrog | s->src_f2_top &= 0xffff0000;
|
1056 | b4e3104b | balrog | s->src_f2_top |= 0x0000ffff & value;
|
1057 | b4e3104b | balrog | break;
|
1058 | b4e3104b | balrog | |
1059 | b4e3104b | balrog | case 0xbd2: /* TOP_B2_U */ |
1060 | b4e3104b | balrog | s->src_f2_top &= 0x0000ffff;
|
1061 | b4e3104b | balrog | s->src_f2_top |= (uint32_t) value << 16;
|
1062 | b4e3104b | balrog | break;
|
1063 | b4e3104b | balrog | |
1064 | b4e3104b | balrog | case 0xbd4: /* BOT_B2_L */ |
1065 | b4e3104b | balrog | s->src_f2_bottom &= 0xffff0000;
|
1066 | b4e3104b | balrog | s->src_f2_bottom |= 0x0000ffff & value;
|
1067 | b4e3104b | balrog | break;
|
1068 | b4e3104b | balrog | |
1069 | b4e3104b | balrog | case 0xbd6: /* BOT_B2_U */ |
1070 | b4e3104b | balrog | s->src_f2_bottom &= 0x0000ffff;
|
1071 | b4e3104b | balrog | s->src_f2_bottom |= (uint32_t) value << 16;
|
1072 | b4e3104b | balrog | break;
|
1073 | b4e3104b | balrog | |
1074 | b4e3104b | balrog | case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ |
1075 | b4e3104b | balrog | s->element_index_f1 = value; |
1076 | b4e3104b | balrog | break;
|
1077 | b4e3104b | balrog | |
1078 | b4e3104b | balrog | case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ |
1079 | b4e3104b | balrog | s->frame_index_f1 &= 0xffff0000;
|
1080 | b4e3104b | balrog | s->frame_index_f1 |= 0x0000ffff & value;
|
1081 | b4e3104b | balrog | break;
|
1082 | b4e3104b | balrog | |
1083 | b4e3104b | balrog | case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ |
1084 | b4e3104b | balrog | s->frame_index_f1 &= 0x0000ffff;
|
1085 | b4e3104b | balrog | s->frame_index_f1 |= (uint32_t) value << 16;
|
1086 | b4e3104b | balrog | break;
|
1087 | b4e3104b | balrog | |
1088 | b4e3104b | balrog | case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ |
1089 | b4e3104b | balrog | s->element_index_f2 = value; |
1090 | b4e3104b | balrog | break;
|
1091 | b4e3104b | balrog | |
1092 | b4e3104b | balrog | case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ |
1093 | b4e3104b | balrog | s->frame_index_f2 &= 0xffff0000;
|
1094 | b4e3104b | balrog | s->frame_index_f2 |= 0x0000ffff & value;
|
1095 | b4e3104b | balrog | break;
|
1096 | b4e3104b | balrog | |
1097 | b4e3104b | balrog | case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ |
1098 | b4e3104b | balrog | s->frame_index_f2 &= 0x0000ffff;
|
1099 | b4e3104b | balrog | s->frame_index_f2 |= (uint32_t) value << 16;
|
1100 | b4e3104b | balrog | break;
|
1101 | b4e3104b | balrog | |
1102 | b4e3104b | balrog | case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ |
1103 | b4e3104b | balrog | s->elements_f1 = value; |
1104 | b4e3104b | balrog | break;
|
1105 | b4e3104b | balrog | |
1106 | b4e3104b | balrog | case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ |
1107 | b4e3104b | balrog | s->frames_f1 = value; |
1108 | b4e3104b | balrog | break;
|
1109 | b4e3104b | balrog | |
1110 | b4e3104b | balrog | case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ |
1111 | b4e3104b | balrog | s->elements_f2 = value; |
1112 | b4e3104b | balrog | break;
|
1113 | b4e3104b | balrog | |
1114 | b4e3104b | balrog | case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ |
1115 | b4e3104b | balrog | s->frames_f2 = value; |
1116 | b4e3104b | balrog | break;
|
1117 | b4e3104b | balrog | |
1118 | b4e3104b | balrog | case 0xbea: /* DMA_LCD_LCH_CTRL */ |
1119 | b4e3104b | balrog | s->lch_type = value & 0xf;
|
1120 | b4e3104b | balrog | break;
|
1121 | b4e3104b | balrog | |
1122 | b4e3104b | balrog | default:
|
1123 | b4e3104b | balrog | return 1; |
1124 | b4e3104b | balrog | } |
1125 | b4e3104b | balrog | return 0; |
1126 | b4e3104b | balrog | } |
1127 | b4e3104b | balrog | |
1128 | b4e3104b | balrog | static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, |
1129 | b4e3104b | balrog | uint16_t *ret) |
1130 | b4e3104b | balrog | { |
1131 | b4e3104b | balrog | switch (offset) {
|
1132 | b4e3104b | balrog | case 0xbc0: /* DMA_LCD_CSDP */ |
1133 | b4e3104b | balrog | *ret = (s->brust_f2 << 14) |
|
1134 | b4e3104b | balrog | (s->pack_f2 << 13) |
|
1135 | b4e3104b | balrog | ((s->data_type_f2 >> 1) << 11) | |
1136 | b4e3104b | balrog | (s->brust_f1 << 7) |
|
1137 | b4e3104b | balrog | (s->pack_f1 << 6) |
|
1138 | b4e3104b | balrog | ((s->data_type_f1 >> 1) << 0); |
1139 | b4e3104b | balrog | break;
|
1140 | b4e3104b | balrog | |
1141 | b4e3104b | balrog | case 0xbc2: /* DMA_LCD_CCR */ |
1142 | b4e3104b | balrog | *ret = (s->mode_f2 << 14) |
|
1143 | b4e3104b | balrog | (s->mode_f1 << 12) |
|
1144 | b4e3104b | balrog | (s->end_prog << 11) |
|
1145 | b4e3104b | balrog | (s->omap_3_1_compatible_disable << 10) |
|
1146 | b4e3104b | balrog | (s->repeat << 9) |
|
1147 | b4e3104b | balrog | (s->auto_init << 8) |
|
1148 | b4e3104b | balrog | (s->running << 7) |
|
1149 | b4e3104b | balrog | (s->priority << 6) |
|
1150 | b4e3104b | balrog | (s->bs << 4);
|
1151 | b4e3104b | balrog | break;
|
1152 | b4e3104b | balrog | |
1153 | b4e3104b | balrog | case 0xbc4: /* DMA_LCD_CTRL */ |
1154 | b4e3104b | balrog | qemu_irq_lower(s->irq); |
1155 | b4e3104b | balrog | *ret = (s->dst << 8) |
|
1156 | b4e3104b | balrog | ((s->src & 0x6) << 5) | |
1157 | b4e3104b | balrog | (s->condition << 3) |
|
1158 | b4e3104b | balrog | (s->interrupts << 1) |
|
1159 | b4e3104b | balrog | s->dual; |
1160 | b4e3104b | balrog | break;
|
1161 | b4e3104b | balrog | |
1162 | b4e3104b | balrog | case 0xbc8: /* TOP_B1_L */ |
1163 | b4e3104b | balrog | *ret = s->src_f1_top & 0xffff;
|
1164 | b4e3104b | balrog | break;
|
1165 | b4e3104b | balrog | |
1166 | b4e3104b | balrog | case 0xbca: /* TOP_B1_U */ |
1167 | b4e3104b | balrog | *ret = s->src_f1_top >> 16;
|
1168 | b4e3104b | balrog | break;
|
1169 | b4e3104b | balrog | |
1170 | b4e3104b | balrog | case 0xbcc: /* BOT_B1_L */ |
1171 | b4e3104b | balrog | *ret = s->src_f1_bottom & 0xffff;
|
1172 | b4e3104b | balrog | break;
|
1173 | b4e3104b | balrog | |
1174 | b4e3104b | balrog | case 0xbce: /* BOT_B1_U */ |
1175 | b4e3104b | balrog | *ret = s->src_f1_bottom >> 16;
|
1176 | b4e3104b | balrog | break;
|
1177 | b4e3104b | balrog | |
1178 | b4e3104b | balrog | case 0xbd0: /* TOP_B2_L */ |
1179 | b4e3104b | balrog | *ret = s->src_f2_top & 0xffff;
|
1180 | b4e3104b | balrog | break;
|
1181 | b4e3104b | balrog | |
1182 | b4e3104b | balrog | case 0xbd2: /* TOP_B2_U */ |
1183 | b4e3104b | balrog | *ret = s->src_f2_top >> 16;
|
1184 | b4e3104b | balrog | break;
|
1185 | b4e3104b | balrog | |
1186 | b4e3104b | balrog | case 0xbd4: /* BOT_B2_L */ |
1187 | b4e3104b | balrog | *ret = s->src_f2_bottom & 0xffff;
|
1188 | b4e3104b | balrog | break;
|
1189 | b4e3104b | balrog | |
1190 | b4e3104b | balrog | case 0xbd6: /* BOT_B2_U */ |
1191 | b4e3104b | balrog | *ret = s->src_f2_bottom >> 16;
|
1192 | b4e3104b | balrog | break;
|
1193 | b4e3104b | balrog | |
1194 | b4e3104b | balrog | case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ |
1195 | b4e3104b | balrog | *ret = s->element_index_f1; |
1196 | b4e3104b | balrog | break;
|
1197 | b4e3104b | balrog | |
1198 | b4e3104b | balrog | case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ |
1199 | b4e3104b | balrog | *ret = s->frame_index_f1 & 0xffff;
|
1200 | b4e3104b | balrog | break;
|
1201 | b4e3104b | balrog | |
1202 | b4e3104b | balrog | case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ |
1203 | b4e3104b | balrog | *ret = s->frame_index_f1 >> 16;
|
1204 | b4e3104b | balrog | break;
|
1205 | b4e3104b | balrog | |
1206 | b4e3104b | balrog | case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ |
1207 | b4e3104b | balrog | *ret = s->element_index_f2; |
1208 | b4e3104b | balrog | break;
|
1209 | b4e3104b | balrog | |
1210 | b4e3104b | balrog | case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ |
1211 | b4e3104b | balrog | *ret = s->frame_index_f2 & 0xffff;
|
1212 | b4e3104b | balrog | break;
|
1213 | b4e3104b | balrog | |
1214 | b4e3104b | balrog | case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ |
1215 | b4e3104b | balrog | *ret = s->frame_index_f2 >> 16;
|
1216 | b4e3104b | balrog | break;
|
1217 | b4e3104b | balrog | |
1218 | b4e3104b | balrog | case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ |
1219 | b4e3104b | balrog | *ret = s->elements_f1; |
1220 | b4e3104b | balrog | break;
|
1221 | b4e3104b | balrog | |
1222 | b4e3104b | balrog | case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ |
1223 | b4e3104b | balrog | *ret = s->frames_f1; |
1224 | b4e3104b | balrog | break;
|
1225 | b4e3104b | balrog | |
1226 | b4e3104b | balrog | case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ |
1227 | b4e3104b | balrog | *ret = s->elements_f2; |
1228 | b4e3104b | balrog | break;
|
1229 | b4e3104b | balrog | |
1230 | b4e3104b | balrog | case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ |
1231 | b4e3104b | balrog | *ret = s->frames_f2; |
1232 | b4e3104b | balrog | break;
|
1233 | b4e3104b | balrog | |
1234 | b4e3104b | balrog | case 0xbea: /* DMA_LCD_LCH_CTRL */ |
1235 | b4e3104b | balrog | *ret = s->lch_type; |
1236 | b4e3104b | balrog | break;
|
1237 | b4e3104b | balrog | |
1238 | b4e3104b | balrog | default:
|
1239 | b4e3104b | balrog | return 1; |
1240 | b4e3104b | balrog | } |
1241 | b4e3104b | balrog | return 0; |
1242 | b4e3104b | balrog | } |
1243 | b4e3104b | balrog | |
1244 | b4e3104b | balrog | static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, |
1245 | b4e3104b | balrog | uint16_t value) |
1246 | b4e3104b | balrog | { |
1247 | b4e3104b | balrog | switch (offset) {
|
1248 | b4e3104b | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
1249 | b4e3104b | balrog | s->src = (value & 0x40) ? imif : emiff;
|
1250 | b4e3104b | balrog | s->condition = 0;
|
1251 | b4e3104b | balrog | /* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
1252 | b4e3104b | balrog | s->interrupts = (value >> 1) & 1; |
1253 | b4e3104b | balrog | s->dual = value & 1;
|
1254 | b4e3104b | balrog | break;
|
1255 | b4e3104b | balrog | |
1256 | b4e3104b | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
1257 | b4e3104b | balrog | s->src_f1_top &= 0xffff0000;
|
1258 | b4e3104b | balrog | s->src_f1_top |= 0x0000ffff & value;
|
1259 | b4e3104b | balrog | break;
|
1260 | b4e3104b | balrog | |
1261 | b4e3104b | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
1262 | b4e3104b | balrog | s->src_f1_top &= 0x0000ffff;
|
1263 | b4e3104b | balrog | s->src_f1_top |= value << 16;
|
1264 | b4e3104b | balrog | break;
|
1265 | b4e3104b | balrog | |
1266 | b4e3104b | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
1267 | b4e3104b | balrog | s->src_f1_bottom &= 0xffff0000;
|
1268 | b4e3104b | balrog | s->src_f1_bottom |= 0x0000ffff & value;
|
1269 | b4e3104b | balrog | break;
|
1270 | b4e3104b | balrog | |
1271 | b4e3104b | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
1272 | b4e3104b | balrog | s->src_f1_bottom &= 0x0000ffff;
|
1273 | b4e3104b | balrog | s->src_f1_bottom |= value << 16;
|
1274 | b4e3104b | balrog | break;
|
1275 | b4e3104b | balrog | |
1276 | b4e3104b | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
1277 | b4e3104b | balrog | s->src_f2_top &= 0xffff0000;
|
1278 | b4e3104b | balrog | s->src_f2_top |= 0x0000ffff & value;
|
1279 | b4e3104b | balrog | break;
|
1280 | b4e3104b | balrog | |
1281 | b4e3104b | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
1282 | b4e3104b | balrog | s->src_f2_top &= 0x0000ffff;
|
1283 | b4e3104b | balrog | s->src_f2_top |= value << 16;
|
1284 | b4e3104b | balrog | break;
|
1285 | b4e3104b | balrog | |
1286 | b4e3104b | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
1287 | b4e3104b | balrog | s->src_f2_bottom &= 0xffff0000;
|
1288 | b4e3104b | balrog | s->src_f2_bottom |= 0x0000ffff & value;
|
1289 | b4e3104b | balrog | break;
|
1290 | b4e3104b | balrog | |
1291 | b4e3104b | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
1292 | b4e3104b | balrog | s->src_f2_bottom &= 0x0000ffff;
|
1293 | b4e3104b | balrog | s->src_f2_bottom |= value << 16;
|
1294 | b4e3104b | balrog | break;
|
1295 | b4e3104b | balrog | |
1296 | b4e3104b | balrog | default:
|
1297 | b4e3104b | balrog | return 1; |
1298 | b4e3104b | balrog | } |
1299 | b4e3104b | balrog | return 0; |
1300 | b4e3104b | balrog | } |
1301 | b4e3104b | balrog | |
1302 | b4e3104b | balrog | static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, |
1303 | b4e3104b | balrog | uint16_t *ret) |
1304 | b4e3104b | balrog | { |
1305 | b4e3104b | balrog | int i;
|
1306 | b4e3104b | balrog | |
1307 | b4e3104b | balrog | switch (offset) {
|
1308 | b4e3104b | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
1309 | b4e3104b | balrog | i = s->condition; |
1310 | b4e3104b | balrog | s->condition = 0;
|
1311 | b4e3104b | balrog | qemu_irq_lower(s->irq); |
1312 | b4e3104b | balrog | *ret = ((s->src == imif) << 6) | (i << 3) | |
1313 | b4e3104b | balrog | (s->interrupts << 1) | s->dual;
|
1314 | b4e3104b | balrog | break;
|
1315 | b4e3104b | balrog | |
1316 | b4e3104b | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
1317 | b4e3104b | balrog | *ret = s->src_f1_top & 0xffff;
|
1318 | b4e3104b | balrog | break;
|
1319 | b4e3104b | balrog | |
1320 | b4e3104b | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
1321 | b4e3104b | balrog | *ret = s->src_f1_top >> 16;
|
1322 | b4e3104b | balrog | break;
|
1323 | b4e3104b | balrog | |
1324 | b4e3104b | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
1325 | b4e3104b | balrog | *ret = s->src_f1_bottom & 0xffff;
|
1326 | b4e3104b | balrog | break;
|
1327 | b4e3104b | balrog | |
1328 | b4e3104b | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
1329 | b4e3104b | balrog | *ret = s->src_f1_bottom >> 16;
|
1330 | b4e3104b | balrog | break;
|
1331 | b4e3104b | balrog | |
1332 | b4e3104b | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
1333 | b4e3104b | balrog | *ret = s->src_f2_top & 0xffff;
|
1334 | b4e3104b | balrog | break;
|
1335 | b4e3104b | balrog | |
1336 | b4e3104b | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
1337 | b4e3104b | balrog | *ret = s->src_f2_top >> 16;
|
1338 | b4e3104b | balrog | break;
|
1339 | b4e3104b | balrog | |
1340 | b4e3104b | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
1341 | b4e3104b | balrog | *ret = s->src_f2_bottom & 0xffff;
|
1342 | b4e3104b | balrog | break;
|
1343 | b4e3104b | balrog | |
1344 | b4e3104b | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
1345 | b4e3104b | balrog | *ret = s->src_f2_bottom >> 16;
|
1346 | b4e3104b | balrog | break;
|
1347 | b4e3104b | balrog | |
1348 | b4e3104b | balrog | default:
|
1349 | b4e3104b | balrog | return 1; |
1350 | b4e3104b | balrog | } |
1351 | b4e3104b | balrog | return 0; |
1352 | b4e3104b | balrog | } |
1353 | b4e3104b | balrog | |
1354 | b4e3104b | balrog | static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) |
1355 | b4e3104b | balrog | { |
1356 | b4e3104b | balrog | switch (offset) {
|
1357 | b4e3104b | balrog | case 0x400: /* SYS_DMA_GCR */ |
1358 | b4e3104b | balrog | s->gcr = value; |
1359 | b4e3104b | balrog | break;
|
1360 | b4e3104b | balrog | |
1361 | b4e3104b | balrog | case 0x404: /* DMA_GSCR */ |
1362 | b4e3104b | balrog | if (value & 0x8) |
1363 | b4e3104b | balrog | omap_dma_disable_3_1_mapping(s); |
1364 | b4e3104b | balrog | else
|
1365 | b4e3104b | balrog | omap_dma_enable_3_1_mapping(s); |
1366 | b4e3104b | balrog | break;
|
1367 | b4e3104b | balrog | |
1368 | b4e3104b | balrog | case 0x408: /* DMA_GRST */ |
1369 | b4e3104b | balrog | if (value & 0x1) |
1370 | afbb5194 | balrog | omap_dma_reset(s->dma); |
1371 | b4e3104b | balrog | break;
|
1372 | b4e3104b | balrog | |
1373 | b4e3104b | balrog | default:
|
1374 | b4e3104b | balrog | return 1; |
1375 | b4e3104b | balrog | } |
1376 | b4e3104b | balrog | return 0; |
1377 | b4e3104b | balrog | } |
1378 | b4e3104b | balrog | |
1379 | b4e3104b | balrog | static int omap_dma_sys_read(struct omap_dma_s *s, int offset, |
1380 | b4e3104b | balrog | uint16_t *ret) |
1381 | b4e3104b | balrog | { |
1382 | b4e3104b | balrog | switch (offset) {
|
1383 | b4e3104b | balrog | case 0x400: /* SYS_DMA_GCR */ |
1384 | b4e3104b | balrog | *ret = s->gcr; |
1385 | b4e3104b | balrog | break;
|
1386 | b4e3104b | balrog | |
1387 | b4e3104b | balrog | case 0x404: /* DMA_GSCR */ |
1388 | b4e3104b | balrog | *ret = s->omap_3_1_mapping_disabled << 3;
|
1389 | b4e3104b | balrog | break;
|
1390 | b4e3104b | balrog | |
1391 | b4e3104b | balrog | case 0x408: /* DMA_GRST */ |
1392 | b4e3104b | balrog | *ret = 0;
|
1393 | b4e3104b | balrog | break;
|
1394 | b4e3104b | balrog | |
1395 | b4e3104b | balrog | case 0x442: /* DMA_HW_ID */ |
1396 | b4e3104b | balrog | case 0x444: /* DMA_PCh2_ID */ |
1397 | b4e3104b | balrog | case 0x446: /* DMA_PCh0_ID */ |
1398 | b4e3104b | balrog | case 0x448: /* DMA_PCh1_ID */ |
1399 | b4e3104b | balrog | case 0x44a: /* DMA_PChG_ID */ |
1400 | b4e3104b | balrog | case 0x44c: /* DMA_PChD_ID */ |
1401 | b4e3104b | balrog | *ret = 1;
|
1402 | b4e3104b | balrog | break;
|
1403 | b4e3104b | balrog | |
1404 | b4e3104b | balrog | case 0x44e: /* DMA_CAPS_0_U */ |
1405 | 827df9f3 | balrog | *ret = (s->caps[0] >> 16) & 0xffff; |
1406 | b4e3104b | balrog | break;
|
1407 | b4e3104b | balrog | case 0x450: /* DMA_CAPS_0_L */ |
1408 | 827df9f3 | balrog | *ret = (s->caps[0] >> 0) & 0xffff; |
1409 | b4e3104b | balrog | break;
|
1410 | b4e3104b | balrog | |
1411 | 827df9f3 | balrog | case 0x452: /* DMA_CAPS_1_U */ |
1412 | 827df9f3 | balrog | *ret = (s->caps[1] >> 16) & 0xffff; |
1413 | 827df9f3 | balrog | break;
|
1414 | b4e3104b | balrog | case 0x454: /* DMA_CAPS_1_L */ |
1415 | 827df9f3 | balrog | *ret = (s->caps[1] >> 0) & 0xffff; |
1416 | b4e3104b | balrog | break;
|
1417 | b4e3104b | balrog | |
1418 | b4e3104b | balrog | case 0x456: /* DMA_CAPS_2 */ |
1419 | 827df9f3 | balrog | *ret = s->caps[2];
|
1420 | b4e3104b | balrog | break;
|
1421 | b4e3104b | balrog | |
1422 | b4e3104b | balrog | case 0x458: /* DMA_CAPS_3 */ |
1423 | 827df9f3 | balrog | *ret = s->caps[3];
|
1424 | b4e3104b | balrog | break;
|
1425 | b4e3104b | balrog | |
1426 | b4e3104b | balrog | case 0x45a: /* DMA_CAPS_4 */ |
1427 | 827df9f3 | balrog | *ret = s->caps[4];
|
1428 | b4e3104b | balrog | break;
|
1429 | b4e3104b | balrog | |
1430 | b4e3104b | balrog | case 0x460: /* DMA_PCh2_SR */ |
1431 | b4e3104b | balrog | case 0x480: /* DMA_PCh0_SR */ |
1432 | b4e3104b | balrog | case 0x482: /* DMA_PCh1_SR */ |
1433 | b4e3104b | balrog | case 0x4c0: /* DMA_PChD_SR_0 */ |
1434 | b4e3104b | balrog | printf("%s: Physical Channel Status Registers not implemented.\n",
|
1435 | b4e3104b | balrog | __FUNCTION__); |
1436 | b4e3104b | balrog | *ret = 0xff;
|
1437 | b4e3104b | balrog | break;
|
1438 | b4e3104b | balrog | |
1439 | b4e3104b | balrog | default:
|
1440 | b4e3104b | balrog | return 1; |
1441 | b4e3104b | balrog | } |
1442 | b4e3104b | balrog | return 0; |
1443 | b4e3104b | balrog | } |
1444 | b4e3104b | balrog | |
1445 | b4e3104b | balrog | static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) |
1446 | b4e3104b | balrog | { |
1447 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1448 | 8da3ff18 | pbrook | int reg, ch;
|
1449 | b4e3104b | balrog | uint16_t ret; |
1450 | b4e3104b | balrog | |
1451 | 8da3ff18 | pbrook | switch (addr) {
|
1452 | b4e3104b | balrog | case 0x300 ... 0x3fe: |
1453 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
1454 | 8da3ff18 | pbrook | if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
|
1455 | b4e3104b | balrog | break;
|
1456 | b4e3104b | balrog | return ret;
|
1457 | b4e3104b | balrog | } |
1458 | b4e3104b | balrog | /* Fall through. */
|
1459 | b4e3104b | balrog | case 0x000 ... 0x2fe: |
1460 | 8da3ff18 | pbrook | reg = addr & 0x3f;
|
1461 | 8da3ff18 | pbrook | ch = (addr >> 6) & 0x0f; |
1462 | b4e3104b | balrog | if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
|
1463 | b4e3104b | balrog | break;
|
1464 | b4e3104b | balrog | return ret;
|
1465 | b4e3104b | balrog | |
1466 | b4e3104b | balrog | case 0x404 ... 0x4fe: |
1467 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1)
|
1468 | b4e3104b | balrog | break;
|
1469 | b4e3104b | balrog | /* Fall through. */
|
1470 | b4e3104b | balrog | case 0x400: |
1471 | 8da3ff18 | pbrook | if (omap_dma_sys_read(s, addr, &ret))
|
1472 | b4e3104b | balrog | break;
|
1473 | b4e3104b | balrog | return ret;
|
1474 | b4e3104b | balrog | |
1475 | b4e3104b | balrog | case 0xb00 ... 0xbfe: |
1476 | b4e3104b | balrog | if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
1477 | 8da3ff18 | pbrook | if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
|
1478 | b4e3104b | balrog | break;
|
1479 | b4e3104b | balrog | return ret;
|
1480 | b4e3104b | balrog | } |
1481 | b4e3104b | balrog | break;
|
1482 | b4e3104b | balrog | } |
1483 | b4e3104b | balrog | |
1484 | b4e3104b | balrog | OMAP_BAD_REG(addr); |
1485 | b4e3104b | balrog | return 0; |
1486 | b4e3104b | balrog | } |
1487 | b4e3104b | balrog | |
1488 | b4e3104b | balrog | static void omap_dma_write(void *opaque, target_phys_addr_t addr, |
1489 | b4e3104b | balrog | uint32_t value) |
1490 | b4e3104b | balrog | { |
1491 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1492 | 8da3ff18 | pbrook | int reg, ch;
|
1493 | b4e3104b | balrog | |
1494 | 8da3ff18 | pbrook | switch (addr) {
|
1495 | b4e3104b | balrog | case 0x300 ... 0x3fe: |
1496 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
1497 | 8da3ff18 | pbrook | if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
|
1498 | b4e3104b | balrog | break;
|
1499 | b4e3104b | balrog | return;
|
1500 | b4e3104b | balrog | } |
1501 | b4e3104b | balrog | /* Fall through. */
|
1502 | b4e3104b | balrog | case 0x000 ... 0x2fe: |
1503 | 8da3ff18 | pbrook | reg = addr & 0x3f;
|
1504 | 8da3ff18 | pbrook | ch = (addr >> 6) & 0x0f; |
1505 | b4e3104b | balrog | if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
|
1506 | b4e3104b | balrog | break;
|
1507 | b4e3104b | balrog | return;
|
1508 | b4e3104b | balrog | |
1509 | b4e3104b | balrog | case 0x404 ... 0x4fe: |
1510 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1)
|
1511 | b4e3104b | balrog | break;
|
1512 | b4e3104b | balrog | case 0x400: |
1513 | b4e3104b | balrog | /* Fall through. */
|
1514 | 8da3ff18 | pbrook | if (omap_dma_sys_write(s, addr, value))
|
1515 | b4e3104b | balrog | break;
|
1516 | b4e3104b | balrog | return;
|
1517 | b4e3104b | balrog | |
1518 | b4e3104b | balrog | case 0xb00 ... 0xbfe: |
1519 | b4e3104b | balrog | if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
1520 | 8da3ff18 | pbrook | if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
|
1521 | b4e3104b | balrog | break;
|
1522 | b4e3104b | balrog | return;
|
1523 | b4e3104b | balrog | } |
1524 | b4e3104b | balrog | break;
|
1525 | b4e3104b | balrog | } |
1526 | b4e3104b | balrog | |
1527 | b4e3104b | balrog | OMAP_BAD_REG(addr); |
1528 | b4e3104b | balrog | } |
1529 | b4e3104b | balrog | |
1530 | b4e3104b | balrog | static CPUReadMemoryFunc *omap_dma_readfn[] = {
|
1531 | b4e3104b | balrog | omap_badwidth_read16, |
1532 | b4e3104b | balrog | omap_dma_read, |
1533 | b4e3104b | balrog | omap_badwidth_read16, |
1534 | b4e3104b | balrog | }; |
1535 | b4e3104b | balrog | |
1536 | b4e3104b | balrog | static CPUWriteMemoryFunc *omap_dma_writefn[] = {
|
1537 | b4e3104b | balrog | omap_badwidth_write16, |
1538 | b4e3104b | balrog | omap_dma_write, |
1539 | b4e3104b | balrog | omap_badwidth_write16, |
1540 | b4e3104b | balrog | }; |
1541 | b4e3104b | balrog | |
1542 | b4e3104b | balrog | static void omap_dma_request(void *opaque, int drq, int req) |
1543 | b4e3104b | balrog | { |
1544 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1545 | 827df9f3 | balrog | /* The request pins are level triggered in QEMU. */
|
1546 | b4e3104b | balrog | if (req) {
|
1547 | afbb5194 | balrog | if (~s->dma->drqbmp & (1 << drq)) { |
1548 | afbb5194 | balrog | s->dma->drqbmp |= 1 << drq;
|
1549 | b4e3104b | balrog | omap_dma_process_request(s, drq); |
1550 | b4e3104b | balrog | } |
1551 | b4e3104b | balrog | } else
|
1552 | afbb5194 | balrog | s->dma->drqbmp &= ~(1 << drq);
|
1553 | b4e3104b | balrog | } |
1554 | b4e3104b | balrog | |
1555 | afbb5194 | balrog | /* XXX: this won't be needed once soc_dma knows about clocks. */
|
1556 | b4e3104b | balrog | static void omap_dma_clk_update(void *opaque, int line, int on) |
1557 | b4e3104b | balrog | { |
1558 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1559 | afbb5194 | balrog | int i;
|
1560 | b4e3104b | balrog | |
1561 | afbb5194 | balrog | s->dma->freq = omap_clk_getrate(s->clk); |
1562 | afbb5194 | balrog | |
1563 | afbb5194 | balrog | for (i = 0; i < s->chans; i ++) |
1564 | afbb5194 | balrog | if (s->ch[i].active)
|
1565 | afbb5194 | balrog | soc_dma_set_request(s->ch[i].dma, on); |
1566 | b4e3104b | balrog | } |
1567 | b4e3104b | balrog | |
1568 | 827df9f3 | balrog | static void omap_dma_setcaps(struct omap_dma_s *s) |
1569 | 827df9f3 | balrog | { |
1570 | 827df9f3 | balrog | switch (s->model) {
|
1571 | 827df9f3 | balrog | default:
|
1572 | 827df9f3 | balrog | case omap_dma_3_1:
|
1573 | 827df9f3 | balrog | break;
|
1574 | 827df9f3 | balrog | case omap_dma_3_2:
|
1575 | 827df9f3 | balrog | case omap_dma_4:
|
1576 | 827df9f3 | balrog | /* XXX Only available for sDMA */
|
1577 | 827df9f3 | balrog | s->caps[0] =
|
1578 | 827df9f3 | balrog | (1 << 19) | /* Constant Fill Capability */ |
1579 | 827df9f3 | balrog | (1 << 18); /* Transparent BLT Capability */ |
1580 | 827df9f3 | balrog | s->caps[1] =
|
1581 | 827df9f3 | balrog | (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */ |
1582 | 827df9f3 | balrog | s->caps[2] =
|
1583 | 827df9f3 | balrog | (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ |
1584 | 827df9f3 | balrog | (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ |
1585 | 827df9f3 | balrog | (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ |
1586 | 827df9f3 | balrog | (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ |
1587 | 827df9f3 | balrog | (1 << 4) | /* DST_CONST_ADRS_CPBLTY */ |
1588 | 827df9f3 | balrog | (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ |
1589 | 827df9f3 | balrog | (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ |
1590 | 827df9f3 | balrog | (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ |
1591 | 827df9f3 | balrog | (1 << 0); /* SRC_CONST_ADRS_CPBLTY */ |
1592 | 827df9f3 | balrog | s->caps[3] =
|
1593 | 827df9f3 | balrog | (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ |
1594 | 827df9f3 | balrog | (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ |
1595 | 827df9f3 | balrog | (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ |
1596 | 827df9f3 | balrog | (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ |
1597 | 827df9f3 | balrog | (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ |
1598 | 827df9f3 | balrog | (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ |
1599 | 827df9f3 | balrog | (1 << 1) | /* FRAME_SYNCHR_CPBLTY */ |
1600 | 827df9f3 | balrog | (1 << 0); /* ELMNT_SYNCHR_CPBLTY */ |
1601 | 827df9f3 | balrog | s->caps[4] =
|
1602 | 827df9f3 | balrog | (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ |
1603 | 827df9f3 | balrog | (1 << 6) | /* SYNC_STATUS_CPBLTY */ |
1604 | 827df9f3 | balrog | (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ |
1605 | 827df9f3 | balrog | (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ |
1606 | 827df9f3 | balrog | (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ |
1607 | 827df9f3 | balrog | (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ |
1608 | 827df9f3 | balrog | (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ |
1609 | 827df9f3 | balrog | (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ |
1610 | 827df9f3 | balrog | break;
|
1611 | 827df9f3 | balrog | } |
1612 | 827df9f3 | balrog | } |
1613 | 827df9f3 | balrog | |
1614 | afbb5194 | balrog | struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
|
1615 | b4e3104b | balrog | qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
|
1616 | b4e3104b | balrog | enum omap_dma_model model)
|
1617 | b4e3104b | balrog | { |
1618 | b4e3104b | balrog | int iomemtype, num_irqs, memsize, i;
|
1619 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) |
1620 | b4e3104b | balrog | qemu_mallocz(sizeof(struct omap_dma_s)); |
1621 | b4e3104b | balrog | |
1622 | 827df9f3 | balrog | if (model <= omap_dma_3_1) {
|
1623 | b4e3104b | balrog | num_irqs = 6;
|
1624 | b4e3104b | balrog | memsize = 0x800;
|
1625 | b4e3104b | balrog | } else {
|
1626 | b4e3104b | balrog | num_irqs = 16;
|
1627 | b4e3104b | balrog | memsize = 0xc00;
|
1628 | b4e3104b | balrog | } |
1629 | b4e3104b | balrog | s->model = model; |
1630 | b4e3104b | balrog | s->mpu = mpu; |
1631 | b4e3104b | balrog | s->clk = clk; |
1632 | b4e3104b | balrog | s->lcd_ch.irq = lcd_irq; |
1633 | b4e3104b | balrog | s->lcd_ch.mpu = mpu; |
1634 | afbb5194 | balrog | |
1635 | afbb5194 | balrog | s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16); |
1636 | afbb5194 | balrog | s->dma->freq = omap_clk_getrate(clk); |
1637 | afbb5194 | balrog | s->dma->transfer_fn = omap_dma_transfer_generic; |
1638 | afbb5194 | balrog | s->dma->setup_fn = omap_dma_transfer_setup; |
1639 | afbb5194 | balrog | s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
|
1640 | afbb5194 | balrog | s->dma->opaque = s; |
1641 | afbb5194 | balrog | |
1642 | b4e3104b | balrog | while (num_irqs --)
|
1643 | b4e3104b | balrog | s->ch[num_irqs].irq = irqs[num_irqs]; |
1644 | b4e3104b | balrog | for (i = 0; i < 3; i ++) { |
1645 | b4e3104b | balrog | s->ch[i].sibling = &s->ch[i + 6];
|
1646 | b4e3104b | balrog | s->ch[i + 6].sibling = &s->ch[i];
|
1647 | b4e3104b | balrog | } |
1648 | afbb5194 | balrog | for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) { |
1649 | afbb5194 | balrog | s->ch[i].dma = &s->dma->ch[i]; |
1650 | afbb5194 | balrog | s->dma->ch[i].opaque = &s->ch[i]; |
1651 | afbb5194 | balrog | } |
1652 | afbb5194 | balrog | |
1653 | afbb5194 | balrog | omap_dma_setcaps(s); |
1654 | b4e3104b | balrog | omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
1655 | afbb5194 | balrog | omap_dma_reset(s->dma); |
1656 | b4e3104b | balrog | omap_dma_clk_update(s, 0, 1); |
1657 | b4e3104b | balrog | |
1658 | b4e3104b | balrog | iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
|
1659 | b4e3104b | balrog | omap_dma_writefn, s); |
1660 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, memsize, iomemtype); |
1661 | b4e3104b | balrog | |
1662 | afbb5194 | balrog | mpu->drq = s->dma->drq; |
1663 | afbb5194 | balrog | |
1664 | afbb5194 | balrog | return s->dma;
|
1665 | b4e3104b | balrog | } |
1666 | b4e3104b | balrog | |
1667 | 827df9f3 | balrog | static void omap_dma_interrupts_4_update(struct omap_dma_s *s) |
1668 | 827df9f3 | balrog | { |
1669 | 827df9f3 | balrog | struct omap_dma_channel_s *ch = s->ch;
|
1670 | 827df9f3 | balrog | uint32_t bmp, bit; |
1671 | 827df9f3 | balrog | |
1672 | 827df9f3 | balrog | for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1) |
1673 | 827df9f3 | balrog | if (ch->status) {
|
1674 | 827df9f3 | balrog | bmp |= bit; |
1675 | 827df9f3 | balrog | ch->cstatus |= ch->status; |
1676 | 827df9f3 | balrog | ch->status = 0;
|
1677 | 827df9f3 | balrog | } |
1678 | 827df9f3 | balrog | if ((s->irqstat[0] |= s->irqen[0] & bmp)) |
1679 | 827df9f3 | balrog | qemu_irq_raise(s->irq[0]);
|
1680 | 827df9f3 | balrog | if ((s->irqstat[1] |= s->irqen[1] & bmp)) |
1681 | 827df9f3 | balrog | qemu_irq_raise(s->irq[1]);
|
1682 | 827df9f3 | balrog | if ((s->irqstat[2] |= s->irqen[2] & bmp)) |
1683 | 827df9f3 | balrog | qemu_irq_raise(s->irq[2]);
|
1684 | 827df9f3 | balrog | if ((s->irqstat[3] |= s->irqen[3] & bmp)) |
1685 | 827df9f3 | balrog | qemu_irq_raise(s->irq[3]);
|
1686 | 827df9f3 | balrog | } |
1687 | 827df9f3 | balrog | |
1688 | 827df9f3 | balrog | static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr) |
1689 | 827df9f3 | balrog | { |
1690 | 827df9f3 | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1691 | 8da3ff18 | pbrook | int irqn = 0, chnum; |
1692 | 827df9f3 | balrog | struct omap_dma_channel_s *ch;
|
1693 | 827df9f3 | balrog | |
1694 | 8da3ff18 | pbrook | switch (addr) {
|
1695 | 827df9f3 | balrog | case 0x00: /* DMA4_REVISION */ |
1696 | 827df9f3 | balrog | return 0x40; |
1697 | 827df9f3 | balrog | |
1698 | 827df9f3 | balrog | case 0x14: /* DMA4_IRQSTATUS_L3 */ |
1699 | 827df9f3 | balrog | irqn ++; |
1700 | 827df9f3 | balrog | case 0x10: /* DMA4_IRQSTATUS_L2 */ |
1701 | 827df9f3 | balrog | irqn ++; |
1702 | 827df9f3 | balrog | case 0x0c: /* DMA4_IRQSTATUS_L1 */ |
1703 | 827df9f3 | balrog | irqn ++; |
1704 | 827df9f3 | balrog | case 0x08: /* DMA4_IRQSTATUS_L0 */ |
1705 | 827df9f3 | balrog | return s->irqstat[irqn];
|
1706 | 827df9f3 | balrog | |
1707 | 827df9f3 | balrog | case 0x24: /* DMA4_IRQENABLE_L3 */ |
1708 | 827df9f3 | balrog | irqn ++; |
1709 | 827df9f3 | balrog | case 0x20: /* DMA4_IRQENABLE_L2 */ |
1710 | 827df9f3 | balrog | irqn ++; |
1711 | 827df9f3 | balrog | case 0x1c: /* DMA4_IRQENABLE_L1 */ |
1712 | 827df9f3 | balrog | irqn ++; |
1713 | 827df9f3 | balrog | case 0x18: /* DMA4_IRQENABLE_L0 */ |
1714 | 827df9f3 | balrog | return s->irqen[irqn];
|
1715 | 827df9f3 | balrog | |
1716 | 827df9f3 | balrog | case 0x28: /* DMA4_SYSSTATUS */ |
1717 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
1718 | 827df9f3 | balrog | |
1719 | 827df9f3 | balrog | case 0x2c: /* DMA4_OCP_SYSCONFIG */ |
1720 | 827df9f3 | balrog | return s->ocp;
|
1721 | 827df9f3 | balrog | |
1722 | 827df9f3 | balrog | case 0x64: /* DMA4_CAPS_0 */ |
1723 | 827df9f3 | balrog | return s->caps[0]; |
1724 | 827df9f3 | balrog | case 0x6c: /* DMA4_CAPS_2 */ |
1725 | 827df9f3 | balrog | return s->caps[2]; |
1726 | 827df9f3 | balrog | case 0x70: /* DMA4_CAPS_3 */ |
1727 | 827df9f3 | balrog | return s->caps[3]; |
1728 | 827df9f3 | balrog | case 0x74: /* DMA4_CAPS_4 */ |
1729 | 827df9f3 | balrog | return s->caps[4]; |
1730 | 827df9f3 | balrog | |
1731 | 827df9f3 | balrog | case 0x78: /* DMA4_GCR */ |
1732 | 827df9f3 | balrog | return s->gcr;
|
1733 | 827df9f3 | balrog | |
1734 | 827df9f3 | balrog | case 0x80 ... 0xfff: |
1735 | 8da3ff18 | pbrook | addr -= 0x80;
|
1736 | 8da3ff18 | pbrook | chnum = addr / 0x60;
|
1737 | 827df9f3 | balrog | ch = s->ch + chnum; |
1738 | 8da3ff18 | pbrook | addr -= chnum * 0x60;
|
1739 | 827df9f3 | balrog | break;
|
1740 | 827df9f3 | balrog | |
1741 | 827df9f3 | balrog | default:
|
1742 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1743 | 827df9f3 | balrog | return 0; |
1744 | 827df9f3 | balrog | } |
1745 | 827df9f3 | balrog | |
1746 | 827df9f3 | balrog | /* Per-channel registers */
|
1747 | 8da3ff18 | pbrook | switch (addr) {
|
1748 | 827df9f3 | balrog | case 0x00: /* DMA4_CCR */ |
1749 | 827df9f3 | balrog | return (ch->buf_disable << 25) | |
1750 | 827df9f3 | balrog | (ch->src_sync << 24) |
|
1751 | 827df9f3 | balrog | (ch->prefetch << 23) |
|
1752 | 827df9f3 | balrog | ((ch->sync & 0x60) << 14) | |
1753 | 827df9f3 | balrog | (ch->bs << 18) |
|
1754 | 827df9f3 | balrog | (ch->transparent_copy << 17) |
|
1755 | 827df9f3 | balrog | (ch->constant_fill << 16) |
|
1756 | 827df9f3 | balrog | (ch->mode[1] << 14) | |
1757 | 827df9f3 | balrog | (ch->mode[0] << 12) | |
1758 | 827df9f3 | balrog | (0 << 10) | (0 << 9) | |
1759 | 827df9f3 | balrog | (ch->suspend << 8) |
|
1760 | 827df9f3 | balrog | (ch->enable << 7) |
|
1761 | 827df9f3 | balrog | (ch->priority << 6) |
|
1762 | 827df9f3 | balrog | (ch->fs << 5) | (ch->sync & 0x1f); |
1763 | 827df9f3 | balrog | |
1764 | 827df9f3 | balrog | case 0x04: /* DMA4_CLNK_CTRL */ |
1765 | 827df9f3 | balrog | return (ch->link_enabled << 15) | ch->link_next_ch; |
1766 | 827df9f3 | balrog | |
1767 | 827df9f3 | balrog | case 0x08: /* DMA4_CICR */ |
1768 | 827df9f3 | balrog | return ch->interrupts;
|
1769 | 827df9f3 | balrog | |
1770 | 827df9f3 | balrog | case 0x0c: /* DMA4_CSR */ |
1771 | 827df9f3 | balrog | return ch->cstatus;
|
1772 | 827df9f3 | balrog | |
1773 | 827df9f3 | balrog | case 0x10: /* DMA4_CSDP */ |
1774 | 827df9f3 | balrog | return (ch->endian[0] << 21) | |
1775 | 827df9f3 | balrog | (ch->endian_lock[0] << 20) | |
1776 | 827df9f3 | balrog | (ch->endian[1] << 19) | |
1777 | 827df9f3 | balrog | (ch->endian_lock[1] << 18) | |
1778 | 827df9f3 | balrog | (ch->write_mode << 16) |
|
1779 | 827df9f3 | balrog | (ch->burst[1] << 14) | |
1780 | 827df9f3 | balrog | (ch->pack[1] << 13) | |
1781 | 827df9f3 | balrog | (ch->translate[1] << 9) | |
1782 | 827df9f3 | balrog | (ch->burst[0] << 7) | |
1783 | 827df9f3 | balrog | (ch->pack[0] << 6) | |
1784 | 827df9f3 | balrog | (ch->translate[0] << 2) | |
1785 | 827df9f3 | balrog | (ch->data_type >> 1);
|
1786 | 827df9f3 | balrog | |
1787 | 827df9f3 | balrog | case 0x14: /* DMA4_CEN */ |
1788 | 827df9f3 | balrog | return ch->elements;
|
1789 | 827df9f3 | balrog | |
1790 | 827df9f3 | balrog | case 0x18: /* DMA4_CFN */ |
1791 | 827df9f3 | balrog | return ch->frames;
|
1792 | 827df9f3 | balrog | |
1793 | 827df9f3 | balrog | case 0x1c: /* DMA4_CSSA */ |
1794 | 827df9f3 | balrog | return ch->addr[0]; |
1795 | 827df9f3 | balrog | |
1796 | 827df9f3 | balrog | case 0x20: /* DMA4_CDSA */ |
1797 | 827df9f3 | balrog | return ch->addr[1]; |
1798 | 827df9f3 | balrog | |
1799 | 827df9f3 | balrog | case 0x24: /* DMA4_CSEI */ |
1800 | 827df9f3 | balrog | return ch->element_index[0]; |
1801 | 827df9f3 | balrog | |
1802 | 827df9f3 | balrog | case 0x28: /* DMA4_CSFI */ |
1803 | 827df9f3 | balrog | return ch->frame_index[0]; |
1804 | 827df9f3 | balrog | |
1805 | 827df9f3 | balrog | case 0x2c: /* DMA4_CDEI */ |
1806 | 827df9f3 | balrog | return ch->element_index[1]; |
1807 | 827df9f3 | balrog | |
1808 | 827df9f3 | balrog | case 0x30: /* DMA4_CDFI */ |
1809 | 827df9f3 | balrog | return ch->frame_index[1]; |
1810 | 827df9f3 | balrog | |
1811 | 827df9f3 | balrog | case 0x34: /* DMA4_CSAC */ |
1812 | 827df9f3 | balrog | return ch->active_set.src & 0xffff; |
1813 | 827df9f3 | balrog | |
1814 | 827df9f3 | balrog | case 0x38: /* DMA4_CDAC */ |
1815 | 827df9f3 | balrog | return ch->active_set.dest & 0xffff; |
1816 | 827df9f3 | balrog | |
1817 | 827df9f3 | balrog | case 0x3c: /* DMA4_CCEN */ |
1818 | 827df9f3 | balrog | return ch->active_set.element;
|
1819 | 827df9f3 | balrog | |
1820 | 827df9f3 | balrog | case 0x40: /* DMA4_CCFN */ |
1821 | 827df9f3 | balrog | return ch->active_set.frame;
|
1822 | 827df9f3 | balrog | |
1823 | 827df9f3 | balrog | case 0x44: /* DMA4_COLOR */ |
1824 | 827df9f3 | balrog | /* XXX only in sDMA */
|
1825 | 827df9f3 | balrog | return ch->color;
|
1826 | 827df9f3 | balrog | |
1827 | 827df9f3 | balrog | default:
|
1828 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1829 | 827df9f3 | balrog | return 0; |
1830 | 827df9f3 | balrog | } |
1831 | 827df9f3 | balrog | } |
1832 | 827df9f3 | balrog | |
1833 | 827df9f3 | balrog | static void omap_dma4_write(void *opaque, target_phys_addr_t addr, |
1834 | 827df9f3 | balrog | uint32_t value) |
1835 | 827df9f3 | balrog | { |
1836 | 827df9f3 | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1837 | 8da3ff18 | pbrook | int chnum, irqn = 0; |
1838 | 827df9f3 | balrog | struct omap_dma_channel_s *ch;
|
1839 | 827df9f3 | balrog | |
1840 | 8da3ff18 | pbrook | switch (addr) {
|
1841 | 827df9f3 | balrog | case 0x14: /* DMA4_IRQSTATUS_L3 */ |
1842 | 827df9f3 | balrog | irqn ++; |
1843 | 827df9f3 | balrog | case 0x10: /* DMA4_IRQSTATUS_L2 */ |
1844 | 827df9f3 | balrog | irqn ++; |
1845 | 827df9f3 | balrog | case 0x0c: /* DMA4_IRQSTATUS_L1 */ |
1846 | 827df9f3 | balrog | irqn ++; |
1847 | 827df9f3 | balrog | case 0x08: /* DMA4_IRQSTATUS_L0 */ |
1848 | 827df9f3 | balrog | s->irqstat[irqn] &= ~value; |
1849 | 827df9f3 | balrog | if (!s->irqstat[irqn])
|
1850 | 827df9f3 | balrog | qemu_irq_lower(s->irq[irqn]); |
1851 | 827df9f3 | balrog | return;
|
1852 | 827df9f3 | balrog | |
1853 | 827df9f3 | balrog | case 0x24: /* DMA4_IRQENABLE_L3 */ |
1854 | 827df9f3 | balrog | irqn ++; |
1855 | 827df9f3 | balrog | case 0x20: /* DMA4_IRQENABLE_L2 */ |
1856 | 827df9f3 | balrog | irqn ++; |
1857 | 827df9f3 | balrog | case 0x1c: /* DMA4_IRQENABLE_L1 */ |
1858 | 827df9f3 | balrog | irqn ++; |
1859 | 827df9f3 | balrog | case 0x18: /* DMA4_IRQENABLE_L0 */ |
1860 | 827df9f3 | balrog | s->irqen[irqn] = value; |
1861 | 827df9f3 | balrog | return;
|
1862 | 827df9f3 | balrog | |
1863 | 827df9f3 | balrog | case 0x2c: /* DMA4_OCP_SYSCONFIG */ |
1864 | 827df9f3 | balrog | if (value & 2) /* SOFTRESET */ |
1865 | afbb5194 | balrog | omap_dma_reset(s->dma); |
1866 | 827df9f3 | balrog | s->ocp = value & 0x3321;
|
1867 | 827df9f3 | balrog | if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */ |
1868 | 827df9f3 | balrog | fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__);
|
1869 | 827df9f3 | balrog | return;
|
1870 | 827df9f3 | balrog | |
1871 | 827df9f3 | balrog | case 0x78: /* DMA4_GCR */ |
1872 | 827df9f3 | balrog | s->gcr = value & 0x00ff00ff;
|
1873 | 827df9f3 | balrog | if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */ |
1874 | 827df9f3 | balrog | fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__);
|
1875 | 827df9f3 | balrog | return;
|
1876 | 827df9f3 | balrog | |
1877 | 827df9f3 | balrog | case 0x80 ... 0xfff: |
1878 | 8da3ff18 | pbrook | addr -= 0x80;
|
1879 | 8da3ff18 | pbrook | chnum = addr / 0x60;
|
1880 | 827df9f3 | balrog | ch = s->ch + chnum; |
1881 | 8da3ff18 | pbrook | addr -= chnum * 0x60;
|
1882 | 827df9f3 | balrog | break;
|
1883 | 827df9f3 | balrog | |
1884 | 827df9f3 | balrog | case 0x00: /* DMA4_REVISION */ |
1885 | 827df9f3 | balrog | case 0x28: /* DMA4_SYSSTATUS */ |
1886 | 827df9f3 | balrog | case 0x64: /* DMA4_CAPS_0 */ |
1887 | 827df9f3 | balrog | case 0x6c: /* DMA4_CAPS_2 */ |
1888 | 827df9f3 | balrog | case 0x70: /* DMA4_CAPS_3 */ |
1889 | 827df9f3 | balrog | case 0x74: /* DMA4_CAPS_4 */ |
1890 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
1891 | 827df9f3 | balrog | return;
|
1892 | 827df9f3 | balrog | |
1893 | 827df9f3 | balrog | default:
|
1894 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1895 | 827df9f3 | balrog | return;
|
1896 | 827df9f3 | balrog | } |
1897 | 827df9f3 | balrog | |
1898 | 827df9f3 | balrog | /* Per-channel registers */
|
1899 | 8da3ff18 | pbrook | switch (addr) {
|
1900 | 827df9f3 | balrog | case 0x00: /* DMA4_CCR */ |
1901 | 827df9f3 | balrog | ch->buf_disable = (value >> 25) & 1; |
1902 | 827df9f3 | balrog | ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */ |
1903 | 827df9f3 | balrog | if (ch->buf_disable && !ch->src_sync)
|
1904 | 827df9f3 | balrog | fprintf(stderr, "%s: Buffering disable is not allowed in "
|
1905 | 827df9f3 | balrog | "destination synchronised mode\n", __FUNCTION__);
|
1906 | 827df9f3 | balrog | ch->prefetch = (value >> 23) & 1; |
1907 | 827df9f3 | balrog | ch->bs = (value >> 18) & 1; |
1908 | 827df9f3 | balrog | ch->transparent_copy = (value >> 17) & 1; |
1909 | 827df9f3 | balrog | ch->constant_fill = (value >> 16) & 1; |
1910 | 827df9f3 | balrog | ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
1911 | 827df9f3 | balrog | ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
1912 | 827df9f3 | balrog | ch->suspend = (value & 0x0100) >> 8; |
1913 | 827df9f3 | balrog | ch->priority = (value & 0x0040) >> 6; |
1914 | 827df9f3 | balrog | ch->fs = (value & 0x0020) >> 5; |
1915 | 827df9f3 | balrog | if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) |
1916 | 827df9f3 | balrog | fprintf(stderr, "%s: For a packet transfer at least one port "
|
1917 | 827df9f3 | balrog | "must be constant-addressed\n", __FUNCTION__);
|
1918 | 827df9f3 | balrog | ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060); |
1919 | 827df9f3 | balrog | /* XXX must be 0x01 for CamDMA */
|
1920 | 827df9f3 | balrog | |
1921 | 827df9f3 | balrog | if (value & 0x0080) |
1922 | 827df9f3 | balrog | omap_dma_enable_channel(s, ch); |
1923 | 827df9f3 | balrog | else
|
1924 | 827df9f3 | balrog | omap_dma_disable_channel(s, ch); |
1925 | 827df9f3 | balrog | |
1926 | 827df9f3 | balrog | break;
|
1927 | 827df9f3 | balrog | |
1928 | 827df9f3 | balrog | case 0x04: /* DMA4_CLNK_CTRL */ |
1929 | 827df9f3 | balrog | ch->link_enabled = (value >> 15) & 0x1; |
1930 | 827df9f3 | balrog | ch->link_next_ch = value & 0x1f;
|
1931 | 827df9f3 | balrog | break;
|
1932 | 827df9f3 | balrog | |
1933 | 827df9f3 | balrog | case 0x08: /* DMA4_CICR */ |
1934 | 827df9f3 | balrog | ch->interrupts = value & 0x09be;
|
1935 | 827df9f3 | balrog | break;
|
1936 | 827df9f3 | balrog | |
1937 | 827df9f3 | balrog | case 0x0c: /* DMA4_CSR */ |
1938 | 827df9f3 | balrog | ch->cstatus &= ~value; |
1939 | 827df9f3 | balrog | break;
|
1940 | 827df9f3 | balrog | |
1941 | 827df9f3 | balrog | case 0x10: /* DMA4_CSDP */ |
1942 | 827df9f3 | balrog | ch->endian[0] =(value >> 21) & 1; |
1943 | 827df9f3 | balrog | ch->endian_lock[0] =(value >> 20) & 1; |
1944 | 827df9f3 | balrog | ch->endian[1] =(value >> 19) & 1; |
1945 | 827df9f3 | balrog | ch->endian_lock[1] =(value >> 18) & 1; |
1946 | 827df9f3 | balrog | if (ch->endian[0] != ch->endian[1]) |
1947 | afbb5194 | balrog | fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n",
|
1948 | 827df9f3 | balrog | __FUNCTION__); |
1949 | 827df9f3 | balrog | ch->write_mode = (value >> 16) & 3; |
1950 | 827df9f3 | balrog | ch->burst[1] = (value & 0xc000) >> 14; |
1951 | 827df9f3 | balrog | ch->pack[1] = (value & 0x2000) >> 13; |
1952 | 827df9f3 | balrog | ch->translate[1] = (value & 0x1e00) >> 9; |
1953 | 827df9f3 | balrog | ch->burst[0] = (value & 0x0180) >> 7; |
1954 | 827df9f3 | balrog | ch->pack[0] = (value & 0x0040) >> 6; |
1955 | 827df9f3 | balrog | ch->translate[0] = (value & 0x003c) >> 2; |
1956 | 827df9f3 | balrog | if (ch->translate[0] | ch->translate[1]) |
1957 | 827df9f3 | balrog | fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",
|
1958 | 827df9f3 | balrog | __FUNCTION__); |
1959 | 827df9f3 | balrog | ch->data_type = 1 << (value & 3); |
1960 | 827df9f3 | balrog | if ((value & 3) == 3) |
1961 | 827df9f3 | balrog | printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
|
1962 | 827df9f3 | balrog | break;
|
1963 | 827df9f3 | balrog | |
1964 | 827df9f3 | balrog | case 0x14: /* DMA4_CEN */ |
1965 | afbb5194 | balrog | ch->set_update = 1;
|
1966 | 827df9f3 | balrog | ch->elements = value & 0xffffff;
|
1967 | 827df9f3 | balrog | break;
|
1968 | 827df9f3 | balrog | |
1969 | 827df9f3 | balrog | case 0x18: /* DMA4_CFN */ |
1970 | 827df9f3 | balrog | ch->frames = value & 0xffff;
|
1971 | afbb5194 | balrog | ch->set_update = 1;
|
1972 | 827df9f3 | balrog | break;
|
1973 | 827df9f3 | balrog | |
1974 | 827df9f3 | balrog | case 0x1c: /* DMA4_CSSA */ |
1975 | 827df9f3 | balrog | ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
|
1976 | afbb5194 | balrog | ch->set_update = 1;
|
1977 | 827df9f3 | balrog | break;
|
1978 | 827df9f3 | balrog | |
1979 | 827df9f3 | balrog | case 0x20: /* DMA4_CDSA */ |
1980 | 827df9f3 | balrog | ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
|
1981 | afbb5194 | balrog | ch->set_update = 1;
|
1982 | 827df9f3 | balrog | break;
|
1983 | 827df9f3 | balrog | |
1984 | 827df9f3 | balrog | case 0x24: /* DMA4_CSEI */ |
1985 | 827df9f3 | balrog | ch->element_index[0] = (int16_t) value;
|
1986 | afbb5194 | balrog | ch->set_update = 1;
|
1987 | 827df9f3 | balrog | break;
|
1988 | 827df9f3 | balrog | |
1989 | 827df9f3 | balrog | case 0x28: /* DMA4_CSFI */ |
1990 | 827df9f3 | balrog | ch->frame_index[0] = (int32_t) value;
|
1991 | afbb5194 | balrog | ch->set_update = 1;
|
1992 | 827df9f3 | balrog | break;
|
1993 | 827df9f3 | balrog | |
1994 | 827df9f3 | balrog | case 0x2c: /* DMA4_CDEI */ |
1995 | 827df9f3 | balrog | ch->element_index[1] = (int16_t) value;
|
1996 | afbb5194 | balrog | ch->set_update = 1;
|
1997 | 827df9f3 | balrog | break;
|
1998 | 827df9f3 | balrog | |
1999 | 827df9f3 | balrog | case 0x30: /* DMA4_CDFI */ |
2000 | 827df9f3 | balrog | ch->frame_index[1] = (int32_t) value;
|
2001 | afbb5194 | balrog | ch->set_update = 1;
|
2002 | 827df9f3 | balrog | break;
|
2003 | 827df9f3 | balrog | |
2004 | 827df9f3 | balrog | case 0x44: /* DMA4_COLOR */ |
2005 | 827df9f3 | balrog | /* XXX only in sDMA */
|
2006 | 827df9f3 | balrog | ch->color = value; |
2007 | 827df9f3 | balrog | break;
|
2008 | 827df9f3 | balrog | |
2009 | 827df9f3 | balrog | case 0x34: /* DMA4_CSAC */ |
2010 | 827df9f3 | balrog | case 0x38: /* DMA4_CDAC */ |
2011 | 827df9f3 | balrog | case 0x3c: /* DMA4_CCEN */ |
2012 | 827df9f3 | balrog | case 0x40: /* DMA4_CCFN */ |
2013 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
2014 | 827df9f3 | balrog | break;
|
2015 | 827df9f3 | balrog | |
2016 | 827df9f3 | balrog | default:
|
2017 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2018 | 827df9f3 | balrog | } |
2019 | 827df9f3 | balrog | } |
2020 | 827df9f3 | balrog | |
2021 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_dma4_readfn[] = {
|
2022 | 827df9f3 | balrog | omap_badwidth_read16, |
2023 | 827df9f3 | balrog | omap_dma4_read, |
2024 | 827df9f3 | balrog | omap_dma4_read, |
2025 | 827df9f3 | balrog | }; |
2026 | 827df9f3 | balrog | |
2027 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_dma4_writefn[] = {
|
2028 | 827df9f3 | balrog | omap_badwidth_write16, |
2029 | 827df9f3 | balrog | omap_dma4_write, |
2030 | 827df9f3 | balrog | omap_dma4_write, |
2031 | 827df9f3 | balrog | }; |
2032 | 827df9f3 | balrog | |
2033 | afbb5194 | balrog | struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
|
2034 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu, int fifo, |
2035 | 827df9f3 | balrog | int chans, omap_clk iclk, omap_clk fclk)
|
2036 | 827df9f3 | balrog | { |
2037 | afbb5194 | balrog | int iomemtype, i;
|
2038 | 827df9f3 | balrog | struct omap_dma_s *s = (struct omap_dma_s *) |
2039 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_dma_s)); |
2040 | 827df9f3 | balrog | |
2041 | 827df9f3 | balrog | s->model = omap_dma_4; |
2042 | 827df9f3 | balrog | s->chans = chans; |
2043 | 827df9f3 | balrog | s->mpu = mpu; |
2044 | 827df9f3 | balrog | s->clk = fclk; |
2045 | afbb5194 | balrog | |
2046 | afbb5194 | balrog | s->dma = soc_dma_init(s->chans); |
2047 | afbb5194 | balrog | s->dma->freq = omap_clk_getrate(fclk); |
2048 | afbb5194 | balrog | s->dma->transfer_fn = omap_dma_transfer_generic; |
2049 | afbb5194 | balrog | s->dma->setup_fn = omap_dma_transfer_setup; |
2050 | afbb5194 | balrog | s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64);
|
2051 | afbb5194 | balrog | s->dma->opaque = s; |
2052 | afbb5194 | balrog | for (i = 0; i < s->chans; i ++) { |
2053 | afbb5194 | balrog | s->ch[i].dma = &s->dma->ch[i]; |
2054 | afbb5194 | balrog | s->dma->ch[i].opaque = &s->ch[i]; |
2055 | afbb5194 | balrog | } |
2056 | afbb5194 | balrog | |
2057 | 827df9f3 | balrog | memcpy(&s->irq, irqs, sizeof(s->irq));
|
2058 | 827df9f3 | balrog | s->intr_update = omap_dma_interrupts_4_update; |
2059 | afbb5194 | balrog | |
2060 | 827df9f3 | balrog | omap_dma_setcaps(s); |
2061 | 827df9f3 | balrog | omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
2062 | afbb5194 | balrog | omap_dma_reset(s->dma); |
2063 | afbb5194 | balrog | omap_dma_clk_update(s, 0, !!s->dma->freq);
|
2064 | 827df9f3 | balrog | |
2065 | 827df9f3 | balrog | iomemtype = cpu_register_io_memory(0, omap_dma4_readfn,
|
2066 | 827df9f3 | balrog | omap_dma4_writefn, s); |
2067 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x1000, iomemtype);
|
2068 | 827df9f3 | balrog | |
2069 | afbb5194 | balrog | mpu->drq = s->dma->drq; |
2070 | afbb5194 | balrog | |
2071 | afbb5194 | balrog | return s->dma;
|
2072 | 827df9f3 | balrog | } |
2073 | 827df9f3 | balrog | |
2074 | afbb5194 | balrog | struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma) |
2075 | b4e3104b | balrog | { |
2076 | afbb5194 | balrog | struct omap_dma_s *s = dma->opaque;
|
2077 | afbb5194 | balrog | |
2078 | b4e3104b | balrog | return &s->lcd_ch;
|
2079 | b4e3104b | balrog | } |