root / target-ppc / machine.c @ e3b42536
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#include "hw/hw.h" |
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#include "hw/boards.h" |
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void register_machines(void) |
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{
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qemu_register_machine(&heathrow_machine); |
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qemu_register_machine(&core99_machine); |
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qemu_register_machine(&prep_machine); |
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qemu_register_machine(&ref405ep_machine); |
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qemu_register_machine(&taihu_machine); |
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qemu_register_machine(&bamboo_machine); |
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qemu_register_machine(&mpc8544ds_machine); |
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} |
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void cpu_save(QEMUFile *f, void *opaque) |
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{
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CPUState *env = (CPUState *)opaque; |
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unsigned int i, j; |
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|
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for (i = 0; i < 32; i++) |
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qemu_put_betls(f, &env->gpr[i]); |
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#if !defined(TARGET_PPC64)
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for (i = 0; i < 32; i++) |
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qemu_put_betls(f, &env->gprh[i]); |
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#endif
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qemu_put_betls(f, &env->lr); |
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qemu_put_betls(f, &env->ctr); |
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for (i = 0; i < 8; i++) |
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qemu_put_be32s(f, &env->crf[i]); |
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qemu_put_betls(f, &env->xer); |
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qemu_put_betls(f, &env->reserve); |
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qemu_put_betls(f, &env->msr); |
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for (i = 0; i < 4; i++) |
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qemu_put_betls(f, &env->tgpr[i]); |
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for (i = 0; i < 32; i++) { |
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union {
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float64 d; |
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uint64_t l; |
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} u; |
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u.d = env->fpr[i]; |
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qemu_put_be64(f, u.l); |
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} |
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qemu_put_be32s(f, &env->fpscr); |
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qemu_put_sbe32s(f, &env->access_type); |
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#if !defined(CONFIG_USER_ONLY)
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#if defined(TARGET_PPC64)
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qemu_put_betls(f, &env->asr); |
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qemu_put_sbe32s(f, &env->slb_nr); |
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#endif
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qemu_put_betls(f, &env->sdr1); |
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for (i = 0; i < 32; i++) |
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qemu_put_betls(f, &env->sr[i]); |
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for (i = 0; i < 2; i++) |
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for (j = 0; j < 8; j++) |
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qemu_put_betls(f, &env->DBAT[i][j]); |
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for (i = 0; i < 2; i++) |
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for (j = 0; j < 8; j++) |
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qemu_put_betls(f, &env->IBAT[i][j]); |
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qemu_put_sbe32s(f, &env->nb_tlb); |
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qemu_put_sbe32s(f, &env->tlb_per_way); |
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qemu_put_sbe32s(f, &env->nb_ways); |
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qemu_put_sbe32s(f, &env->last_way); |
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qemu_put_sbe32s(f, &env->id_tlbs); |
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qemu_put_sbe32s(f, &env->nb_pids); |
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if (env->tlb) {
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// XXX assumes 6xx
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for (i = 0; i < env->nb_tlb; i++) { |
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qemu_put_betls(f, &env->tlb[i].tlb6.pte0); |
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qemu_put_betls(f, &env->tlb[i].tlb6.pte1); |
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qemu_put_betls(f, &env->tlb[i].tlb6.EPN); |
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} |
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} |
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for (i = 0; i < 4; i++) |
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qemu_put_betls(f, &env->pb[i]); |
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#endif
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for (i = 0; i < 1024; i++) |
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qemu_put_betls(f, &env->spr[i]); |
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qemu_put_be32s(f, &env->vscr); |
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qemu_put_be64s(f, &env->spe_acc); |
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qemu_put_be32s(f, &env->spe_fscr); |
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qemu_put_betls(f, &env->msr_mask); |
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qemu_put_be32s(f, &env->flags); |
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qemu_put_sbe32s(f, &env->error_code); |
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qemu_put_be32s(f, &env->pending_interrupts); |
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#if !defined(CONFIG_USER_ONLY)
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qemu_put_be32s(f, &env->irq_input_state); |
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for (i = 0; i < POWERPC_EXCP_NB; i++) |
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qemu_put_betls(f, &env->excp_vectors[i]); |
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qemu_put_betls(f, &env->excp_prefix); |
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qemu_put_betls(f, &env->hreset_excp_prefix); |
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qemu_put_betls(f, &env->ivor_mask); |
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qemu_put_betls(f, &env->ivpr_mask); |
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qemu_put_betls(f, &env->hreset_vector); |
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#endif
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qemu_put_betls(f, &env->nip); |
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qemu_put_betls(f, &env->hflags); |
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qemu_put_betls(f, &env->hflags_nmsr); |
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qemu_put_sbe32s(f, &env->mmu_idx); |
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qemu_put_sbe32s(f, &env->power_mode); |
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} |
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int cpu_load(QEMUFile *f, void *opaque, int version_id) |
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{
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CPUState *env = (CPUState *)opaque; |
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unsigned int i, j; |
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|
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for (i = 0; i < 32; i++) |
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qemu_get_betls(f, &env->gpr[i]); |
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#if !defined(TARGET_PPC64)
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for (i = 0; i < 32; i++) |
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qemu_get_betls(f, &env->gprh[i]); |
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#endif
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qemu_get_betls(f, &env->lr); |
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qemu_get_betls(f, &env->ctr); |
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for (i = 0; i < 8; i++) |
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qemu_get_be32s(f, &env->crf[i]); |
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qemu_get_betls(f, &env->xer); |
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qemu_get_betls(f, &env->reserve); |
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qemu_get_betls(f, &env->msr); |
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for (i = 0; i < 4; i++) |
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qemu_get_betls(f, &env->tgpr[i]); |
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for (i = 0; i < 32; i++) { |
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union {
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float64 d; |
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uint64_t l; |
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} u; |
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u.l = qemu_get_be64(f); |
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env->fpr[i] = u.d; |
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} |
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qemu_get_be32s(f, &env->fpscr); |
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qemu_get_sbe32s(f, &env->access_type); |
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#if !defined(CONFIG_USER_ONLY)
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#if defined(TARGET_PPC64)
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qemu_get_betls(f, &env->asr); |
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qemu_get_sbe32s(f, &env->slb_nr); |
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#endif
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qemu_get_betls(f, &env->sdr1); |
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for (i = 0; i < 32; i++) |
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qemu_get_betls(f, &env->sr[i]); |
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for (i = 0; i < 2; i++) |
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for (j = 0; j < 8; j++) |
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qemu_get_betls(f, &env->DBAT[i][j]); |
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for (i = 0; i < 2; i++) |
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for (j = 0; j < 8; j++) |
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qemu_get_betls(f, &env->IBAT[i][j]); |
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qemu_get_sbe32s(f, &env->nb_tlb); |
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qemu_get_sbe32s(f, &env->tlb_per_way); |
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qemu_get_sbe32s(f, &env->nb_ways); |
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qemu_get_sbe32s(f, &env->last_way); |
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qemu_get_sbe32s(f, &env->id_tlbs); |
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qemu_get_sbe32s(f, &env->nb_pids); |
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if (env->tlb) {
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// XXX assumes 6xx
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for (i = 0; i < env->nb_tlb; i++) { |
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qemu_get_betls(f, &env->tlb[i].tlb6.pte0); |
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qemu_get_betls(f, &env->tlb[i].tlb6.pte1); |
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qemu_get_betls(f, &env->tlb[i].tlb6.EPN); |
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} |
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} |
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for (i = 0; i < 4; i++) |
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qemu_get_betls(f, &env->pb[i]); |
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#endif
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for (i = 0; i < 1024; i++) |
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qemu_get_betls(f, &env->spr[i]); |
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qemu_get_be32s(f, &env->vscr); |
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qemu_get_be64s(f, &env->spe_acc); |
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qemu_get_be32s(f, &env->spe_fscr); |
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qemu_get_betls(f, &env->msr_mask); |
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qemu_get_be32s(f, &env->flags); |
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qemu_get_sbe32s(f, &env->error_code); |
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qemu_get_be32s(f, &env->pending_interrupts); |
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#if !defined(CONFIG_USER_ONLY)
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qemu_get_be32s(f, &env->irq_input_state); |
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for (i = 0; i < POWERPC_EXCP_NB; i++) |
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qemu_get_betls(f, &env->excp_vectors[i]); |
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qemu_get_betls(f, &env->excp_prefix); |
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qemu_get_betls(f, &env->hreset_excp_prefix); |
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qemu_get_betls(f, &env->ivor_mask); |
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qemu_get_betls(f, &env->ivpr_mask); |
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qemu_get_betls(f, &env->hreset_vector); |
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#endif
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qemu_get_betls(f, &env->nip); |
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qemu_get_betls(f, &env->hflags); |
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qemu_get_betls(f, &env->hflags_nmsr); |
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qemu_get_sbe32s(f, &env->mmu_idx); |
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qemu_get_sbe32s(f, &env->power_mode); |
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return 0; |
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} |