root / target-ppc / machine.c @ e3b42536
History | View | Annotate | Download (5.9 kB)
1 |
#include "hw/hw.h" |
---|---|
2 |
#include "hw/boards.h" |
3 |
|
4 |
void register_machines(void) |
5 |
{ |
6 |
qemu_register_machine(&heathrow_machine); |
7 |
qemu_register_machine(&core99_machine); |
8 |
qemu_register_machine(&prep_machine); |
9 |
qemu_register_machine(&ref405ep_machine); |
10 |
qemu_register_machine(&taihu_machine); |
11 |
qemu_register_machine(&bamboo_machine); |
12 |
qemu_register_machine(&mpc8544ds_machine); |
13 |
} |
14 |
|
15 |
void cpu_save(QEMUFile *f, void *opaque) |
16 |
{ |
17 |
CPUState *env = (CPUState *)opaque; |
18 |
unsigned int i, j; |
19 |
|
20 |
for (i = 0; i < 32; i++) |
21 |
qemu_put_betls(f, &env->gpr[i]); |
22 |
#if !defined(TARGET_PPC64)
|
23 |
for (i = 0; i < 32; i++) |
24 |
qemu_put_betls(f, &env->gprh[i]); |
25 |
#endif
|
26 |
qemu_put_betls(f, &env->lr); |
27 |
qemu_put_betls(f, &env->ctr); |
28 |
for (i = 0; i < 8; i++) |
29 |
qemu_put_be32s(f, &env->crf[i]); |
30 |
qemu_put_betls(f, &env->xer); |
31 |
qemu_put_betls(f, &env->reserve); |
32 |
qemu_put_betls(f, &env->msr); |
33 |
for (i = 0; i < 4; i++) |
34 |
qemu_put_betls(f, &env->tgpr[i]); |
35 |
for (i = 0; i < 32; i++) { |
36 |
union {
|
37 |
float64 d; |
38 |
uint64_t l; |
39 |
} u; |
40 |
u.d = env->fpr[i]; |
41 |
qemu_put_be64(f, u.l); |
42 |
} |
43 |
qemu_put_be32s(f, &env->fpscr); |
44 |
qemu_put_sbe32s(f, &env->access_type); |
45 |
#if !defined(CONFIG_USER_ONLY)
|
46 |
#if defined(TARGET_PPC64)
|
47 |
qemu_put_betls(f, &env->asr); |
48 |
qemu_put_sbe32s(f, &env->slb_nr); |
49 |
#endif
|
50 |
qemu_put_betls(f, &env->sdr1); |
51 |
for (i = 0; i < 32; i++) |
52 |
qemu_put_betls(f, &env->sr[i]); |
53 |
for (i = 0; i < 2; i++) |
54 |
for (j = 0; j < 8; j++) |
55 |
qemu_put_betls(f, &env->DBAT[i][j]); |
56 |
for (i = 0; i < 2; i++) |
57 |
for (j = 0; j < 8; j++) |
58 |
qemu_put_betls(f, &env->IBAT[i][j]); |
59 |
qemu_put_sbe32s(f, &env->nb_tlb); |
60 |
qemu_put_sbe32s(f, &env->tlb_per_way); |
61 |
qemu_put_sbe32s(f, &env->nb_ways); |
62 |
qemu_put_sbe32s(f, &env->last_way); |
63 |
qemu_put_sbe32s(f, &env->id_tlbs); |
64 |
qemu_put_sbe32s(f, &env->nb_pids); |
65 |
if (env->tlb) {
|
66 |
// XXX assumes 6xx
|
67 |
for (i = 0; i < env->nb_tlb; i++) { |
68 |
qemu_put_betls(f, &env->tlb[i].tlb6.pte0); |
69 |
qemu_put_betls(f, &env->tlb[i].tlb6.pte1); |
70 |
qemu_put_betls(f, &env->tlb[i].tlb6.EPN); |
71 |
} |
72 |
} |
73 |
for (i = 0; i < 4; i++) |
74 |
qemu_put_betls(f, &env->pb[i]); |
75 |
#endif
|
76 |
for (i = 0; i < 1024; i++) |
77 |
qemu_put_betls(f, &env->spr[i]); |
78 |
qemu_put_be32s(f, &env->vscr); |
79 |
qemu_put_be64s(f, &env->spe_acc); |
80 |
qemu_put_be32s(f, &env->spe_fscr); |
81 |
qemu_put_betls(f, &env->msr_mask); |
82 |
qemu_put_be32s(f, &env->flags); |
83 |
qemu_put_sbe32s(f, &env->error_code); |
84 |
qemu_put_be32s(f, &env->pending_interrupts); |
85 |
#if !defined(CONFIG_USER_ONLY)
|
86 |
qemu_put_be32s(f, &env->irq_input_state); |
87 |
for (i = 0; i < POWERPC_EXCP_NB; i++) |
88 |
qemu_put_betls(f, &env->excp_vectors[i]); |
89 |
qemu_put_betls(f, &env->excp_prefix); |
90 |
qemu_put_betls(f, &env->hreset_excp_prefix); |
91 |
qemu_put_betls(f, &env->ivor_mask); |
92 |
qemu_put_betls(f, &env->ivpr_mask); |
93 |
qemu_put_betls(f, &env->hreset_vector); |
94 |
#endif
|
95 |
qemu_put_betls(f, &env->nip); |
96 |
qemu_put_betls(f, &env->hflags); |
97 |
qemu_put_betls(f, &env->hflags_nmsr); |
98 |
qemu_put_sbe32s(f, &env->mmu_idx); |
99 |
qemu_put_sbe32s(f, &env->power_mode); |
100 |
} |
101 |
|
102 |
int cpu_load(QEMUFile *f, void *opaque, int version_id) |
103 |
{ |
104 |
CPUState *env = (CPUState *)opaque; |
105 |
unsigned int i, j; |
106 |
|
107 |
for (i = 0; i < 32; i++) |
108 |
qemu_get_betls(f, &env->gpr[i]); |
109 |
#if !defined(TARGET_PPC64)
|
110 |
for (i = 0; i < 32; i++) |
111 |
qemu_get_betls(f, &env->gprh[i]); |
112 |
#endif
|
113 |
qemu_get_betls(f, &env->lr); |
114 |
qemu_get_betls(f, &env->ctr); |
115 |
for (i = 0; i < 8; i++) |
116 |
qemu_get_be32s(f, &env->crf[i]); |
117 |
qemu_get_betls(f, &env->xer); |
118 |
qemu_get_betls(f, &env->reserve); |
119 |
qemu_get_betls(f, &env->msr); |
120 |
for (i = 0; i < 4; i++) |
121 |
qemu_get_betls(f, &env->tgpr[i]); |
122 |
for (i = 0; i < 32; i++) { |
123 |
union {
|
124 |
float64 d; |
125 |
uint64_t l; |
126 |
} u; |
127 |
u.l = qemu_get_be64(f); |
128 |
env->fpr[i] = u.d; |
129 |
} |
130 |
qemu_get_be32s(f, &env->fpscr); |
131 |
qemu_get_sbe32s(f, &env->access_type); |
132 |
#if !defined(CONFIG_USER_ONLY)
|
133 |
#if defined(TARGET_PPC64)
|
134 |
qemu_get_betls(f, &env->asr); |
135 |
qemu_get_sbe32s(f, &env->slb_nr); |
136 |
#endif
|
137 |
qemu_get_betls(f, &env->sdr1); |
138 |
for (i = 0; i < 32; i++) |
139 |
qemu_get_betls(f, &env->sr[i]); |
140 |
for (i = 0; i < 2; i++) |
141 |
for (j = 0; j < 8; j++) |
142 |
qemu_get_betls(f, &env->DBAT[i][j]); |
143 |
for (i = 0; i < 2; i++) |
144 |
for (j = 0; j < 8; j++) |
145 |
qemu_get_betls(f, &env->IBAT[i][j]); |
146 |
qemu_get_sbe32s(f, &env->nb_tlb); |
147 |
qemu_get_sbe32s(f, &env->tlb_per_way); |
148 |
qemu_get_sbe32s(f, &env->nb_ways); |
149 |
qemu_get_sbe32s(f, &env->last_way); |
150 |
qemu_get_sbe32s(f, &env->id_tlbs); |
151 |
qemu_get_sbe32s(f, &env->nb_pids); |
152 |
if (env->tlb) {
|
153 |
// XXX assumes 6xx
|
154 |
for (i = 0; i < env->nb_tlb; i++) { |
155 |
qemu_get_betls(f, &env->tlb[i].tlb6.pte0); |
156 |
qemu_get_betls(f, &env->tlb[i].tlb6.pte1); |
157 |
qemu_get_betls(f, &env->tlb[i].tlb6.EPN); |
158 |
} |
159 |
} |
160 |
for (i = 0; i < 4; i++) |
161 |
qemu_get_betls(f, &env->pb[i]); |
162 |
#endif
|
163 |
for (i = 0; i < 1024; i++) |
164 |
qemu_get_betls(f, &env->spr[i]); |
165 |
qemu_get_be32s(f, &env->vscr); |
166 |
qemu_get_be64s(f, &env->spe_acc); |
167 |
qemu_get_be32s(f, &env->spe_fscr); |
168 |
qemu_get_betls(f, &env->msr_mask); |
169 |
qemu_get_be32s(f, &env->flags); |
170 |
qemu_get_sbe32s(f, &env->error_code); |
171 |
qemu_get_be32s(f, &env->pending_interrupts); |
172 |
#if !defined(CONFIG_USER_ONLY)
|
173 |
qemu_get_be32s(f, &env->irq_input_state); |
174 |
for (i = 0; i < POWERPC_EXCP_NB; i++) |
175 |
qemu_get_betls(f, &env->excp_vectors[i]); |
176 |
qemu_get_betls(f, &env->excp_prefix); |
177 |
qemu_get_betls(f, &env->hreset_excp_prefix); |
178 |
qemu_get_betls(f, &env->ivor_mask); |
179 |
qemu_get_betls(f, &env->ivpr_mask); |
180 |
qemu_get_betls(f, &env->hreset_vector); |
181 |
#endif
|
182 |
qemu_get_betls(f, &env->nip); |
183 |
qemu_get_betls(f, &env->hflags); |
184 |
qemu_get_betls(f, &env->hflags_nmsr); |
185 |
qemu_get_sbe32s(f, &env->mmu_idx); |
186 |
qemu_get_sbe32s(f, &env->power_mode); |
187 |
|
188 |
return 0; |
189 |
} |