root / hw / mips_mipssim.c @ e3d7e843
History | View | Annotate | Download (6.4 kB)
1 | f0fc6f8f | ths | /*
|
---|---|---|---|
2 | f0fc6f8f | ths | * QEMU/mipssim emulation
|
3 | f0fc6f8f | ths | *
|
4 | f0fc6f8f | ths | * Emulates a very simple machine model similiar to the one use by the
|
5 | f0fc6f8f | ths | * proprietary MIPS emulator.
|
6 | a79ee211 | ths | *
|
7 | a79ee211 | ths | * Copyright (c) 2007 Thiemo Seufer
|
8 | a79ee211 | ths | *
|
9 | a79ee211 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
10 | a79ee211 | ths | * of this software and associated documentation files (the "Software"), to deal
|
11 | a79ee211 | ths | * in the Software without restriction, including without limitation the rights
|
12 | a79ee211 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
13 | a79ee211 | ths | * copies of the Software, and to permit persons to whom the Software is
|
14 | a79ee211 | ths | * furnished to do so, subject to the following conditions:
|
15 | a79ee211 | ths | *
|
16 | a79ee211 | ths | * The above copyright notice and this permission notice shall be included in
|
17 | a79ee211 | ths | * all copies or substantial portions of the Software.
|
18 | a79ee211 | ths | *
|
19 | a79ee211 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
20 | a79ee211 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
21 | a79ee211 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
22 | a79ee211 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
23 | a79ee211 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
24 | a79ee211 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
25 | a79ee211 | ths | * THE SOFTWARE.
|
26 | f0fc6f8f | ths | */
|
27 | f0fc6f8f | ths | #include "vl.h" |
28 | f0fc6f8f | ths | |
29 | f0fc6f8f | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
30 | f0fc6f8f | ths | #define BIOS_FILENAME "mips_bios.bin" |
31 | f0fc6f8f | ths | #else
|
32 | f0fc6f8f | ths | #define BIOS_FILENAME "mipsel_bios.bin" |
33 | f0fc6f8f | ths | #endif
|
34 | f0fc6f8f | ths | |
35 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
|
36 | f0fc6f8f | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL) |
37 | f0fc6f8f | ths | #else
|
38 | f0fc6f8f | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU) |
39 | f0fc6f8f | ths | #endif
|
40 | f0fc6f8f | ths | |
41 | f0fc6f8f | ths | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
42 | f0fc6f8f | ths | |
43 | 7df526e3 | ths | static struct _loaderparams { |
44 | 7df526e3 | ths | int ram_size;
|
45 | 7df526e3 | ths | const char *kernel_filename; |
46 | 7df526e3 | ths | const char *kernel_cmdline; |
47 | 7df526e3 | ths | const char *initrd_filename; |
48 | 7df526e3 | ths | } loaderparams; |
49 | 7df526e3 | ths | |
50 | f0fc6f8f | ths | static void load_kernel (CPUState *env) |
51 | f0fc6f8f | ths | { |
52 | f0fc6f8f | ths | int64_t entry, kernel_low, kernel_high; |
53 | f0fc6f8f | ths | long kernel_size;
|
54 | f0fc6f8f | ths | long initrd_size;
|
55 | f0fc6f8f | ths | ram_addr_t initrd_offset; |
56 | f0fc6f8f | ths | |
57 | 7df526e3 | ths | kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, |
58 | f0fc6f8f | ths | &entry, &kernel_low, &kernel_high); |
59 | f0fc6f8f | ths | if (kernel_size >= 0) { |
60 | f0fc6f8f | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
61 | f0fc6f8f | ths | entry = (int32_t)entry; |
62 | f0fc6f8f | ths | env->PC[env->current_tc] = entry; |
63 | f0fc6f8f | ths | } else {
|
64 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
65 | 7df526e3 | ths | loaderparams.kernel_filename); |
66 | f0fc6f8f | ths | exit(1);
|
67 | f0fc6f8f | ths | } |
68 | f0fc6f8f | ths | |
69 | f0fc6f8f | ths | /* load initrd */
|
70 | f0fc6f8f | ths | initrd_size = 0;
|
71 | f0fc6f8f | ths | initrd_offset = 0;
|
72 | 7df526e3 | ths | if (loaderparams.initrd_filename) {
|
73 | 7df526e3 | ths | initrd_size = get_image_size (loaderparams.initrd_filename); |
74 | f0fc6f8f | ths | if (initrd_size > 0) { |
75 | f0fc6f8f | ths | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
76 | 7df526e3 | ths | if (initrd_offset + initrd_size > loaderparams.ram_size) {
|
77 | f0fc6f8f | ths | fprintf(stderr, |
78 | f0fc6f8f | ths | "qemu: memory too small for initial ram disk '%s'\n",
|
79 | 7df526e3 | ths | loaderparams.initrd_filename); |
80 | f0fc6f8f | ths | exit(1);
|
81 | f0fc6f8f | ths | } |
82 | 7df526e3 | ths | initrd_size = load_image(loaderparams.initrd_filename, |
83 | f0fc6f8f | ths | phys_ram_base + initrd_offset); |
84 | f0fc6f8f | ths | } |
85 | f0fc6f8f | ths | if (initrd_size == (target_ulong) -1) { |
86 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
87 | 7df526e3 | ths | loaderparams.initrd_filename); |
88 | f0fc6f8f | ths | exit(1);
|
89 | f0fc6f8f | ths | } |
90 | f0fc6f8f | ths | } |
91 | f0fc6f8f | ths | } |
92 | f0fc6f8f | ths | |
93 | f0fc6f8f | ths | static void main_cpu_reset(void *opaque) |
94 | f0fc6f8f | ths | { |
95 | f0fc6f8f | ths | CPUState *env = opaque; |
96 | f0fc6f8f | ths | cpu_reset(env); |
97 | f0fc6f8f | ths | cpu_mips_register(env, NULL);
|
98 | f0fc6f8f | ths | |
99 | 7df526e3 | ths | if (loaderparams.kernel_filename)
|
100 | f0fc6f8f | ths | load_kernel (env); |
101 | f0fc6f8f | ths | } |
102 | f0fc6f8f | ths | |
103 | f0fc6f8f | ths | static void |
104 | 6ac0e82d | balrog | mips_mipssim_init (int ram_size, int vga_ram_size, const char *boot_device, |
105 | f0fc6f8f | ths | DisplayState *ds, const char **fd_filename, int snapshot, |
106 | f0fc6f8f | ths | const char *kernel_filename, const char *kernel_cmdline, |
107 | f0fc6f8f | ths | const char *initrd_filename, const char *cpu_model) |
108 | f0fc6f8f | ths | { |
109 | f0fc6f8f | ths | char buf[1024]; |
110 | f0fc6f8f | ths | unsigned long bios_offset; |
111 | f0fc6f8f | ths | CPUState *env; |
112 | b5334159 | ths | int bios_size;
|
113 | f0fc6f8f | ths | mips_def_t *def; |
114 | f0fc6f8f | ths | |
115 | f0fc6f8f | ths | /* Init CPUs. */
|
116 | f0fc6f8f | ths | if (cpu_model == NULL) { |
117 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
|
118 | f0fc6f8f | ths | cpu_model = "5Kf";
|
119 | f0fc6f8f | ths | #else
|
120 | f0fc6f8f | ths | cpu_model = "24Kf";
|
121 | f0fc6f8f | ths | #endif
|
122 | f0fc6f8f | ths | } |
123 | f0fc6f8f | ths | if (mips_find_by_name(cpu_model, &def) != 0) |
124 | f0fc6f8f | ths | def = NULL;
|
125 | f0fc6f8f | ths | env = cpu_init(); |
126 | f0fc6f8f | ths | cpu_mips_register(env, def); |
127 | f0fc6f8f | ths | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
128 | f0fc6f8f | ths | qemu_register_reset(main_cpu_reset, env); |
129 | f0fc6f8f | ths | |
130 | f0fc6f8f | ths | /* Allocate RAM. */
|
131 | f0fc6f8f | ths | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
132 | f0fc6f8f | ths | |
133 | f0fc6f8f | ths | /* Load a BIOS / boot exception handler image. */
|
134 | b5334159 | ths | bios_offset = ram_size + vga_ram_size; |
135 | f0fc6f8f | ths | if (bios_name == NULL) |
136 | f0fc6f8f | ths | bios_name = BIOS_FILENAME; |
137 | f0fc6f8f | ths | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
138 | b5334159 | ths | bios_size = load_image(buf, phys_ram_base + bios_offset); |
139 | b5334159 | ths | if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) { |
140 | f0fc6f8f | ths | /* Bail out if we have neither a kernel image nor boot vector code. */
|
141 | f0fc6f8f | ths | fprintf(stderr, |
142 | f0fc6f8f | ths | "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
|
143 | f0fc6f8f | ths | buf); |
144 | f0fc6f8f | ths | exit(1);
|
145 | f0fc6f8f | ths | } else {
|
146 | b5334159 | ths | /* Map the BIOS / boot exception handler. */
|
147 | f0fc6f8f | ths | cpu_register_physical_memory(0x1fc00000LL,
|
148 | b5334159 | ths | bios_size, bios_offset | IO_MEM_ROM); |
149 | b5334159 | ths | /* We have a boot vector start address. */
|
150 | b5334159 | ths | env->PC[env->current_tc] = (target_long)(int32_t)0xbfc00000;
|
151 | f0fc6f8f | ths | } |
152 | f0fc6f8f | ths | |
153 | f0fc6f8f | ths | if (kernel_filename) {
|
154 | 7df526e3 | ths | loaderparams.ram_size = ram_size; |
155 | 7df526e3 | ths | loaderparams.kernel_filename = kernel_filename; |
156 | 7df526e3 | ths | loaderparams.kernel_cmdline = kernel_cmdline; |
157 | 7df526e3 | ths | loaderparams.initrd_filename = initrd_filename; |
158 | f0fc6f8f | ths | load_kernel(env); |
159 | f0fc6f8f | ths | } |
160 | f0fc6f8f | ths | |
161 | f0fc6f8f | ths | /* Init CPU internal devices. */
|
162 | f0fc6f8f | ths | cpu_mips_irq_init_cpu(env); |
163 | f0fc6f8f | ths | cpu_mips_clock_init(env); |
164 | f0fc6f8f | ths | cpu_mips_irqctrl_init(); |
165 | f0fc6f8f | ths | |
166 | f0fc6f8f | ths | /* Register 64 KB of ISA IO space at 0x1fd00000. */
|
167 | f0fc6f8f | ths | isa_mmio_init(0x1fd00000, 0x00010000); |
168 | f0fc6f8f | ths | |
169 | f0fc6f8f | ths | /* A single 16450 sits at offset 0x3f8. It is attached to
|
170 | f0fc6f8f | ths | MIPS CPU INT2, which is interrupt 4. */
|
171 | f0fc6f8f | ths | if (serial_hds[0]) |
172 | f0fc6f8f | ths | serial_init(0x3f8, env->irq[4], serial_hds[0]); |
173 | f0fc6f8f | ths | |
174 | f0fc6f8f | ths | if (nd_table[0].vlan) { |
175 | f0fc6f8f | ths | if (nd_table[0].model == NULL |
176 | f0fc6f8f | ths | || strcmp(nd_table[0].model, "mipsnet") == 0) { |
177 | f0fc6f8f | ths | /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
|
178 | f0fc6f8f | ths | mipsnet_init(0x4200, env->irq[2], &nd_table[0]); |
179 | f0fc6f8f | ths | } else if (strcmp(nd_table[0].model, "?") == 0) { |
180 | f0fc6f8f | ths | fprintf(stderr, "qemu: Supported NICs: mipsnet\n");
|
181 | f0fc6f8f | ths | exit (1);
|
182 | f0fc6f8f | ths | } else {
|
183 | f0fc6f8f | ths | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
184 | f0fc6f8f | ths | exit (1);
|
185 | f0fc6f8f | ths | } |
186 | f0fc6f8f | ths | } |
187 | f0fc6f8f | ths | } |
188 | f0fc6f8f | ths | |
189 | f0fc6f8f | ths | QEMUMachine mips_mipssim_machine = { |
190 | f0fc6f8f | ths | "mipssim",
|
191 | f0fc6f8f | ths | "MIPS MIPSsim platform",
|
192 | f0fc6f8f | ths | mips_mipssim_init, |
193 | f0fc6f8f | ths | }; |