root / hw / omap_mmc.c @ e3d7e843
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1 | b30bb3a2 | balrog | /*
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2 | b30bb3a2 | balrog | * OMAP on-chip MMC/SD host emulation.
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3 | b30bb3a2 | balrog | *
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4 | b30bb3a2 | balrog | * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | b30bb3a2 | balrog | *
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6 | b30bb3a2 | balrog | * This program is free software; you can redistribute it and/or
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7 | b30bb3a2 | balrog | * modify it under the terms of the GNU General Public License as
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8 | b30bb3a2 | balrog | * published by the Free Software Foundation; either version 2 of
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9 | b30bb3a2 | balrog | * the License, or (at your option) any later version.
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10 | b30bb3a2 | balrog | *
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11 | b30bb3a2 | balrog | * This program is distributed in the hope that it will be useful,
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12 | b30bb3a2 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | b30bb3a2 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | b30bb3a2 | balrog | * GNU General Public License for more details.
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15 | b30bb3a2 | balrog | *
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16 | b30bb3a2 | balrog | * You should have received a copy of the GNU General Public License
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17 | b30bb3a2 | balrog | * along with this program; if not, write to the Free Software
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18 | b30bb3a2 | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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19 | b30bb3a2 | balrog | * MA 02111-1307 USA
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20 | b30bb3a2 | balrog | */
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21 | b30bb3a2 | balrog | #include "vl.h" |
22 | b30bb3a2 | balrog | #include "sd.h" |
23 | b30bb3a2 | balrog | |
24 | b30bb3a2 | balrog | struct omap_mmc_s {
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25 | b30bb3a2 | balrog | target_phys_addr_t base; |
26 | b30bb3a2 | balrog | qemu_irq irq; |
27 | b30bb3a2 | balrog | qemu_irq *dma; |
28 | 8e129e07 | balrog | qemu_irq handler[2];
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29 | b30bb3a2 | balrog | omap_clk clk; |
30 | b30bb3a2 | balrog | SDState *card; |
31 | b30bb3a2 | balrog | uint16_t last_cmd; |
32 | b30bb3a2 | balrog | uint16_t sdio; |
33 | b30bb3a2 | balrog | uint16_t rsp[8];
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34 | b30bb3a2 | balrog | uint32_t arg; |
35 | b30bb3a2 | balrog | int dw;
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36 | b30bb3a2 | balrog | int mode;
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37 | b30bb3a2 | balrog | int enable;
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38 | b30bb3a2 | balrog | uint16_t status; |
39 | b30bb3a2 | balrog | uint16_t mask; |
40 | b30bb3a2 | balrog | uint8_t cto; |
41 | b30bb3a2 | balrog | uint16_t dto; |
42 | b30bb3a2 | balrog | uint16_t fifo[32];
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43 | b30bb3a2 | balrog | int fifo_start;
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44 | b30bb3a2 | balrog | int fifo_len;
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45 | b30bb3a2 | balrog | uint16_t blen; |
46 | b30bb3a2 | balrog | uint16_t blen_counter; |
47 | b30bb3a2 | balrog | uint16_t nblk; |
48 | b30bb3a2 | balrog | uint16_t nblk_counter; |
49 | b30bb3a2 | balrog | int tx_dma;
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50 | b30bb3a2 | balrog | int rx_dma;
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51 | b30bb3a2 | balrog | int af_level;
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52 | b30bb3a2 | balrog | int ae_level;
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53 | b30bb3a2 | balrog | |
54 | b30bb3a2 | balrog | int ddir;
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55 | b30bb3a2 | balrog | int transfer;
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56 | b30bb3a2 | balrog | }; |
57 | b30bb3a2 | balrog | |
58 | b30bb3a2 | balrog | static void omap_mmc_interrupts_update(struct omap_mmc_s *s) |
59 | b30bb3a2 | balrog | { |
60 | b30bb3a2 | balrog | qemu_set_irq(s->irq, !!(s->status & s->mask)); |
61 | b30bb3a2 | balrog | } |
62 | b30bb3a2 | balrog | |
63 | b30bb3a2 | balrog | static void omap_mmc_fifolevel_update(struct omap_mmc_s *host) |
64 | b30bb3a2 | balrog | { |
65 | b30bb3a2 | balrog | if (!host->transfer && !host->fifo_len) {
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66 | b30bb3a2 | balrog | host->status &= 0xf3ff;
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67 | b30bb3a2 | balrog | return;
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68 | b30bb3a2 | balrog | } |
69 | b30bb3a2 | balrog | |
70 | b30bb3a2 | balrog | if (host->fifo_len > host->af_level && host->ddir) {
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71 | b30bb3a2 | balrog | if (host->rx_dma) {
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72 | b30bb3a2 | balrog | host->status &= 0xfbff;
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73 | b30bb3a2 | balrog | qemu_irq_raise(host->dma[1]);
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74 | b30bb3a2 | balrog | } else
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75 | b30bb3a2 | balrog | host->status |= 0x0400;
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76 | b30bb3a2 | balrog | } else {
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77 | b30bb3a2 | balrog | host->status &= 0xfbff;
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78 | b30bb3a2 | balrog | qemu_irq_lower(host->dma[1]);
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79 | b30bb3a2 | balrog | } |
80 | b30bb3a2 | balrog | |
81 | b30bb3a2 | balrog | if (host->fifo_len < host->ae_level && !host->ddir) {
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82 | b30bb3a2 | balrog | if (host->tx_dma) {
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83 | b30bb3a2 | balrog | host->status &= 0xf7ff;
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84 | b30bb3a2 | balrog | qemu_irq_raise(host->dma[0]);
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85 | b30bb3a2 | balrog | } else
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86 | b30bb3a2 | balrog | host->status |= 0x0800;
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87 | b30bb3a2 | balrog | } else {
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88 | b30bb3a2 | balrog | qemu_irq_lower(host->dma[0]);
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89 | b30bb3a2 | balrog | host->status &= 0xf7ff;
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90 | b30bb3a2 | balrog | } |
91 | b30bb3a2 | balrog | } |
92 | b30bb3a2 | balrog | |
93 | b30bb3a2 | balrog | typedef enum { |
94 | b30bb3a2 | balrog | sd_nore = 0, /* no response */ |
95 | b30bb3a2 | balrog | sd_r1, /* normal response command */
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96 | b30bb3a2 | balrog | sd_r2, /* CID, CSD registers */
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97 | b30bb3a2 | balrog | sd_r3, /* OCR register */
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98 | b30bb3a2 | balrog | sd_r6 = 6, /* Published RCA response */ |
99 | b30bb3a2 | balrog | sd_r1b = -1,
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100 | b30bb3a2 | balrog | } sd_rsp_type_t; |
101 | b30bb3a2 | balrog | |
102 | b30bb3a2 | balrog | static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, |
103 | b30bb3a2 | balrog | sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init) |
104 | b30bb3a2 | balrog | { |
105 | b30bb3a2 | balrog | uint32_t rspstatus, mask; |
106 | b30bb3a2 | balrog | int rsplen, timeout;
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107 | b30bb3a2 | balrog | struct sd_request_s request;
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108 | b30bb3a2 | balrog | uint8_t response[16];
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109 | b30bb3a2 | balrog | |
110 | b30bb3a2 | balrog | if (resptype == sd_r1 && busy)
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111 | b30bb3a2 | balrog | resptype = sd_r1b; |
112 | b30bb3a2 | balrog | |
113 | b30bb3a2 | balrog | if (type == sd_adtc) {
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114 | b30bb3a2 | balrog | host->fifo_start = 0;
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115 | b30bb3a2 | balrog | host->fifo_len = 0;
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116 | b30bb3a2 | balrog | host->transfer = 1;
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117 | b30bb3a2 | balrog | host->ddir = dir; |
118 | b30bb3a2 | balrog | } else
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119 | b30bb3a2 | balrog | host->transfer = 0;
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120 | b30bb3a2 | balrog | timeout = 0;
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121 | b30bb3a2 | balrog | mask = 0;
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122 | b30bb3a2 | balrog | rspstatus = 0;
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123 | b30bb3a2 | balrog | |
124 | b30bb3a2 | balrog | request.cmd = cmd; |
125 | b30bb3a2 | balrog | request.arg = host->arg; |
126 | b30bb3a2 | balrog | request.crc = 0; /* FIXME */ |
127 | b30bb3a2 | balrog | |
128 | b30bb3a2 | balrog | rsplen = sd_do_command(host->card, &request, response); |
129 | b30bb3a2 | balrog | |
130 | b30bb3a2 | balrog | /* TODO: validate CRCs */
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131 | b30bb3a2 | balrog | switch (resptype) {
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132 | b30bb3a2 | balrog | case sd_nore:
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133 | b30bb3a2 | balrog | rsplen = 0;
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134 | b30bb3a2 | balrog | break;
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135 | b30bb3a2 | balrog | |
136 | b30bb3a2 | balrog | case sd_r1:
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137 | b30bb3a2 | balrog | case sd_r1b:
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138 | b30bb3a2 | balrog | if (rsplen < 4) { |
139 | b30bb3a2 | balrog | timeout = 1;
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140 | b30bb3a2 | balrog | break;
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141 | b30bb3a2 | balrog | } |
142 | b30bb3a2 | balrog | rsplen = 4;
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143 | b30bb3a2 | balrog | |
144 | b30bb3a2 | balrog | mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR | |
145 | b30bb3a2 | balrog | ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION | |
146 | b30bb3a2 | balrog | LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND | |
147 | b30bb3a2 | balrog | CARD_ECC_FAILED | CC_ERROR | SD_ERROR | |
148 | b30bb3a2 | balrog | CID_CSD_OVERWRITE; |
149 | b30bb3a2 | balrog | if (host->sdio & (1 << 13)) |
150 | b30bb3a2 | balrog | mask |= AKE_SEQ_ERROR; |
151 | b30bb3a2 | balrog | rspstatus = (response[0] << 24) | (response[1] << 16) | |
152 | b30bb3a2 | balrog | (response[2] << 8) | (response[3] << 0); |
153 | b30bb3a2 | balrog | break;
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154 | b30bb3a2 | balrog | |
155 | b30bb3a2 | balrog | case sd_r2:
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156 | b30bb3a2 | balrog | if (rsplen < 16) { |
157 | b30bb3a2 | balrog | timeout = 1;
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158 | b30bb3a2 | balrog | break;
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159 | b30bb3a2 | balrog | } |
160 | b30bb3a2 | balrog | rsplen = 16;
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161 | b30bb3a2 | balrog | break;
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162 | b30bb3a2 | balrog | |
163 | b30bb3a2 | balrog | case sd_r3:
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164 | b30bb3a2 | balrog | if (rsplen < 4) { |
165 | b30bb3a2 | balrog | timeout = 1;
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166 | b30bb3a2 | balrog | break;
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167 | b30bb3a2 | balrog | } |
168 | b30bb3a2 | balrog | rsplen = 4;
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169 | b30bb3a2 | balrog | |
170 | b30bb3a2 | balrog | rspstatus = (response[0] << 24) | (response[1] << 16) | |
171 | b30bb3a2 | balrog | (response[2] << 8) | (response[3] << 0); |
172 | b30bb3a2 | balrog | if (rspstatus & 0x80000000) |
173 | b30bb3a2 | balrog | host->status &= 0xe000;
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174 | b30bb3a2 | balrog | else
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175 | b30bb3a2 | balrog | host->status |= 0x1000;
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176 | b30bb3a2 | balrog | break;
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177 | b30bb3a2 | balrog | |
178 | b30bb3a2 | balrog | case sd_r6:
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179 | b30bb3a2 | balrog | if (rsplen < 4) { |
180 | b30bb3a2 | balrog | timeout = 1;
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181 | b30bb3a2 | balrog | break;
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182 | b30bb3a2 | balrog | } |
183 | b30bb3a2 | balrog | rsplen = 4;
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184 | b30bb3a2 | balrog | |
185 | b30bb3a2 | balrog | mask = 0xe000 | AKE_SEQ_ERROR;
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186 | b30bb3a2 | balrog | rspstatus = (response[2] << 8) | (response[3] << 0); |
187 | b30bb3a2 | balrog | } |
188 | b30bb3a2 | balrog | |
189 | b30bb3a2 | balrog | if (rspstatus & mask)
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190 | b30bb3a2 | balrog | host->status |= 0x4000;
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191 | b30bb3a2 | balrog | else
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192 | b30bb3a2 | balrog | host->status &= 0xb000;
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193 | b30bb3a2 | balrog | |
194 | b30bb3a2 | balrog | if (rsplen)
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195 | b30bb3a2 | balrog | for (rsplen = 0; rsplen < 8; rsplen ++) |
196 | b30bb3a2 | balrog | host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] | |
197 | b30bb3a2 | balrog | (response[(rsplen << 1) | 0] << 8); |
198 | b30bb3a2 | balrog | |
199 | b30bb3a2 | balrog | if (timeout)
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200 | b30bb3a2 | balrog | host->status |= 0x0080;
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201 | b30bb3a2 | balrog | else if (cmd == 12) |
202 | b30bb3a2 | balrog | host->status |= 0x0005; /* Makes it more real */ |
203 | b30bb3a2 | balrog | else
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204 | b30bb3a2 | balrog | host->status |= 0x0001;
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205 | b30bb3a2 | balrog | } |
206 | b30bb3a2 | balrog | |
207 | b30bb3a2 | balrog | static void omap_mmc_transfer(struct omap_mmc_s *host) |
208 | b30bb3a2 | balrog | { |
209 | b30bb3a2 | balrog | uint8_t value; |
210 | b30bb3a2 | balrog | |
211 | b30bb3a2 | balrog | if (!host->transfer)
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212 | b30bb3a2 | balrog | return;
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213 | b30bb3a2 | balrog | |
214 | b30bb3a2 | balrog | while (1) { |
215 | b30bb3a2 | balrog | if (host->ddir) {
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216 | b30bb3a2 | balrog | if (host->fifo_len > host->af_level)
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217 | b30bb3a2 | balrog | break;
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218 | b30bb3a2 | balrog | |
219 | b30bb3a2 | balrog | value = sd_read_data(host->card); |
220 | b30bb3a2 | balrog | host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
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221 | b30bb3a2 | balrog | if (-- host->blen_counter) {
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222 | b30bb3a2 | balrog | value = sd_read_data(host->card); |
223 | b30bb3a2 | balrog | host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
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224 | b30bb3a2 | balrog | value << 8;
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225 | b30bb3a2 | balrog | host->blen_counter --; |
226 | b30bb3a2 | balrog | } |
227 | b30bb3a2 | balrog | |
228 | b30bb3a2 | balrog | host->fifo_len ++; |
229 | b30bb3a2 | balrog | } else {
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230 | b30bb3a2 | balrog | if (!host->fifo_len)
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231 | b30bb3a2 | balrog | break;
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232 | b30bb3a2 | balrog | |
233 | b30bb3a2 | balrog | value = host->fifo[host->fifo_start] & 0xff;
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234 | b30bb3a2 | balrog | sd_write_data(host->card, value); |
235 | b30bb3a2 | balrog | if (-- host->blen_counter) {
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236 | b30bb3a2 | balrog | value = host->fifo[host->fifo_start] >> 8;
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237 | b30bb3a2 | balrog | sd_write_data(host->card, value); |
238 | b30bb3a2 | balrog | host->blen_counter --; |
239 | b30bb3a2 | balrog | } |
240 | b30bb3a2 | balrog | |
241 | b30bb3a2 | balrog | host->fifo_start ++; |
242 | b30bb3a2 | balrog | host->fifo_len --; |
243 | b30bb3a2 | balrog | host->fifo_start &= 31;
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244 | b30bb3a2 | balrog | } |
245 | b30bb3a2 | balrog | |
246 | b30bb3a2 | balrog | if (host->blen_counter == 0) { |
247 | b30bb3a2 | balrog | host->nblk_counter --; |
248 | b30bb3a2 | balrog | host->blen_counter = host->blen; |
249 | b30bb3a2 | balrog | |
250 | b30bb3a2 | balrog | if (host->nblk_counter == 0) { |
251 | b30bb3a2 | balrog | host->nblk_counter = host->nblk; |
252 | b30bb3a2 | balrog | host->transfer = 0;
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253 | b30bb3a2 | balrog | host->status |= 0x0008;
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254 | b30bb3a2 | balrog | break;
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255 | b30bb3a2 | balrog | } |
256 | b30bb3a2 | balrog | } |
257 | b30bb3a2 | balrog | } |
258 | b30bb3a2 | balrog | } |
259 | b30bb3a2 | balrog | |
260 | b30bb3a2 | balrog | static void omap_mmc_update(void *opaque) |
261 | b30bb3a2 | balrog | { |
262 | b30bb3a2 | balrog | struct omap_mmc_s *s = opaque;
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263 | b30bb3a2 | balrog | omap_mmc_transfer(s); |
264 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
265 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
266 | b30bb3a2 | balrog | } |
267 | b30bb3a2 | balrog | |
268 | b30bb3a2 | balrog | static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset) |
269 | b30bb3a2 | balrog | { |
270 | b30bb3a2 | balrog | uint16_t i; |
271 | b30bb3a2 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; |
272 | cf965d24 | balrog | offset &= OMAP_MPUI_REG_MASK; |
273 | b30bb3a2 | balrog | |
274 | b30bb3a2 | balrog | switch (offset) {
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275 | b30bb3a2 | balrog | case 0x00: /* MMC_CMD */ |
276 | b30bb3a2 | balrog | return s->last_cmd;
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277 | b30bb3a2 | balrog | |
278 | b30bb3a2 | balrog | case 0x04: /* MMC_ARGL */ |
279 | b30bb3a2 | balrog | return s->arg & 0x0000ffff; |
280 | b30bb3a2 | balrog | |
281 | b30bb3a2 | balrog | case 0x08: /* MMC_ARGH */ |
282 | b30bb3a2 | balrog | return s->arg >> 16; |
283 | b30bb3a2 | balrog | |
284 | b30bb3a2 | balrog | case 0x0c: /* MMC_CON */ |
285 | b30bb3a2 | balrog | return (s->dw << 15) | (s->mode << 12) | (s->enable << 11); |
286 | b30bb3a2 | balrog | |
287 | b30bb3a2 | balrog | case 0x10: /* MMC_STAT */ |
288 | b30bb3a2 | balrog | return s->status;
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289 | b30bb3a2 | balrog | |
290 | b30bb3a2 | balrog | case 0x14: /* MMC_IE */ |
291 | b30bb3a2 | balrog | return s->mask;
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292 | b30bb3a2 | balrog | |
293 | b30bb3a2 | balrog | case 0x18: /* MMC_CTO */ |
294 | b30bb3a2 | balrog | return s->cto;
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295 | b30bb3a2 | balrog | |
296 | b30bb3a2 | balrog | case 0x1c: /* MMC_DTO */ |
297 | b30bb3a2 | balrog | return s->dto;
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298 | b30bb3a2 | balrog | |
299 | b30bb3a2 | balrog | case 0x20: /* MMC_DATA */ |
300 | b30bb3a2 | balrog | /* TODO: support 8-bit access */
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301 | b30bb3a2 | balrog | i = s->fifo[s->fifo_start]; |
302 | b30bb3a2 | balrog | if (s->fifo_len == 0) { |
303 | b30bb3a2 | balrog | printf("MMC: FIFO underrun\n");
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304 | b30bb3a2 | balrog | return i;
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305 | b30bb3a2 | balrog | } |
306 | b30bb3a2 | balrog | s->fifo_start ++; |
307 | b30bb3a2 | balrog | s->fifo_len --; |
308 | b30bb3a2 | balrog | s->fifo_start &= 31;
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309 | b30bb3a2 | balrog | omap_mmc_transfer(s); |
310 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
311 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
312 | b30bb3a2 | balrog | return i;
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313 | b30bb3a2 | balrog | |
314 | b30bb3a2 | balrog | case 0x24: /* MMC_BLEN */ |
315 | b30bb3a2 | balrog | return s->blen_counter;
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316 | b30bb3a2 | balrog | |
317 | b30bb3a2 | balrog | case 0x28: /* MMC_NBLK */ |
318 | b30bb3a2 | balrog | return s->nblk_counter;
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319 | b30bb3a2 | balrog | |
320 | b30bb3a2 | balrog | case 0x2c: /* MMC_BUF */ |
321 | b30bb3a2 | balrog | return (s->rx_dma << 15) | (s->af_level << 8) | |
322 | b30bb3a2 | balrog | (s->tx_dma << 7) | s->ae_level;
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323 | b30bb3a2 | balrog | |
324 | b30bb3a2 | balrog | case 0x30: /* MMC_SPI */ |
325 | b30bb3a2 | balrog | return 0x0000; |
326 | b30bb3a2 | balrog | case 0x34: /* MMC_SDIO */ |
327 | b30bb3a2 | balrog | return s->sdio;
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328 | b30bb3a2 | balrog | case 0x38: /* MMC_SYST */ |
329 | b30bb3a2 | balrog | return 0x0000; |
330 | b30bb3a2 | balrog | |
331 | b30bb3a2 | balrog | case 0x3c: /* MMC_REV */ |
332 | b30bb3a2 | balrog | return 0x0001; |
333 | b30bb3a2 | balrog | |
334 | b30bb3a2 | balrog | case 0x40: /* MMC_RSP0 */ |
335 | b30bb3a2 | balrog | case 0x44: /* MMC_RSP1 */ |
336 | b30bb3a2 | balrog | case 0x48: /* MMC_RSP2 */ |
337 | b30bb3a2 | balrog | case 0x4c: /* MMC_RSP3 */ |
338 | b30bb3a2 | balrog | case 0x50: /* MMC_RSP4 */ |
339 | b30bb3a2 | balrog | case 0x54: /* MMC_RSP5 */ |
340 | b30bb3a2 | balrog | case 0x58: /* MMC_RSP6 */ |
341 | b30bb3a2 | balrog | case 0x5c: /* MMC_RSP7 */ |
342 | b30bb3a2 | balrog | return s->rsp[(offset - 0x40) >> 2]; |
343 | b30bb3a2 | balrog | } |
344 | b30bb3a2 | balrog | |
345 | b30bb3a2 | balrog | OMAP_BAD_REG(offset); |
346 | b30bb3a2 | balrog | return 0; |
347 | b30bb3a2 | balrog | } |
348 | b30bb3a2 | balrog | |
349 | b30bb3a2 | balrog | static void omap_mmc_write(void *opaque, target_phys_addr_t offset, |
350 | b30bb3a2 | balrog | uint32_t value) |
351 | b30bb3a2 | balrog | { |
352 | b30bb3a2 | balrog | int i;
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353 | b30bb3a2 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; |
354 | cf965d24 | balrog | offset &= OMAP_MPUI_REG_MASK; |
355 | b30bb3a2 | balrog | |
356 | b30bb3a2 | balrog | switch (offset) {
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357 | b30bb3a2 | balrog | case 0x00: /* MMC_CMD */ |
358 | b30bb3a2 | balrog | if (!s->enable)
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359 | b30bb3a2 | balrog | break;
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360 | b30bb3a2 | balrog | |
361 | b30bb3a2 | balrog | s->last_cmd = value; |
362 | b30bb3a2 | balrog | for (i = 0; i < 8; i ++) |
363 | b30bb3a2 | balrog | s->rsp[i] = 0x0000;
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364 | b30bb3a2 | balrog | omap_mmc_command(s, value & 63, (value >> 15) & 1, |
365 | b30bb3a2 | balrog | (sd_cmd_type_t) ((value >> 12) & 3), |
366 | b30bb3a2 | balrog | (value >> 11) & 1, |
367 | b30bb3a2 | balrog | (sd_rsp_type_t) ((value >> 8) & 7), |
368 | b30bb3a2 | balrog | (value >> 7) & 1); |
369 | b30bb3a2 | balrog | omap_mmc_update(s); |
370 | b30bb3a2 | balrog | break;
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371 | b30bb3a2 | balrog | |
372 | b30bb3a2 | balrog | case 0x04: /* MMC_ARGL */ |
373 | b30bb3a2 | balrog | s->arg &= 0xffff0000;
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374 | b30bb3a2 | balrog | s->arg |= 0x0000ffff & value;
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375 | b30bb3a2 | balrog | break;
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376 | b30bb3a2 | balrog | |
377 | b30bb3a2 | balrog | case 0x08: /* MMC_ARGH */ |
378 | b30bb3a2 | balrog | s->arg &= 0x0000ffff;
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379 | b30bb3a2 | balrog | s->arg |= value << 16;
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380 | b30bb3a2 | balrog | break;
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381 | b30bb3a2 | balrog | |
382 | b30bb3a2 | balrog | case 0x0c: /* MMC_CON */ |
383 | b30bb3a2 | balrog | s->dw = (value >> 15) & 1; |
384 | b30bb3a2 | balrog | s->mode = (value >> 12) & 3; |
385 | b30bb3a2 | balrog | s->enable = (value >> 11) & 1; |
386 | b30bb3a2 | balrog | if (s->mode != 0) |
387 | b30bb3a2 | balrog | printf("SD mode %i unimplemented!\n", s->mode);
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388 | b30bb3a2 | balrog | if (s->dw != 0) |
389 | b30bb3a2 | balrog | printf("4-bit SD bus enabled\n");
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390 | b30bb3a2 | balrog | break;
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391 | b30bb3a2 | balrog | |
392 | b30bb3a2 | balrog | case 0x10: /* MMC_STAT */ |
393 | b30bb3a2 | balrog | s->status &= ~value; |
394 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
395 | b30bb3a2 | balrog | break;
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396 | b30bb3a2 | balrog | |
397 | b30bb3a2 | balrog | case 0x14: /* MMC_IE */ |
398 | b30bb3a2 | balrog | s->mask = value; |
399 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
400 | b30bb3a2 | balrog | break;
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401 | b30bb3a2 | balrog | |
402 | b30bb3a2 | balrog | case 0x18: /* MMC_CTO */ |
403 | b30bb3a2 | balrog | s->cto = value & 0xff;
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404 | b30bb3a2 | balrog | if (s->cto > 0xfd) |
405 | b30bb3a2 | balrog | printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
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406 | b30bb3a2 | balrog | break;
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407 | b30bb3a2 | balrog | |
408 | b30bb3a2 | balrog | case 0x1c: /* MMC_DTO */ |
409 | b30bb3a2 | balrog | s->dto = value & 0xffff;
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410 | b30bb3a2 | balrog | break;
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411 | b30bb3a2 | balrog | |
412 | b30bb3a2 | balrog | case 0x20: /* MMC_DATA */ |
413 | b30bb3a2 | balrog | /* TODO: support 8-bit access */
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414 | b30bb3a2 | balrog | if (s->fifo_len == 32) |
415 | b30bb3a2 | balrog | break;
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416 | b30bb3a2 | balrog | s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
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417 | b30bb3a2 | balrog | s->fifo_len ++; |
418 | b30bb3a2 | balrog | omap_mmc_transfer(s); |
419 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
420 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
421 | b30bb3a2 | balrog | break;
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422 | b30bb3a2 | balrog | |
423 | b30bb3a2 | balrog | case 0x24: /* MMC_BLEN */ |
424 | b30bb3a2 | balrog | s->blen = (value & 0x07ff) + 1; |
425 | b30bb3a2 | balrog | s->blen_counter = s->blen; |
426 | b30bb3a2 | balrog | break;
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427 | b30bb3a2 | balrog | |
428 | b30bb3a2 | balrog | case 0x28: /* MMC_NBLK */ |
429 | b30bb3a2 | balrog | s->nblk = (value & 0x07ff) + 1; |
430 | b30bb3a2 | balrog | s->nblk_counter = s->nblk; |
431 | b30bb3a2 | balrog | s->blen_counter = s->blen; |
432 | b30bb3a2 | balrog | break;
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433 | b30bb3a2 | balrog | |
434 | b30bb3a2 | balrog | case 0x2c: /* MMC_BUF */ |
435 | b30bb3a2 | balrog | s->rx_dma = (value >> 15) & 1; |
436 | b30bb3a2 | balrog | s->af_level = (value >> 8) & 0x1f; |
437 | b30bb3a2 | balrog | s->tx_dma = (value >> 7) & 1; |
438 | b30bb3a2 | balrog | s->ae_level = value & 0x1f;
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439 | b30bb3a2 | balrog | |
440 | b30bb3a2 | balrog | if (s->rx_dma)
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441 | b30bb3a2 | balrog | s->status &= 0xfbff;
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442 | b30bb3a2 | balrog | if (s->tx_dma)
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443 | b30bb3a2 | balrog | s->status &= 0xf7ff;
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444 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
445 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
446 | b30bb3a2 | balrog | break;
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447 | b30bb3a2 | balrog | |
448 | b30bb3a2 | balrog | /* SPI, SDIO and TEST modes unimplemented */
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449 | b30bb3a2 | balrog | case 0x30: /* MMC_SPI */ |
450 | b30bb3a2 | balrog | break;
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451 | b30bb3a2 | balrog | case 0x34: /* MMC_SDIO */ |
452 | b30bb3a2 | balrog | s->sdio = value & 0x2020;
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453 | b30bb3a2 | balrog | break;
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454 | b30bb3a2 | balrog | case 0x38: /* MMC_SYST */ |
455 | b30bb3a2 | balrog | break;
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456 | b30bb3a2 | balrog | |
457 | b30bb3a2 | balrog | case 0x3c: /* MMC_REV */ |
458 | b30bb3a2 | balrog | case 0x40: /* MMC_RSP0 */ |
459 | b30bb3a2 | balrog | case 0x44: /* MMC_RSP1 */ |
460 | b30bb3a2 | balrog | case 0x48: /* MMC_RSP2 */ |
461 | b30bb3a2 | balrog | case 0x4c: /* MMC_RSP3 */ |
462 | b30bb3a2 | balrog | case 0x50: /* MMC_RSP4 */ |
463 | b30bb3a2 | balrog | case 0x54: /* MMC_RSP5 */ |
464 | b30bb3a2 | balrog | case 0x58: /* MMC_RSP6 */ |
465 | b30bb3a2 | balrog | case 0x5c: /* MMC_RSP7 */ |
466 | b30bb3a2 | balrog | OMAP_RO_REG(offset); |
467 | b30bb3a2 | balrog | break;
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468 | b30bb3a2 | balrog | |
469 | b30bb3a2 | balrog | default:
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470 | b30bb3a2 | balrog | OMAP_BAD_REG(offset); |
471 | b30bb3a2 | balrog | } |
472 | b30bb3a2 | balrog | } |
473 | b30bb3a2 | balrog | |
474 | b30bb3a2 | balrog | static CPUReadMemoryFunc *omap_mmc_readfn[] = {
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475 | b30bb3a2 | balrog | omap_badwidth_read16, |
476 | b30bb3a2 | balrog | omap_mmc_read, |
477 | b30bb3a2 | balrog | omap_badwidth_read16, |
478 | b30bb3a2 | balrog | }; |
479 | b30bb3a2 | balrog | |
480 | b30bb3a2 | balrog | static CPUWriteMemoryFunc *omap_mmc_writefn[] = {
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481 | b30bb3a2 | balrog | omap_badwidth_write16, |
482 | b30bb3a2 | balrog | omap_mmc_write, |
483 | b30bb3a2 | balrog | omap_badwidth_write16, |
484 | b30bb3a2 | balrog | }; |
485 | b30bb3a2 | balrog | |
486 | b30bb3a2 | balrog | void omap_mmc_reset(struct omap_mmc_s *host) |
487 | b30bb3a2 | balrog | { |
488 | b30bb3a2 | balrog | host->last_cmd = 0;
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489 | b30bb3a2 | balrog | memset(host->rsp, 0, sizeof(host->rsp)); |
490 | b30bb3a2 | balrog | host->arg = 0;
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491 | b30bb3a2 | balrog | host->dw = 0;
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492 | b30bb3a2 | balrog | host->mode = 0;
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493 | b30bb3a2 | balrog | host->enable = 0;
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494 | b30bb3a2 | balrog | host->status = 0;
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495 | b30bb3a2 | balrog | host->mask = 0;
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496 | b30bb3a2 | balrog | host->cto = 0;
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497 | b30bb3a2 | balrog | host->dto = 0;
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498 | b30bb3a2 | balrog | host->fifo_len = 0;
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499 | b30bb3a2 | balrog | host->blen = 0;
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500 | b30bb3a2 | balrog | host->blen_counter = 0;
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501 | b30bb3a2 | balrog | host->nblk = 0;
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502 | b30bb3a2 | balrog | host->nblk_counter = 0;
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503 | b30bb3a2 | balrog | host->tx_dma = 0;
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504 | b30bb3a2 | balrog | host->rx_dma = 0;
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505 | b30bb3a2 | balrog | host->ae_level = 0x00;
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506 | b30bb3a2 | balrog | host->af_level = 0x1f;
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507 | b30bb3a2 | balrog | host->transfer = 0;
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508 | b30bb3a2 | balrog | } |
509 | b30bb3a2 | balrog | |
510 | 8e129e07 | balrog | static void omap_mmc_ro_cb(void *opaque, int level) |
511 | 8e129e07 | balrog | { |
512 | 8e129e07 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; |
513 | 8e129e07 | balrog | |
514 | 8e129e07 | balrog | if (s->handler[0]) |
515 | 8e129e07 | balrog | qemu_set_irq(s->handler[0], level);
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516 | 8e129e07 | balrog | } |
517 | 8e129e07 | balrog | |
518 | 8e129e07 | balrog | static void omap_mmc_cover_cb(void *opaque, int level) |
519 | 8e129e07 | balrog | { |
520 | 8e129e07 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; |
521 | 8e129e07 | balrog | |
522 | 8e129e07 | balrog | if (s->handler[1]) |
523 | 8e129e07 | balrog | qemu_set_irq(s->handler[1], level);
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524 | 8e129e07 | balrog | } |
525 | 8e129e07 | balrog | |
526 | b30bb3a2 | balrog | struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
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527 | b30bb3a2 | balrog | qemu_irq irq, qemu_irq dma[], omap_clk clk) |
528 | b30bb3a2 | balrog | { |
529 | b30bb3a2 | balrog | int iomemtype;
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530 | b30bb3a2 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) |
531 | b30bb3a2 | balrog | qemu_mallocz(sizeof(struct omap_mmc_s)); |
532 | b30bb3a2 | balrog | |
533 | b30bb3a2 | balrog | s->irq = irq; |
534 | b30bb3a2 | balrog | s->base = base; |
535 | b30bb3a2 | balrog | s->dma = dma; |
536 | b30bb3a2 | balrog | s->clk = clk; |
537 | b30bb3a2 | balrog | |
538 | b30bb3a2 | balrog | iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
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539 | b30bb3a2 | balrog | omap_mmc_writefn, s); |
540 | b30bb3a2 | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
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541 | b30bb3a2 | balrog | |
542 | b30bb3a2 | balrog | /* Instantiate the storage */
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543 | b30bb3a2 | balrog | s->card = sd_init(sd_bdrv); |
544 | b30bb3a2 | balrog | |
545 | 8e129e07 | balrog | sd_set_cb(s->card, s, omap_mmc_ro_cb, omap_mmc_cover_cb); |
546 | 8e129e07 | balrog | |
547 | b30bb3a2 | balrog | return s;
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548 | b30bb3a2 | balrog | } |
549 | b30bb3a2 | balrog | |
550 | 8e129e07 | balrog | void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover) |
551 | 8e129e07 | balrog | { |
552 | 8e129e07 | balrog | s->handler[0] = ro;
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553 | 8e129e07 | balrog | s->handler[1] = cover;
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554 | 8e129e07 | balrog | } |