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1 | 502a5395 | pbrook | /*
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2 | 502a5395 | pbrook | * QEMU i440FX/PIIX3 PCI Bridge Emulation
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3 | 502a5395 | pbrook | *
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4 | 502a5395 | pbrook | * Copyright (c) 2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
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12 | 502a5395 | pbrook | *
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13 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
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15 | 502a5395 | pbrook | *
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16 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 502a5395 | pbrook | * THE SOFTWARE.
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23 | 502a5395 | pbrook | */
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24 | 502a5395 | pbrook | |
25 | 502a5395 | pbrook | #include "vl.h" |
26 | 502a5395 | pbrook | typedef uint32_t pci_addr_t;
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27 | 502a5395 | pbrook | #include "pci_host.h" |
28 | 502a5395 | pbrook | |
29 | 502a5395 | pbrook | typedef PCIHostState I440FXState;
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30 | 502a5395 | pbrook | |
31 | 502a5395 | pbrook | static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
32 | 502a5395 | pbrook | { |
33 | 502a5395 | pbrook | I440FXState *s = opaque; |
34 | 502a5395 | pbrook | s->config_reg = val; |
35 | 502a5395 | pbrook | } |
36 | 502a5395 | pbrook | |
37 | 502a5395 | pbrook | static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr) |
38 | 502a5395 | pbrook | { |
39 | 502a5395 | pbrook | I440FXState *s = opaque; |
40 | 502a5395 | pbrook | return s->config_reg;
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41 | 502a5395 | pbrook | } |
42 | 502a5395 | pbrook | |
43 | d537cf6c | pbrook | static void piix3_set_irq(qemu_irq *pic, int irq_num, int level); |
44 | d2b59317 | pbrook | |
45 | d2b59317 | pbrook | /* return the global irq number corresponding to a given device irq
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46 | d2b59317 | pbrook | pin. We could also use the bus number to have a more precise
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47 | d2b59317 | pbrook | mapping. */
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48 | d2b59317 | pbrook | static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
49 | d2b59317 | pbrook | { |
50 | d2b59317 | pbrook | int slot_addend;
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51 | d2b59317 | pbrook | slot_addend = (pci_dev->devfn >> 3) - 1; |
52 | d2b59317 | pbrook | return (irq_num + slot_addend) & 3; |
53 | d2b59317 | pbrook | } |
54 | 502a5395 | pbrook | |
55 | ee0ea1d0 | bellard | static uint32_t isa_page_descs[384 / 4]; |
56 | ee0ea1d0 | bellard | static uint8_t smm_enabled;
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57 | ee0ea1d0 | bellard | |
58 | 84631fd7 | bellard | static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r) |
59 | 84631fd7 | bellard | { |
60 | 84631fd7 | bellard | uint32_t addr; |
61 | 84631fd7 | bellard | |
62 | 84631fd7 | bellard | // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
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63 | 84631fd7 | bellard | switch(r) {
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64 | 84631fd7 | bellard | case 3: |
65 | 84631fd7 | bellard | /* RAM */
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66 | 5fafdf24 | ths | cpu_register_physical_memory(start, end - start, |
67 | 84631fd7 | bellard | start); |
68 | 84631fd7 | bellard | break;
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69 | 84631fd7 | bellard | case 1: |
70 | 84631fd7 | bellard | /* ROM (XXX: not quite correct) */
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71 | 5fafdf24 | ths | cpu_register_physical_memory(start, end - start, |
72 | 84631fd7 | bellard | start | IO_MEM_ROM); |
73 | 84631fd7 | bellard | break;
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74 | 84631fd7 | bellard | case 2: |
75 | 84631fd7 | bellard | case 0: |
76 | 84631fd7 | bellard | /* XXX: should distinguish read/write cases */
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77 | 84631fd7 | bellard | for(addr = start; addr < end; addr += 4096) { |
78 | 5fafdf24 | ths | cpu_register_physical_memory(addr, 4096,
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79 | 84631fd7 | bellard | isa_page_descs[(addr - 0xa0000) >> 12]); |
80 | 84631fd7 | bellard | } |
81 | 84631fd7 | bellard | break;
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82 | 84631fd7 | bellard | } |
83 | 84631fd7 | bellard | } |
84 | ee0ea1d0 | bellard | |
85 | ee0ea1d0 | bellard | static void i440fx_update_memory_mappings(PCIDevice *d) |
86 | ee0ea1d0 | bellard | { |
87 | ee0ea1d0 | bellard | int i, r;
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88 | 84631fd7 | bellard | uint32_t smram, addr; |
89 | 84631fd7 | bellard | |
90 | 84631fd7 | bellard | update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3); |
91 | 84631fd7 | bellard | for(i = 0; i < 12; i++) { |
92 | 84631fd7 | bellard | r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3; |
93 | 84631fd7 | bellard | update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r); |
94 | ee0ea1d0 | bellard | } |
95 | 84631fd7 | bellard | smram = d->config[0x72];
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96 | 84631fd7 | bellard | if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) { |
97 | 84631fd7 | bellard | cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000); |
98 | 84631fd7 | bellard | } else {
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99 | 84631fd7 | bellard | for(addr = 0xa0000; addr < 0xc0000; addr += 4096) { |
100 | 5fafdf24 | ths | cpu_register_physical_memory(addr, 4096,
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101 | 84631fd7 | bellard | isa_page_descs[(addr - 0xa0000) >> 12]); |
102 | ee0ea1d0 | bellard | } |
103 | ee0ea1d0 | bellard | } |
104 | ee0ea1d0 | bellard | } |
105 | ee0ea1d0 | bellard | |
106 | ee0ea1d0 | bellard | void i440fx_set_smm(PCIDevice *d, int val) |
107 | ee0ea1d0 | bellard | { |
108 | ee0ea1d0 | bellard | val = (val != 0);
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109 | ee0ea1d0 | bellard | if (smm_enabled != val) {
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110 | ee0ea1d0 | bellard | smm_enabled = val; |
111 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
112 | ee0ea1d0 | bellard | } |
113 | ee0ea1d0 | bellard | } |
114 | ee0ea1d0 | bellard | |
115 | ee0ea1d0 | bellard | |
116 | ee0ea1d0 | bellard | /* XXX: suppress when better memory API. We make the assumption that
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117 | ee0ea1d0 | bellard | no device (in particular the VGA) changes the memory mappings in
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118 | ee0ea1d0 | bellard | the 0xa0000-0x100000 range */
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119 | ee0ea1d0 | bellard | void i440fx_init_memory_mappings(PCIDevice *d)
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120 | ee0ea1d0 | bellard | { |
121 | ee0ea1d0 | bellard | int i;
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122 | ee0ea1d0 | bellard | for(i = 0; i < 96; i++) { |
123 | ee0ea1d0 | bellard | isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000); |
124 | ee0ea1d0 | bellard | } |
125 | ee0ea1d0 | bellard | } |
126 | ee0ea1d0 | bellard | |
127 | 5fafdf24 | ths | static void i440fx_write_config(PCIDevice *d, |
128 | ee0ea1d0 | bellard | uint32_t address, uint32_t val, int len)
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129 | ee0ea1d0 | bellard | { |
130 | ee0ea1d0 | bellard | /* XXX: implement SMRAM.D_LOCK */
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131 | ee0ea1d0 | bellard | pci_default_write_config(d, address, val, len); |
132 | 84631fd7 | bellard | if ((address >= 0x59 && address <= 0x5f) || address == 0x72) |
133 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
134 | ee0ea1d0 | bellard | } |
135 | ee0ea1d0 | bellard | |
136 | ee0ea1d0 | bellard | static void i440fx_save(QEMUFile* f, void *opaque) |
137 | ee0ea1d0 | bellard | { |
138 | ee0ea1d0 | bellard | PCIDevice *d = opaque; |
139 | ee0ea1d0 | bellard | pci_device_save(d, f); |
140 | ee0ea1d0 | bellard | qemu_put_8s(f, &smm_enabled); |
141 | ee0ea1d0 | bellard | } |
142 | ee0ea1d0 | bellard | |
143 | ee0ea1d0 | bellard | static int i440fx_load(QEMUFile* f, void *opaque, int version_id) |
144 | ee0ea1d0 | bellard | { |
145 | ee0ea1d0 | bellard | PCIDevice *d = opaque; |
146 | ee0ea1d0 | bellard | int ret;
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147 | ee0ea1d0 | bellard | |
148 | ee0ea1d0 | bellard | if (version_id != 1) |
149 | ee0ea1d0 | bellard | return -EINVAL;
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150 | ee0ea1d0 | bellard | ret = pci_device_load(d, f); |
151 | ee0ea1d0 | bellard | if (ret < 0) |
152 | ee0ea1d0 | bellard | return ret;
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153 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
154 | ee0ea1d0 | bellard | qemu_get_8s(f, &smm_enabled); |
155 | ee0ea1d0 | bellard | return 0; |
156 | ee0ea1d0 | bellard | } |
157 | ee0ea1d0 | bellard | |
158 | d537cf6c | pbrook | PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic) |
159 | 502a5395 | pbrook | { |
160 | 502a5395 | pbrook | PCIBus *b; |
161 | 502a5395 | pbrook | PCIDevice *d; |
162 | 502a5395 | pbrook | I440FXState *s; |
163 | 502a5395 | pbrook | |
164 | 502a5395 | pbrook | s = qemu_mallocz(sizeof(I440FXState));
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165 | d537cf6c | pbrook | b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0, 4); |
166 | 502a5395 | pbrook | s->bus = b; |
167 | 502a5395 | pbrook | |
168 | 502a5395 | pbrook | register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s); |
169 | 502a5395 | pbrook | register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s); |
170 | 502a5395 | pbrook | |
171 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s); |
172 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s); |
173 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s); |
174 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s); |
175 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s); |
176 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s); |
177 | 502a5395 | pbrook | |
178 | 5fafdf24 | ths | d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0, |
179 | ee0ea1d0 | bellard | NULL, i440fx_write_config);
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180 | 502a5395 | pbrook | |
181 | 502a5395 | pbrook | d->config[0x00] = 0x86; // vendor_id |
182 | 502a5395 | pbrook | d->config[0x01] = 0x80; |
183 | 502a5395 | pbrook | d->config[0x02] = 0x37; // device_id |
184 | 502a5395 | pbrook | d->config[0x03] = 0x12; |
185 | 502a5395 | pbrook | d->config[0x08] = 0x02; // revision |
186 | 502a5395 | pbrook | d->config[0x0a] = 0x00; // class_sub = host2pci |
187 | 502a5395 | pbrook | d->config[0x0b] = 0x06; // class_base = PCI_bridge |
188 | 502a5395 | pbrook | d->config[0x0e] = 0x00; // header_type |
189 | ee0ea1d0 | bellard | |
190 | 84631fd7 | bellard | d->config[0x72] = 0x02; /* SMRAM */ |
191 | ee0ea1d0 | bellard | |
192 | ee0ea1d0 | bellard | register_savevm("I440FX", 0, 1, i440fx_save, i440fx_load, d); |
193 | ee0ea1d0 | bellard | *pi440fx_state = d; |
194 | 502a5395 | pbrook | return b;
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195 | 502a5395 | pbrook | } |
196 | 502a5395 | pbrook | |
197 | 502a5395 | pbrook | /* PIIX3 PCI to ISA bridge */
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198 | 502a5395 | pbrook | |
199 | 8f1c91d8 | ths | PCIDevice *piix3_dev; |
200 | 5c2b87e3 | ths | PCIDevice *piix4_dev; |
201 | 502a5395 | pbrook | |
202 | 502a5395 | pbrook | /* just used for simpler irq handling. */
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203 | 502a5395 | pbrook | #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
204 | 502a5395 | pbrook | |
205 | d2b59317 | pbrook | static int pci_irq_levels[4]; |
206 | 502a5395 | pbrook | |
207 | d537cf6c | pbrook | static void piix3_set_irq(qemu_irq *pic, int irq_num, int level) |
208 | 502a5395 | pbrook | { |
209 | d2b59317 | pbrook | int i, pic_irq, pic_level;
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210 | 502a5395 | pbrook | |
211 | 3f6ffb6a | ths | piix3_dev->config[0x60 + irq_num] &= ~0x80; // enable bit |
212 | d2b59317 | pbrook | pci_irq_levels[irq_num] = level; |
213 | 502a5395 | pbrook | |
214 | 502a5395 | pbrook | /* now we change the pic irq level according to the piix irq mappings */
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215 | 502a5395 | pbrook | /* XXX: optimize */
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216 | 502a5395 | pbrook | pic_irq = piix3_dev->config[0x60 + irq_num];
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217 | 502a5395 | pbrook | if (pic_irq < 16) { |
218 | d2b59317 | pbrook | /* The pic level is the logical OR of all the PCI irqs mapped
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219 | 502a5395 | pbrook | to it */
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220 | 502a5395 | pbrook | pic_level = 0;
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221 | d2b59317 | pbrook | for (i = 0; i < 4; i++) { |
222 | d2b59317 | pbrook | if (pic_irq == piix3_dev->config[0x60 + i]) |
223 | d2b59317 | pbrook | pic_level |= pci_irq_levels[i]; |
224 | d2b59317 | pbrook | } |
225 | d537cf6c | pbrook | qemu_set_irq(pic[pic_irq], pic_level); |
226 | 502a5395 | pbrook | } |
227 | 502a5395 | pbrook | } |
228 | 502a5395 | pbrook | |
229 | 502a5395 | pbrook | static void piix3_reset(PCIDevice *d) |
230 | 502a5395 | pbrook | { |
231 | 502a5395 | pbrook | uint8_t *pci_conf = d->config; |
232 | 502a5395 | pbrook | |
233 | 502a5395 | pbrook | pci_conf[0x04] = 0x07; // master, memory and I/O |
234 | 502a5395 | pbrook | pci_conf[0x05] = 0x00; |
235 | 502a5395 | pbrook | pci_conf[0x06] = 0x00; |
236 | 502a5395 | pbrook | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
237 | 502a5395 | pbrook | pci_conf[0x4c] = 0x4d; |
238 | 502a5395 | pbrook | pci_conf[0x4e] = 0x03; |
239 | 502a5395 | pbrook | pci_conf[0x4f] = 0x00; |
240 | 502a5395 | pbrook | pci_conf[0x60] = 0x80; |
241 | 502a5395 | pbrook | pci_conf[0x69] = 0x02; |
242 | 502a5395 | pbrook | pci_conf[0x70] = 0x80; |
243 | 502a5395 | pbrook | pci_conf[0x76] = 0x0c; |
244 | 502a5395 | pbrook | pci_conf[0x77] = 0x0c; |
245 | 502a5395 | pbrook | pci_conf[0x78] = 0x02; |
246 | 502a5395 | pbrook | pci_conf[0x79] = 0x00; |
247 | 502a5395 | pbrook | pci_conf[0x80] = 0x00; |
248 | 502a5395 | pbrook | pci_conf[0x82] = 0x00; |
249 | 502a5395 | pbrook | pci_conf[0xa0] = 0x08; |
250 | 502a5395 | pbrook | pci_conf[0xa2] = 0x00; |
251 | 502a5395 | pbrook | pci_conf[0xa3] = 0x00; |
252 | 502a5395 | pbrook | pci_conf[0xa4] = 0x00; |
253 | 502a5395 | pbrook | pci_conf[0xa5] = 0x00; |
254 | 502a5395 | pbrook | pci_conf[0xa6] = 0x00; |
255 | 502a5395 | pbrook | pci_conf[0xa7] = 0x00; |
256 | 502a5395 | pbrook | pci_conf[0xa8] = 0x0f; |
257 | 502a5395 | pbrook | pci_conf[0xaa] = 0x00; |
258 | 502a5395 | pbrook | pci_conf[0xab] = 0x00; |
259 | 502a5395 | pbrook | pci_conf[0xac] = 0x00; |
260 | 502a5395 | pbrook | pci_conf[0xae] = 0x00; |
261 | 502a5395 | pbrook | } |
262 | 502a5395 | pbrook | |
263 | 5c2b87e3 | ths | static void piix4_reset(PCIDevice *d) |
264 | 5c2b87e3 | ths | { |
265 | 5c2b87e3 | ths | uint8_t *pci_conf = d->config; |
266 | 5c2b87e3 | ths | |
267 | 5c2b87e3 | ths | pci_conf[0x04] = 0x07; // master, memory and I/O |
268 | 5c2b87e3 | ths | pci_conf[0x05] = 0x00; |
269 | 5c2b87e3 | ths | pci_conf[0x06] = 0x00; |
270 | 5c2b87e3 | ths | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
271 | 5c2b87e3 | ths | pci_conf[0x4c] = 0x4d; |
272 | 5c2b87e3 | ths | pci_conf[0x4e] = 0x03; |
273 | 5c2b87e3 | ths | pci_conf[0x4f] = 0x00; |
274 | 5c2b87e3 | ths | pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 |
275 | 5c2b87e3 | ths | pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 |
276 | 5c2b87e3 | ths | pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 |
277 | 5c2b87e3 | ths | pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 |
278 | 5c2b87e3 | ths | pci_conf[0x69] = 0x02; |
279 | 5c2b87e3 | ths | pci_conf[0x70] = 0x80; |
280 | 5c2b87e3 | ths | pci_conf[0x76] = 0x0c; |
281 | 5c2b87e3 | ths | pci_conf[0x77] = 0x0c; |
282 | 5c2b87e3 | ths | pci_conf[0x78] = 0x02; |
283 | 5c2b87e3 | ths | pci_conf[0x79] = 0x00; |
284 | 5c2b87e3 | ths | pci_conf[0x80] = 0x00; |
285 | 5c2b87e3 | ths | pci_conf[0x82] = 0x00; |
286 | 5c2b87e3 | ths | pci_conf[0xa0] = 0x08; |
287 | 5c2b87e3 | ths | pci_conf[0xa2] = 0x00; |
288 | 5c2b87e3 | ths | pci_conf[0xa3] = 0x00; |
289 | 5c2b87e3 | ths | pci_conf[0xa4] = 0x00; |
290 | 5c2b87e3 | ths | pci_conf[0xa5] = 0x00; |
291 | 5c2b87e3 | ths | pci_conf[0xa6] = 0x00; |
292 | 5c2b87e3 | ths | pci_conf[0xa7] = 0x00; |
293 | 5c2b87e3 | ths | pci_conf[0xa8] = 0x0f; |
294 | 5c2b87e3 | ths | pci_conf[0xaa] = 0x00; |
295 | 5c2b87e3 | ths | pci_conf[0xab] = 0x00; |
296 | 5c2b87e3 | ths | pci_conf[0xac] = 0x00; |
297 | 5c2b87e3 | ths | pci_conf[0xae] = 0x00; |
298 | 5c2b87e3 | ths | } |
299 | 5c2b87e3 | ths | |
300 | 1941d19c | bellard | static void piix_save(QEMUFile* f, void *opaque) |
301 | 1941d19c | bellard | { |
302 | 1941d19c | bellard | PCIDevice *d = opaque; |
303 | 1941d19c | bellard | pci_device_save(d, f); |
304 | 1941d19c | bellard | } |
305 | 1941d19c | bellard | |
306 | 1941d19c | bellard | static int piix_load(QEMUFile* f, void *opaque, int version_id) |
307 | 1941d19c | bellard | { |
308 | 1941d19c | bellard | PCIDevice *d = opaque; |
309 | 1941d19c | bellard | if (version_id != 2) |
310 | 1941d19c | bellard | return -EINVAL;
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311 | 1941d19c | bellard | return pci_device_load(d, f);
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312 | 1941d19c | bellard | } |
313 | 1941d19c | bellard | |
314 | e6a71ae3 | ths | int piix_init(PCIBus *bus, int devfn) |
315 | e6a71ae3 | ths | { |
316 | e6a71ae3 | ths | PCIDevice *d; |
317 | e6a71ae3 | ths | uint8_t *pci_conf; |
318 | e6a71ae3 | ths | |
319 | e6a71ae3 | ths | d = pci_register_device(bus, "PIIX", sizeof(PCIDevice), |
320 | e6a71ae3 | ths | devfn, NULL, NULL); |
321 | e6a71ae3 | ths | register_savevm("PIIX", 0, 2, piix_save, piix_load, d); |
322 | e6a71ae3 | ths | |
323 | e6a71ae3 | ths | piix3_dev = d; |
324 | e6a71ae3 | ths | pci_conf = d->config; |
325 | e6a71ae3 | ths | |
326 | e6a71ae3 | ths | pci_conf[0x00] = 0x86; // Intel |
327 | e6a71ae3 | ths | pci_conf[0x01] = 0x80; |
328 | e6a71ae3 | ths | pci_conf[0x02] = 0x2E; // 82371FB PIIX PCI-to-ISA bridge |
329 | e6a71ae3 | ths | pci_conf[0x03] = 0x12; |
330 | e6a71ae3 | ths | pci_conf[0x08] = 0x02; // Step A1 |
331 | e6a71ae3 | ths | pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
332 | e6a71ae3 | ths | pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
333 | e6a71ae3 | ths | pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
334 | e6a71ae3 | ths | |
335 | e6a71ae3 | ths | piix3_reset(d); |
336 | e6a71ae3 | ths | return d->devfn;
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337 | e6a71ae3 | ths | } |
338 | e6a71ae3 | ths | |
339 | 8f1c91d8 | ths | int piix3_init(PCIBus *bus, int devfn) |
340 | 502a5395 | pbrook | { |
341 | 502a5395 | pbrook | PCIDevice *d; |
342 | 502a5395 | pbrook | uint8_t *pci_conf; |
343 | 502a5395 | pbrook | |
344 | 502a5395 | pbrook | d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice), |
345 | 8f1c91d8 | ths | devfn, NULL, NULL); |
346 | 1941d19c | bellard | register_savevm("PIIX3", 0, 2, piix_save, piix_load, d); |
347 | 502a5395 | pbrook | |
348 | 502a5395 | pbrook | piix3_dev = d; |
349 | 502a5395 | pbrook | pci_conf = d->config; |
350 | 502a5395 | pbrook | |
351 | 502a5395 | pbrook | pci_conf[0x00] = 0x86; // Intel |
352 | 502a5395 | pbrook | pci_conf[0x01] = 0x80; |
353 | 502a5395 | pbrook | pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
354 | 502a5395 | pbrook | pci_conf[0x03] = 0x70; |
355 | 502a5395 | pbrook | pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
356 | 502a5395 | pbrook | pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
357 | 502a5395 | pbrook | pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
358 | 502a5395 | pbrook | |
359 | 502a5395 | pbrook | piix3_reset(d); |
360 | 502a5395 | pbrook | return d->devfn;
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361 | 502a5395 | pbrook | } |
362 | 5c2b87e3 | ths | |
363 | 5c2b87e3 | ths | int piix4_init(PCIBus *bus, int devfn) |
364 | 5c2b87e3 | ths | { |
365 | 5c2b87e3 | ths | PCIDevice *d; |
366 | 5c2b87e3 | ths | uint8_t *pci_conf; |
367 | 5c2b87e3 | ths | |
368 | 5c2b87e3 | ths | d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice), |
369 | 5c2b87e3 | ths | devfn, NULL, NULL); |
370 | 5c2b87e3 | ths | register_savevm("PIIX4", 0, 2, piix_save, piix_load, d); |
371 | 5c2b87e3 | ths | |
372 | 5c2b87e3 | ths | piix4_dev = d; |
373 | 5c2b87e3 | ths | pci_conf = d->config; |
374 | 5c2b87e3 | ths | |
375 | 5c2b87e3 | ths | pci_conf[0x00] = 0x86; // Intel |
376 | 5c2b87e3 | ths | pci_conf[0x01] = 0x80; |
377 | 5c2b87e3 | ths | pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge |
378 | 5c2b87e3 | ths | pci_conf[0x03] = 0x71; |
379 | 5c2b87e3 | ths | pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
380 | 5c2b87e3 | ths | pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
381 | 5c2b87e3 | ths | pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
382 | 5c2b87e3 | ths | |
383 | 5c2b87e3 | ths | piix4_reset(d); |
384 | 5c2b87e3 | ths | return d->devfn;
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385 | 5c2b87e3 | ths | } |