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1 | 5fafdf24 | ths | /*
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2 | 16406950 | pbrook | * ARM Versatile Platform/Application Baseboard System emulation.
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3 | cdbdb648 | pbrook | *
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4 | a1bb27b1 | pbrook | * Copyright (c) 2005-2007 CodeSourcery.
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5 | cdbdb648 | pbrook | * Written by Paul Brook
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6 | cdbdb648 | pbrook | *
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7 | cdbdb648 | pbrook | * This code is licenced under the GPL.
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8 | cdbdb648 | pbrook | */
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9 | cdbdb648 | pbrook | |
10 | cdbdb648 | pbrook | #include "vl.h" |
11 | cdbdb648 | pbrook | #include "arm_pic.h" |
12 | cdbdb648 | pbrook | |
13 | cdbdb648 | pbrook | /* Primary interrupt controller. */
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14 | cdbdb648 | pbrook | |
15 | cdbdb648 | pbrook | typedef struct vpb_sic_state |
16 | cdbdb648 | pbrook | { |
17 | cdbdb648 | pbrook | uint32_t base; |
18 | cdbdb648 | pbrook | uint32_t level; |
19 | cdbdb648 | pbrook | uint32_t mask; |
20 | cdbdb648 | pbrook | uint32_t pic_enable; |
21 | d537cf6c | pbrook | qemu_irq *parent; |
22 | cdbdb648 | pbrook | int irq;
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23 | cdbdb648 | pbrook | } vpb_sic_state; |
24 | cdbdb648 | pbrook | |
25 | cdbdb648 | pbrook | static void vpb_sic_update(vpb_sic_state *s) |
26 | cdbdb648 | pbrook | { |
27 | cdbdb648 | pbrook | uint32_t flags; |
28 | cdbdb648 | pbrook | |
29 | cdbdb648 | pbrook | flags = s->level & s->mask; |
30 | d537cf6c | pbrook | qemu_set_irq(s->parent[s->irq], flags != 0);
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31 | cdbdb648 | pbrook | } |
32 | cdbdb648 | pbrook | |
33 | cdbdb648 | pbrook | static void vpb_sic_update_pic(vpb_sic_state *s) |
34 | cdbdb648 | pbrook | { |
35 | cdbdb648 | pbrook | int i;
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36 | cdbdb648 | pbrook | uint32_t mask; |
37 | cdbdb648 | pbrook | |
38 | cdbdb648 | pbrook | for (i = 21; i <= 30; i++) { |
39 | cdbdb648 | pbrook | mask = 1u << i;
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40 | cdbdb648 | pbrook | if (!(s->pic_enable & mask))
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41 | cdbdb648 | pbrook | continue;
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42 | d537cf6c | pbrook | qemu_set_irq(s->parent[i], (s->level & mask) != 0);
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43 | cdbdb648 | pbrook | } |
44 | cdbdb648 | pbrook | } |
45 | cdbdb648 | pbrook | |
46 | cdbdb648 | pbrook | static void vpb_sic_set_irq(void *opaque, int irq, int level) |
47 | cdbdb648 | pbrook | { |
48 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
49 | cdbdb648 | pbrook | if (level)
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50 | cdbdb648 | pbrook | s->level |= 1u << irq;
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51 | cdbdb648 | pbrook | else
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52 | cdbdb648 | pbrook | s->level &= ~(1u << irq);
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53 | cdbdb648 | pbrook | if (s->pic_enable & (1u << irq)) |
54 | d537cf6c | pbrook | qemu_set_irq(s->parent[irq], level); |
55 | cdbdb648 | pbrook | vpb_sic_update(s); |
56 | cdbdb648 | pbrook | } |
57 | cdbdb648 | pbrook | |
58 | cdbdb648 | pbrook | static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset) |
59 | cdbdb648 | pbrook | { |
60 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
61 | cdbdb648 | pbrook | |
62 | cdbdb648 | pbrook | offset -= s->base; |
63 | cdbdb648 | pbrook | switch (offset >> 2) { |
64 | cdbdb648 | pbrook | case 0: /* STATUS */ |
65 | cdbdb648 | pbrook | return s->level & s->mask;
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66 | cdbdb648 | pbrook | case 1: /* RAWSTAT */ |
67 | cdbdb648 | pbrook | return s->level;
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68 | cdbdb648 | pbrook | case 2: /* ENABLE */ |
69 | cdbdb648 | pbrook | return s->mask;
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70 | cdbdb648 | pbrook | case 4: /* SOFTINT */ |
71 | cdbdb648 | pbrook | return s->level & 1; |
72 | cdbdb648 | pbrook | case 8: /* PICENABLE */ |
73 | cdbdb648 | pbrook | return s->pic_enable;
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74 | cdbdb648 | pbrook | default:
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75 | e69954b9 | pbrook | printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); |
76 | cdbdb648 | pbrook | return 0; |
77 | cdbdb648 | pbrook | } |
78 | cdbdb648 | pbrook | } |
79 | cdbdb648 | pbrook | |
80 | cdbdb648 | pbrook | static void vpb_sic_write(void *opaque, target_phys_addr_t offset, |
81 | cdbdb648 | pbrook | uint32_t value) |
82 | cdbdb648 | pbrook | { |
83 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
84 | cdbdb648 | pbrook | offset -= s->base; |
85 | cdbdb648 | pbrook | |
86 | cdbdb648 | pbrook | switch (offset >> 2) { |
87 | cdbdb648 | pbrook | case 2: /* ENSET */ |
88 | cdbdb648 | pbrook | s->mask |= value; |
89 | cdbdb648 | pbrook | break;
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90 | cdbdb648 | pbrook | case 3: /* ENCLR */ |
91 | cdbdb648 | pbrook | s->mask &= ~value; |
92 | cdbdb648 | pbrook | break;
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93 | cdbdb648 | pbrook | case 4: /* SOFTINTSET */ |
94 | cdbdb648 | pbrook | if (value)
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95 | cdbdb648 | pbrook | s->mask |= 1;
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96 | cdbdb648 | pbrook | break;
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97 | cdbdb648 | pbrook | case 5: /* SOFTINTCLR */ |
98 | cdbdb648 | pbrook | if (value)
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99 | cdbdb648 | pbrook | s->mask &= ~1u;
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100 | cdbdb648 | pbrook | break;
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101 | cdbdb648 | pbrook | case 8: /* PICENSET */ |
102 | cdbdb648 | pbrook | s->pic_enable |= (value & 0x7fe00000);
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103 | cdbdb648 | pbrook | vpb_sic_update_pic(s); |
104 | cdbdb648 | pbrook | break;
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105 | cdbdb648 | pbrook | case 9: /* PICENCLR */ |
106 | cdbdb648 | pbrook | s->pic_enable &= ~value; |
107 | cdbdb648 | pbrook | vpb_sic_update_pic(s); |
108 | cdbdb648 | pbrook | break;
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109 | cdbdb648 | pbrook | default:
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110 | e69954b9 | pbrook | printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); |
111 | cdbdb648 | pbrook | return;
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112 | cdbdb648 | pbrook | } |
113 | cdbdb648 | pbrook | vpb_sic_update(s); |
114 | cdbdb648 | pbrook | } |
115 | cdbdb648 | pbrook | |
116 | cdbdb648 | pbrook | static CPUReadMemoryFunc *vpb_sic_readfn[] = {
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117 | cdbdb648 | pbrook | vpb_sic_read, |
118 | cdbdb648 | pbrook | vpb_sic_read, |
119 | cdbdb648 | pbrook | vpb_sic_read |
120 | cdbdb648 | pbrook | }; |
121 | cdbdb648 | pbrook | |
122 | cdbdb648 | pbrook | static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
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123 | cdbdb648 | pbrook | vpb_sic_write, |
124 | cdbdb648 | pbrook | vpb_sic_write, |
125 | cdbdb648 | pbrook | vpb_sic_write |
126 | cdbdb648 | pbrook | }; |
127 | cdbdb648 | pbrook | |
128 | d537cf6c | pbrook | static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq) |
129 | cdbdb648 | pbrook | { |
130 | cdbdb648 | pbrook | vpb_sic_state *s; |
131 | d537cf6c | pbrook | qemu_irq *qi; |
132 | cdbdb648 | pbrook | int iomemtype;
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133 | cdbdb648 | pbrook | |
134 | cdbdb648 | pbrook | s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
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135 | cdbdb648 | pbrook | if (!s)
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136 | cdbdb648 | pbrook | return NULL; |
137 | d537cf6c | pbrook | qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
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138 | cdbdb648 | pbrook | s->base = base; |
139 | cdbdb648 | pbrook | s->parent = parent; |
140 | cdbdb648 | pbrook | s->irq = irq; |
141 | cdbdb648 | pbrook | iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
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142 | cdbdb648 | pbrook | vpb_sic_writefn, s); |
143 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
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144 | cdbdb648 | pbrook | /* ??? Save/restore. */
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145 | d537cf6c | pbrook | return qi;
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146 | cdbdb648 | pbrook | } |
147 | cdbdb648 | pbrook | |
148 | cdbdb648 | pbrook | /* Board init. */
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149 | cdbdb648 | pbrook | |
150 | 16406950 | pbrook | /* The AB and PB boards both use the same core, just with different
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151 | 16406950 | pbrook | peripherans and expansion busses. For now we emulate a subset of the
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152 | 16406950 | pbrook | PB peripherals and just change the board ID. */
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153 | cdbdb648 | pbrook | |
154 | 6ac0e82d | balrog | static void versatile_init(int ram_size, int vga_ram_size, |
155 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
156 | 6ac0e82d | balrog | const char **fd_filename, int snapshot, |
157 | cdbdb648 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
158 | 3371d272 | pbrook | const char *initrd_filename, const char *cpu_model, |
159 | 3371d272 | pbrook | int board_id)
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160 | cdbdb648 | pbrook | { |
161 | cdbdb648 | pbrook | CPUState *env; |
162 | d537cf6c | pbrook | qemu_irq *pic; |
163 | d537cf6c | pbrook | qemu_irq *sic; |
164 | 7d8406be | pbrook | void *scsi_hba;
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165 | 502a5395 | pbrook | PCIBus *pci_bus; |
166 | 502a5395 | pbrook | NICInfo *nd; |
167 | 502a5395 | pbrook | int n;
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168 | 502a5395 | pbrook | int done_smc = 0; |
169 | cdbdb648 | pbrook | |
170 | cdbdb648 | pbrook | env = cpu_init(); |
171 | 3371d272 | pbrook | if (!cpu_model)
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172 | 3371d272 | pbrook | cpu_model = "arm926";
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173 | 3371d272 | pbrook | cpu_arm_set_model(env, cpu_model); |
174 | cdbdb648 | pbrook | /* ??? RAM shoud repeat to fill physical memory space. */
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175 | cdbdb648 | pbrook | /* SDRAM at address zero. */
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176 | cdbdb648 | pbrook | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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177 | cdbdb648 | pbrook | |
178 | e69954b9 | pbrook | arm_sysctl_init(0x10000000, 0x41007004); |
179 | cdbdb648 | pbrook | pic = arm_pic_init_cpu(env); |
180 | d537cf6c | pbrook | pic = pl190_init(0x10140000, pic[0], pic[1]); |
181 | cdbdb648 | pbrook | sic = vpb_sic_init(0x10003000, pic, 31); |
182 | d537cf6c | pbrook | pl050_init(0x10006000, sic[3], 0); |
183 | d537cf6c | pbrook | pl050_init(0x10007000, sic[4], 1); |
184 | cdbdb648 | pbrook | |
185 | e69954b9 | pbrook | pci_bus = pci_vpb_init(sic, 27, 0); |
186 | 502a5395 | pbrook | /* The Versatile PCI bridge does not provide access to PCI IO space,
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187 | 502a5395 | pbrook | so many of the qemu PCI devices are not useable. */
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188 | 502a5395 | pbrook | for(n = 0; n < nb_nics; n++) { |
189 | 502a5395 | pbrook | nd = &nd_table[n]; |
190 | 502a5395 | pbrook | if (!nd->model)
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191 | 502a5395 | pbrook | nd->model = done_smc ? "rtl8139" : "smc91c111"; |
192 | 502a5395 | pbrook | if (strcmp(nd->model, "smc91c111") == 0) { |
193 | d537cf6c | pbrook | smc91c111_init(nd, 0x10010000, sic[25]); |
194 | cdbdb648 | pbrook | } else {
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195 | abcebc7e | ths | pci_nic_init(pci_bus, nd, -1);
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196 | cdbdb648 | pbrook | } |
197 | cdbdb648 | pbrook | } |
198 | 0d92ed30 | pbrook | if (usb_enabled) {
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199 | e24ad6f1 | pbrook | usb_ohci_init_pci(pci_bus, 3, -1); |
200 | 0d92ed30 | pbrook | } |
201 | 7d8406be | pbrook | scsi_hba = lsi_scsi_init(pci_bus, -1);
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202 | 7d8406be | pbrook | for (n = 0; n < MAX_DISKS; n++) { |
203 | 7d8406be | pbrook | if (bs_table[n]) {
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204 | 7d8406be | pbrook | lsi_scsi_attach(scsi_hba, bs_table[n], n); |
205 | 7d8406be | pbrook | } |
206 | 7d8406be | pbrook | } |
207 | cdbdb648 | pbrook | |
208 | d537cf6c | pbrook | pl011_init(0x101f1000, pic[12], serial_hds[0]); |
209 | d537cf6c | pbrook | pl011_init(0x101f2000, pic[13], serial_hds[1]); |
210 | d537cf6c | pbrook | pl011_init(0x101f3000, pic[14], serial_hds[2]); |
211 | d537cf6c | pbrook | pl011_init(0x10009000, sic[6], serial_hds[3]); |
212 | cdbdb648 | pbrook | |
213 | d537cf6c | pbrook | pl080_init(0x10130000, pic[17], 8); |
214 | d537cf6c | pbrook | sp804_init(0x101e2000, pic[4]); |
215 | d537cf6c | pbrook | sp804_init(0x101e3000, pic[5]); |
216 | cdbdb648 | pbrook | |
217 | cdbdb648 | pbrook | /* The versatile/PB actually has a modified Color LCD controller
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218 | cdbdb648 | pbrook | that includes hardware cursor support from the PL111. */
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219 | d537cf6c | pbrook | pl110_init(ds, 0x10120000, pic[16], 1); |
220 | cdbdb648 | pbrook | |
221 | d537cf6c | pbrook | pl181_init(0x10005000, sd_bdrv, sic[22], sic[1]); |
222 | a1bb27b1 | pbrook | #if 0
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223 | a1bb27b1 | pbrook | /* Disabled because there's no way of specifying a block device. */
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224 | a1bb27b1 | pbrook | pl181_init(0x1000b000, NULL, sic, 23, 2);
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225 | a1bb27b1 | pbrook | #endif
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226 | a1bb27b1 | pbrook | |
227 | 7e1543c2 | pbrook | /* Add PL031 Real Time Clock. */
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228 | 7e1543c2 | pbrook | pl031_init(0x101e8000,pic[10]); |
229 | 7e1543c2 | pbrook | |
230 | 16406950 | pbrook | /* Memory map for Versatile/PB: */
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231 | cdbdb648 | pbrook | /* 0x10000000 System registers. */
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232 | cdbdb648 | pbrook | /* 0x10001000 PCI controller config registers. */
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233 | cdbdb648 | pbrook | /* 0x10002000 Serial bus interface. */
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234 | cdbdb648 | pbrook | /* 0x10003000 Secondary interrupt controller. */
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235 | cdbdb648 | pbrook | /* 0x10004000 AACI (audio). */
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236 | a1bb27b1 | pbrook | /* 0x10005000 MMCI0. */
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237 | cdbdb648 | pbrook | /* 0x10006000 KMI0 (keyboard). */
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238 | cdbdb648 | pbrook | /* 0x10007000 KMI1 (mouse). */
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239 | cdbdb648 | pbrook | /* 0x10008000 Character LCD Interface. */
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240 | cdbdb648 | pbrook | /* 0x10009000 UART3. */
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241 | cdbdb648 | pbrook | /* 0x1000a000 Smart card 1. */
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242 | a1bb27b1 | pbrook | /* 0x1000b000 MMCI1. */
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243 | cdbdb648 | pbrook | /* 0x10010000 Ethernet. */
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244 | cdbdb648 | pbrook | /* 0x10020000 USB. */
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245 | cdbdb648 | pbrook | /* 0x10100000 SSMC. */
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246 | cdbdb648 | pbrook | /* 0x10110000 MPMC. */
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247 | cdbdb648 | pbrook | /* 0x10120000 CLCD Controller. */
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248 | cdbdb648 | pbrook | /* 0x10130000 DMA Controller. */
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249 | cdbdb648 | pbrook | /* 0x10140000 Vectored interrupt controller. */
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250 | cdbdb648 | pbrook | /* 0x101d0000 AHB Monitor Interface. */
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251 | cdbdb648 | pbrook | /* 0x101e0000 System Controller. */
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252 | cdbdb648 | pbrook | /* 0x101e1000 Watchdog Interface. */
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253 | cdbdb648 | pbrook | /* 0x101e2000 Timer 0/1. */
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254 | cdbdb648 | pbrook | /* 0x101e3000 Timer 2/3. */
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255 | cdbdb648 | pbrook | /* 0x101e4000 GPIO port 0. */
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256 | cdbdb648 | pbrook | /* 0x101e5000 GPIO port 1. */
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257 | cdbdb648 | pbrook | /* 0x101e6000 GPIO port 2. */
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258 | cdbdb648 | pbrook | /* 0x101e7000 GPIO port 3. */
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259 | cdbdb648 | pbrook | /* 0x101e8000 RTC. */
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260 | cdbdb648 | pbrook | /* 0x101f0000 Smart card 0. */
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261 | cdbdb648 | pbrook | /* 0x101f1000 UART0. */
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262 | cdbdb648 | pbrook | /* 0x101f2000 UART1. */
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263 | cdbdb648 | pbrook | /* 0x101f3000 UART2. */
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264 | cdbdb648 | pbrook | /* 0x101f4000 SSPI. */
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265 | cdbdb648 | pbrook | |
266 | daf90626 | pbrook | arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline, |
267 | 9d551997 | balrog | initrd_filename, board_id, 0x0);
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268 | 16406950 | pbrook | } |
269 | 16406950 | pbrook | |
270 | 6ac0e82d | balrog | static void vpb_init(int ram_size, int vga_ram_size, const char *boot_device, |
271 | 16406950 | pbrook | DisplayState *ds, const char **fd_filename, int snapshot, |
272 | 16406950 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
273 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
274 | 16406950 | pbrook | { |
275 | 16406950 | pbrook | versatile_init(ram_size, vga_ram_size, boot_device, |
276 | 16406950 | pbrook | ds, fd_filename, snapshot, |
277 | 16406950 | pbrook | kernel_filename, kernel_cmdline, |
278 | 3371d272 | pbrook | initrd_filename, cpu_model, 0x183);
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279 | 16406950 | pbrook | } |
280 | 16406950 | pbrook | |
281 | 6ac0e82d | balrog | static void vab_init(int ram_size, int vga_ram_size, const char *boot_device, |
282 | 16406950 | pbrook | DisplayState *ds, const char **fd_filename, int snapshot, |
283 | 16406950 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
284 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
285 | 16406950 | pbrook | { |
286 | 16406950 | pbrook | versatile_init(ram_size, vga_ram_size, boot_device, |
287 | 16406950 | pbrook | ds, fd_filename, snapshot, |
288 | 16406950 | pbrook | kernel_filename, kernel_cmdline, |
289 | 3371d272 | pbrook | initrd_filename, cpu_model, 0x25e);
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290 | cdbdb648 | pbrook | } |
291 | cdbdb648 | pbrook | |
292 | cdbdb648 | pbrook | QEMUMachine versatilepb_machine = { |
293 | cdbdb648 | pbrook | "versatilepb",
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294 | cdbdb648 | pbrook | "ARM Versatile/PB (ARM926EJ-S)",
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295 | cdbdb648 | pbrook | vpb_init, |
296 | cdbdb648 | pbrook | }; |
297 | 16406950 | pbrook | |
298 | 16406950 | pbrook | QEMUMachine versatileab_machine = { |
299 | 16406950 | pbrook | "versatileab",
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300 | 16406950 | pbrook | "ARM Versatile/AB (ARM926EJ-S)",
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301 | 16406950 | pbrook | vab_init, |
302 | 16406950 | pbrook | }; |