root / hw / mcf5208.c @ e3d7e843
History | View | Annotate | Download (8 kB)
1 |
/*
|
---|---|
2 |
* Motorola ColdFire MCF5208 SoC emulation.
|
3 |
*
|
4 |
* Copyright (c) 2007 CodeSourcery.
|
5 |
*
|
6 |
* This code is licenced under the GPL
|
7 |
*/
|
8 |
#include "vl.h" |
9 |
|
10 |
#define SYS_FREQ 66000000 |
11 |
|
12 |
#define PCSR_EN 0x0001 |
13 |
#define PCSR_RLD 0x0002 |
14 |
#define PCSR_PIF 0x0004 |
15 |
#define PCSR_PIE 0x0008 |
16 |
#define PCSR_OVW 0x0010 |
17 |
#define PCSR_DBG 0x0020 |
18 |
#define PCSR_DOZE 0x0040 |
19 |
#define PCSR_PRE_SHIFT 8 |
20 |
#define PCSR_PRE_MASK 0x0f00 |
21 |
|
22 |
typedef struct { |
23 |
qemu_irq irq; |
24 |
ptimer_state *timer; |
25 |
uint16_t pcsr; |
26 |
uint16_t pmr; |
27 |
uint16_t pcntr; |
28 |
} m5208_timer_state; |
29 |
|
30 |
static void m5208_timer_update(m5208_timer_state *s) |
31 |
{ |
32 |
if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
|
33 |
qemu_irq_raise(s->irq); |
34 |
else
|
35 |
qemu_irq_lower(s->irq); |
36 |
} |
37 |
|
38 |
static void m5208_timer_write(m5208_timer_state *s, int offset, |
39 |
uint32_t value) |
40 |
{ |
41 |
int prescale;
|
42 |
int limit;
|
43 |
switch (offset) {
|
44 |
case 0: |
45 |
/* The PIF bit is set-to-clear. */
|
46 |
if (value & PCSR_PIF) {
|
47 |
s->pcsr &= ~PCSR_PIF; |
48 |
value &= ~PCSR_PIF; |
49 |
} |
50 |
/* Avoid frobbing the timer if we're just twiddling IRQ bits. */
|
51 |
if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { |
52 |
s->pcsr = value; |
53 |
m5208_timer_update(s); |
54 |
return;
|
55 |
} |
56 |
|
57 |
if (s->pcsr & PCSR_EN)
|
58 |
ptimer_stop(s->timer); |
59 |
|
60 |
s->pcsr = value; |
61 |
|
62 |
prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
|
63 |
ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
|
64 |
if (s->pcsr & PCSR_RLD)
|
65 |
limit = s->pmr; |
66 |
else
|
67 |
limit = 0xffff;
|
68 |
ptimer_set_limit(s->timer, limit, 0);
|
69 |
|
70 |
if (s->pcsr & PCSR_EN)
|
71 |
ptimer_run(s->timer, 0);
|
72 |
break;
|
73 |
case 2: |
74 |
s->pmr = value; |
75 |
s->pcsr &= ~PCSR_PIF; |
76 |
if ((s->pcsr & PCSR_RLD) == 0) { |
77 |
if (s->pcsr & PCSR_OVW)
|
78 |
ptimer_set_count(s->timer, value); |
79 |
} else {
|
80 |
ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); |
81 |
} |
82 |
break;
|
83 |
case 4: |
84 |
break;
|
85 |
default:
|
86 |
/* Should never happen. */
|
87 |
abort(); |
88 |
} |
89 |
m5208_timer_update(s); |
90 |
} |
91 |
|
92 |
static void m5208_timer_trigger(void *opaque) |
93 |
{ |
94 |
m5208_timer_state *s = (m5208_timer_state *)opaque; |
95 |
s->pcsr |= PCSR_PIF; |
96 |
m5208_timer_update(s); |
97 |
} |
98 |
|
99 |
typedef struct { |
100 |
m5208_timer_state timer[2];
|
101 |
} m5208_sys_state; |
102 |
|
103 |
static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr) |
104 |
{ |
105 |
m5208_sys_state *s = (m5208_sys_state *)opaque; |
106 |
switch (addr) {
|
107 |
/* PIT0 */
|
108 |
case 0xfc080000: |
109 |
return s->timer[0].pcsr; |
110 |
case 0xfc080002: |
111 |
return s->timer[0].pmr; |
112 |
case 0xfc080004: |
113 |
return ptimer_get_count(s->timer[0].timer); |
114 |
/* PIT1 */
|
115 |
case 0xfc084000: |
116 |
return s->timer[1].pcsr; |
117 |
case 0xfc084002: |
118 |
return s->timer[1].pmr; |
119 |
case 0xfc084004: |
120 |
return ptimer_get_count(s->timer[1].timer); |
121 |
|
122 |
/* SDRAM Controller. */
|
123 |
case 0xfc0a8110: /* SDCS0 */ |
124 |
{ |
125 |
int n;
|
126 |
for (n = 0; n < 32; n++) { |
127 |
if (ram_size < (2u << n)) |
128 |
break;
|
129 |
} |
130 |
return (n - 1) | 0x40000000; |
131 |
} |
132 |
case 0xfc0a8114: /* SDCS1 */ |
133 |
return 0; |
134 |
|
135 |
default:
|
136 |
cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n",
|
137 |
(int)addr);
|
138 |
return 0; |
139 |
} |
140 |
} |
141 |
|
142 |
static void m5208_sys_write(void *opaque, target_phys_addr_t addr, |
143 |
uint32_t value) |
144 |
{ |
145 |
m5208_sys_state *s = (m5208_sys_state *)opaque; |
146 |
switch (addr) {
|
147 |
/* PIT0 */
|
148 |
case 0xfc080000: |
149 |
case 0xfc080002: |
150 |
case 0xfc080004: |
151 |
m5208_timer_write(&s->timer[0], addr & 0xf, value); |
152 |
return;
|
153 |
/* PIT1 */
|
154 |
case 0xfc084000: |
155 |
case 0xfc084002: |
156 |
case 0xfc084004: |
157 |
m5208_timer_write(&s->timer[1], addr & 0xf, value); |
158 |
return;
|
159 |
default:
|
160 |
cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
|
161 |
(int)addr);
|
162 |
break;
|
163 |
} |
164 |
} |
165 |
|
166 |
static CPUReadMemoryFunc *m5208_sys_readfn[] = {
|
167 |
m5208_sys_read, |
168 |
m5208_sys_read, |
169 |
m5208_sys_read |
170 |
}; |
171 |
|
172 |
static CPUWriteMemoryFunc *m5208_sys_writefn[] = {
|
173 |
m5208_sys_write, |
174 |
m5208_sys_write, |
175 |
m5208_sys_write |
176 |
}; |
177 |
|
178 |
static void mcf5208_sys_init(qemu_irq *pic) |
179 |
{ |
180 |
int iomemtype;
|
181 |
m5208_sys_state *s; |
182 |
QEMUBH *bh; |
183 |
int i;
|
184 |
|
185 |
s = (m5208_sys_state *)qemu_mallocz(sizeof(m5208_sys_state));
|
186 |
iomemtype = cpu_register_io_memory(0, m5208_sys_readfn,
|
187 |
m5208_sys_writefn, s); |
188 |
/* SDRAMC. */
|
189 |
cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype); |
190 |
/* Timers. */
|
191 |
for (i = 0; i < 2; i++) { |
192 |
bh = qemu_bh_new(m5208_timer_trigger, &s->timer[i]); |
193 |
s->timer[i].timer = ptimer_init(bh); |
194 |
cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000, |
195 |
iomemtype); |
196 |
s->timer[i].irq = pic[4 + i];
|
197 |
} |
198 |
} |
199 |
|
200 |
static void mcf5208evb_init(int ram_size, int vga_ram_size, |
201 |
const char *boot_device, DisplayState *ds, |
202 |
const char **fd_filename, int snapshot, |
203 |
const char *kernel_filename, const char *kernel_cmdline, |
204 |
const char *initrd_filename, const char *cpu_model) |
205 |
{ |
206 |
CPUState *env; |
207 |
int kernel_size;
|
208 |
uint64_t elf_entry; |
209 |
target_ulong entry; |
210 |
qemu_irq *pic; |
211 |
|
212 |
env = cpu_init(); |
213 |
if (!cpu_model)
|
214 |
cpu_model = "m5208";
|
215 |
if (cpu_m68k_set_model(env, cpu_model)) {
|
216 |
cpu_abort(env, "Unable to find m68k CPU definition\n");
|
217 |
} |
218 |
|
219 |
/* Initialize CPU registers. */
|
220 |
env->vbr = 0;
|
221 |
/* TODO: Configure BARs. */
|
222 |
|
223 |
/* DRAM at 0x20000000 */
|
224 |
cpu_register_physical_memory(0x40000000, ram_size,
|
225 |
qemu_ram_alloc(ram_size) | IO_MEM_RAM); |
226 |
|
227 |
/* Internal SRAM. */
|
228 |
cpu_register_physical_memory(0x80000000, 16384, |
229 |
qemu_ram_alloc(16384) | IO_MEM_RAM);
|
230 |
|
231 |
/* Internal peripherals. */
|
232 |
pic = mcf_intc_init(0xfc048000, env);
|
233 |
|
234 |
mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]); |
235 |
mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); |
236 |
mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); |
237 |
|
238 |
mcf5208_sys_init(pic); |
239 |
|
240 |
if (nb_nics > 1) { |
241 |
fprintf(stderr, "Too many NICs\n");
|
242 |
exit(1);
|
243 |
} |
244 |
if (nd_table[0].vlan) { |
245 |
if (nd_table[0].model == NULL |
246 |
|| strcmp(nd_table[0].model, "mcf_fec") == 0) { |
247 |
mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36); |
248 |
} else if (strcmp(nd_table[0].model, "?") == 0) { |
249 |
fprintf(stderr, "qemu: Supported NICs: mcf_fec\n");
|
250 |
exit (1);
|
251 |
} else {
|
252 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
253 |
exit (1);
|
254 |
} |
255 |
} |
256 |
|
257 |
/* 0xfc000000 SCM. */
|
258 |
/* 0xfc004000 XBS. */
|
259 |
/* 0xfc008000 FlexBus CS. */
|
260 |
/* 0xfc030000 FEC. */
|
261 |
/* 0xfc040000 SCM + Power management. */
|
262 |
/* 0xfc044000 eDMA. */
|
263 |
/* 0xfc048000 INTC. */
|
264 |
/* 0xfc058000 I2C. */
|
265 |
/* 0xfc05c000 QSPI. */
|
266 |
/* 0xfc060000 UART0. */
|
267 |
/* 0xfc064000 UART0. */
|
268 |
/* 0xfc068000 UART0. */
|
269 |
/* 0xfc070000 DMA timers. */
|
270 |
/* 0xfc080000 PIT0. */
|
271 |
/* 0xfc084000 PIT1. */
|
272 |
/* 0xfc088000 EPORT. */
|
273 |
/* 0xfc08c000 Watchdog. */
|
274 |
/* 0xfc090000 clock module. */
|
275 |
/* 0xfc0a0000 CCM + reset. */
|
276 |
/* 0xfc0a4000 GPIO. */
|
277 |
/* 0xfc0a8000 SDRAM controller. */
|
278 |
|
279 |
/* Load kernel. */
|
280 |
if (!kernel_filename) {
|
281 |
fprintf(stderr, "Kernel image must be specified\n");
|
282 |
exit(1);
|
283 |
} |
284 |
|
285 |
kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL); |
286 |
entry = elf_entry; |
287 |
if (kernel_size < 0) { |
288 |
kernel_size = load_uboot(kernel_filename, &entry, NULL);
|
289 |
} |
290 |
if (kernel_size < 0) { |
291 |
kernel_size = load_image(kernel_filename, phys_ram_base); |
292 |
entry = 0x20000000;
|
293 |
} |
294 |
if (kernel_size < 0) { |
295 |
fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
|
296 |
exit(1);
|
297 |
} |
298 |
|
299 |
env->pc = entry; |
300 |
} |
301 |
|
302 |
QEMUMachine mcf5208evb_machine = { |
303 |
"mcf5208evb",
|
304 |
"MCF5206EVB",
|
305 |
mcf5208evb_init, |
306 |
}; |