root / hw / pxa2xx_mmci.c @ e3d7e843
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/*
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* Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GPLv2.
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*/
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#include "vl.h" |
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#include "sd.h" |
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struct pxa2xx_mmci_s {
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target_phys_addr_t base; |
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qemu_irq irq; |
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void *dma;
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SDState *card; |
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uint32_t status; |
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uint32_t clkrt; |
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uint32_t spi; |
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uint32_t cmdat; |
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uint32_t resp_tout; |
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uint32_t read_tout; |
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int blklen;
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int numblk;
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uint32_t intmask; |
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uint32_t intreq; |
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int cmd;
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uint32_t arg; |
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int active;
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int bytesleft;
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uint8_t tx_fifo[64];
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int tx_start;
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int tx_len;
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uint8_t rx_fifo[32];
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int rx_start;
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int rx_len;
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uint16_t resp_fifo[9];
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int resp_len;
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int cmdreq;
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int ac_width;
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}; |
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#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */ |
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#define MMC_STAT 0x04 /* MMC Status register */ |
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#define MMC_CLKRT 0x08 /* MMC Clock Rate register */ |
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#define MMC_SPI 0x0c /* MMC SPI Mode register */ |
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#define MMC_CMDAT 0x10 /* MMC Command/Data register */ |
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#define MMC_RESTO 0x14 /* MMC Response Time-Out register */ |
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#define MMC_RDTO 0x18 /* MMC Read Time-Out register */ |
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#define MMC_BLKLEN 0x1c /* MMC Block Length register */ |
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#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */ |
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#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */ |
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#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */ |
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#define MMC_I_REG 0x2c /* MMC Interrupt Request register */ |
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#define MMC_CMD 0x30 /* MMC Command register */ |
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#define MMC_ARGH 0x34 /* MMC Argument High register */ |
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#define MMC_ARGL 0x38 /* MMC Argument Low register */ |
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#define MMC_RES 0x3c /* MMC Response FIFO */ |
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#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */ |
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#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */ |
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#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */ |
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#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */ |
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/* Bitfield masks */
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#define STRPCL_STOP_CLK (1 << 0) |
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#define STRPCL_STRT_CLK (1 << 1) |
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#define STAT_TOUT_RES (1 << 1) |
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#define STAT_CLK_EN (1 << 8) |
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#define STAT_DATA_DONE (1 << 11) |
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#define STAT_PRG_DONE (1 << 12) |
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#define STAT_END_CMDRES (1 << 13) |
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#define SPI_SPI_MODE (1 << 0) |
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#define CMDAT_RES_TYPE (3 << 0) |
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#define CMDAT_DATA_EN (1 << 2) |
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#define CMDAT_WR_RD (1 << 3) |
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#define CMDAT_DMA_EN (1 << 7) |
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#define CMDAT_STOP_TRAN (1 << 10) |
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#define INT_DATA_DONE (1 << 0) |
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#define INT_PRG_DONE (1 << 1) |
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#define INT_END_CMD (1 << 2) |
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#define INT_STOP_CMD (1 << 3) |
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#define INT_CLK_OFF (1 << 4) |
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#define INT_RXFIFO_REQ (1 << 5) |
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#define INT_TXFIFO_REQ (1 << 6) |
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#define INT_TINT (1 << 7) |
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#define INT_DAT_ERR (1 << 8) |
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#define INT_RES_ERR (1 << 9) |
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#define INT_RD_STALLED (1 << 10) |
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#define INT_SDIO_INT (1 << 11) |
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#define INT_SDIO_SACK (1 << 12) |
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#define PRTBUF_PRT_BUF (1 << 0) |
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/* Route internal interrupt lines to the global IC and DMA */
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static void pxa2xx_mmci_int_update(struct pxa2xx_mmci_s *s) |
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{ |
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uint32_t mask = s->intmask; |
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if (s->cmdat & CMDAT_DMA_EN) {
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mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ; |
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pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
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PXA2XX_RX_RQ_MMCI, !!(s->intreq & INT_RXFIFO_REQ)); |
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pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
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PXA2XX_TX_RQ_MMCI, !!(s->intreq & INT_TXFIFO_REQ)); |
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} |
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qemu_set_irq(s->irq, !!(s->intreq & ~mask)); |
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} |
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static void pxa2xx_mmci_fifo_update(struct pxa2xx_mmci_s *s) |
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{ |
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if (!s->active)
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return;
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if (s->cmdat & CMDAT_WR_RD) {
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while (s->bytesleft && s->tx_len) {
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sd_write_data(s->card, s->tx_fifo[s->tx_start ++]); |
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s->tx_start &= 0x1f;
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s->tx_len --; |
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s->bytesleft --; |
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} |
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if (s->bytesleft)
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s->intreq |= INT_TXFIFO_REQ; |
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} else
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while (s->bytesleft && s->rx_len < 32) { |
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s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
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sd_read_data(s->card); |
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s->bytesleft --; |
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s->intreq |= INT_RXFIFO_REQ; |
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} |
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if (!s->bytesleft) {
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s->active = 0;
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s->intreq |= INT_DATA_DONE; |
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s->status |= STAT_DATA_DONE; |
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if (s->cmdat & CMDAT_WR_RD) {
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s->intreq |= INT_PRG_DONE; |
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s->status |= STAT_PRG_DONE; |
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} |
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} |
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pxa2xx_mmci_int_update(s); |
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} |
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static void pxa2xx_mmci_wakequeues(struct pxa2xx_mmci_s *s) |
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{ |
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int rsplen, i;
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struct sd_request_s request;
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uint8_t response[16];
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s->active = 1;
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s->rx_len = 0;
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s->tx_len = 0;
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s->cmdreq = 0;
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request.cmd = s->cmd; |
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request.arg = s->arg; |
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request.crc = 0; /* FIXME */ |
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rsplen = sd_do_command(s->card, &request, response); |
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s->intreq |= INT_END_CMD; |
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memset(s->resp_fifo, 0, sizeof(s->resp_fifo)); |
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switch (s->cmdat & CMDAT_RES_TYPE) {
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#define PXAMMCI_RESP(wd, value0, value1) \
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s->resp_fifo[(wd) + 0] |= (value0); \
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s->resp_fifo[(wd) + 1] |= (value1) << 8; |
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case 0: /* No response */ |
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goto complete;
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case 1: /* R1, R4, R5 or R6 */ |
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if (rsplen < 4) |
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goto timeout;
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goto complete;
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case 2: /* R2 */ |
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if (rsplen < 16) |
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goto timeout;
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goto complete;
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case 3: /* R3 */ |
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if (rsplen < 4) |
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goto timeout;
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goto complete;
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complete:
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for (i = 0; rsplen > 0; i ++, rsplen -= 2) { |
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PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]); |
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} |
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s->status |= STAT_END_CMDRES; |
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if (!(s->cmdat & CMDAT_DATA_EN))
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s->active = 0;
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else
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s->bytesleft = s->numblk * s->blklen; |
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s->resp_len = 0;
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break;
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timeout:
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s->active = 0;
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s->status |= STAT_TOUT_RES; |
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break;
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} |
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pxa2xx_mmci_fifo_update(s); |
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} |
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static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset) |
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{ |
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struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
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uint32_t ret; |
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offset -= s->base; |
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switch (offset) {
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case MMC_STRPCL:
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return 0; |
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case MMC_STAT:
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return s->status;
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case MMC_CLKRT:
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return s->clkrt;
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case MMC_SPI:
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return s->spi;
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case MMC_CMDAT:
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return s->cmdat;
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case MMC_RESTO:
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return s->resp_tout;
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case MMC_RDTO:
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return s->read_tout;
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case MMC_BLKLEN:
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return s->blklen;
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case MMC_NUMBLK:
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return s->numblk;
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case MMC_PRTBUF:
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return 0; |
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case MMC_I_MASK:
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return s->intmask;
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case MMC_I_REG:
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return s->intreq;
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case MMC_CMD:
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return s->cmd | 0x40; |
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case MMC_ARGH:
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return s->arg >> 16; |
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case MMC_ARGL:
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return s->arg & 0xffff; |
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case MMC_RES:
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if (s->resp_len < 9) |
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return s->resp_fifo[s->resp_len ++];
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return 0; |
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case MMC_RXFIFO:
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ret = 0;
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while (s->ac_width -- && s->rx_len) {
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ret |= s->rx_fifo[s->rx_start ++] << (s->ac_width << 3);
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s->rx_start &= 0x1f;
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s->rx_len --; |
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} |
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s->intreq &= ~INT_RXFIFO_REQ; |
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pxa2xx_mmci_fifo_update(s); |
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return ret;
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case MMC_RDWAIT:
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return 0; |
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case MMC_BLKS_REM:
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return s->numblk;
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default:
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cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n", |
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__FUNCTION__, offset); |
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} |
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return 0; |
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} |
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static void pxa2xx_mmci_write(void *opaque, |
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target_phys_addr_t offset, uint32_t value) |
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{ |
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struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
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offset -= s->base; |
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switch (offset) {
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case MMC_STRPCL:
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if (value & STRPCL_STRT_CLK) {
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s->status |= STAT_CLK_EN; |
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s->intreq &= ~INT_CLK_OFF; |
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if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
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s->status &= STAT_CLK_EN; |
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pxa2xx_mmci_wakequeues(s); |
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} |
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} |
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if (value & STRPCL_STOP_CLK) {
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s->status &= ~STAT_CLK_EN; |
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s->intreq |= INT_CLK_OFF; |
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s->active = 0;
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} |
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pxa2xx_mmci_int_update(s); |
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break;
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case MMC_CLKRT:
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s->clkrt = value & 7;
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break;
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case MMC_SPI:
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s->spi = value & 0xf;
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if (value & SPI_SPI_MODE)
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printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
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break;
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case MMC_CMDAT:
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s->cmdat = value & 0x3dff;
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s->active = 0;
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s->cmdreq = 1;
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if (!(value & CMDAT_STOP_TRAN)) {
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s->status &= STAT_CLK_EN; |
320 |
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if (s->status & STAT_CLK_EN)
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pxa2xx_mmci_wakequeues(s); |
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} |
324 |
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pxa2xx_mmci_int_update(s); |
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break;
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case MMC_RESTO:
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s->resp_tout = value & 0x7f;
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break;
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case MMC_RDTO:
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s->read_tout = value & 0xffff;
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break;
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case MMC_BLKLEN:
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s->blklen = value & 0xfff;
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break;
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case MMC_NUMBLK:
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s->numblk = value & 0xffff;
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break;
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case MMC_PRTBUF:
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if (value & PRTBUF_PRT_BUF) {
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s->tx_start ^= 32;
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s->tx_len = 0;
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} |
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pxa2xx_mmci_fifo_update(s); |
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break;
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case MMC_I_MASK:
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s->intmask = value & 0x1fff;
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pxa2xx_mmci_int_update(s); |
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break;
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case MMC_CMD:
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s->cmd = value & 0x3f;
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break;
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360 |
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case MMC_ARGH:
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s->arg &= 0x0000ffff;
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s->arg |= value << 16;
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break;
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case MMC_ARGL:
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s->arg &= 0xffff0000;
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s->arg |= value & 0x0000ffff;
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break;
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case MMC_TXFIFO:
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while (s->ac_width -- && s->tx_len < 0x20) |
373 |
s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
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(value >> (s->ac_width << 3)) & 0xff; |
375 |
s->intreq &= ~INT_TXFIFO_REQ; |
376 |
pxa2xx_mmci_fifo_update(s); |
377 |
break;
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378 |
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case MMC_RDWAIT:
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case MMC_BLKS_REM:
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break;
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382 |
|
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default:
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cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n", |
385 |
__FUNCTION__, offset); |
386 |
} |
387 |
} |
388 |
|
389 |
static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset) |
390 |
{ |
391 |
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
392 |
s->ac_width = 1;
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return pxa2xx_mmci_read(opaque, offset);
|
394 |
} |
395 |
|
396 |
static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset) |
397 |
{ |
398 |
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
399 |
s->ac_width = 2;
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return pxa2xx_mmci_read(opaque, offset);
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401 |
} |
402 |
|
403 |
static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset) |
404 |
{ |
405 |
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
406 |
s->ac_width = 4;
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407 |
return pxa2xx_mmci_read(opaque, offset);
|
408 |
} |
409 |
|
410 |
static CPUReadMemoryFunc *pxa2xx_mmci_readfn[] = {
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411 |
pxa2xx_mmci_readb, |
412 |
pxa2xx_mmci_readh, |
413 |
pxa2xx_mmci_readw |
414 |
}; |
415 |
|
416 |
static void pxa2xx_mmci_writeb(void *opaque, |
417 |
target_phys_addr_t offset, uint32_t value) |
418 |
{ |
419 |
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
420 |
s->ac_width = 1;
|
421 |
pxa2xx_mmci_write(opaque, offset, value); |
422 |
} |
423 |
|
424 |
static void pxa2xx_mmci_writeh(void *opaque, |
425 |
target_phys_addr_t offset, uint32_t value) |
426 |
{ |
427 |
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
428 |
s->ac_width = 2;
|
429 |
pxa2xx_mmci_write(opaque, offset, value); |
430 |
} |
431 |
|
432 |
static void pxa2xx_mmci_writew(void *opaque, |
433 |
target_phys_addr_t offset, uint32_t value) |
434 |
{ |
435 |
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
436 |
s->ac_width = 4;
|
437 |
pxa2xx_mmci_write(opaque, offset, value); |
438 |
} |
439 |
|
440 |
static CPUWriteMemoryFunc *pxa2xx_mmci_writefn[] = {
|
441 |
pxa2xx_mmci_writeb, |
442 |
pxa2xx_mmci_writeh, |
443 |
pxa2xx_mmci_writew |
444 |
}; |
445 |
|
446 |
static void pxa2xx_mmci_save(QEMUFile *f, void *opaque) |
447 |
{ |
448 |
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
449 |
int i;
|
450 |
|
451 |
qemu_put_be32s(f, &s->status); |
452 |
qemu_put_be32s(f, &s->clkrt); |
453 |
qemu_put_be32s(f, &s->spi); |
454 |
qemu_put_be32s(f, &s->cmdat); |
455 |
qemu_put_be32s(f, &s->resp_tout); |
456 |
qemu_put_be32s(f, &s->read_tout); |
457 |
qemu_put_be32(f, s->blklen); |
458 |
qemu_put_be32(f, s->numblk); |
459 |
qemu_put_be32s(f, &s->intmask); |
460 |
qemu_put_be32s(f, &s->intreq); |
461 |
qemu_put_be32(f, s->cmd); |
462 |
qemu_put_be32s(f, &s->arg); |
463 |
qemu_put_be32(f, s->cmdreq); |
464 |
qemu_put_be32(f, s->active); |
465 |
qemu_put_be32(f, s->bytesleft); |
466 |
|
467 |
qemu_put_byte(f, s->tx_len); |
468 |
for (i = 0; i < s->tx_len; i ++) |
469 |
qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]);
|
470 |
|
471 |
qemu_put_byte(f, s->rx_len); |
472 |
for (i = 0; i < s->rx_len; i ++) |
473 |
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]);
|
474 |
|
475 |
qemu_put_byte(f, s->resp_len); |
476 |
for (i = s->resp_len; i < 9; i ++) |
477 |
qemu_put_be16s(f, &s->resp_fifo[i]); |
478 |
} |
479 |
|
480 |
static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id) |
481 |
{ |
482 |
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
483 |
int i;
|
484 |
|
485 |
qemu_get_be32s(f, &s->status); |
486 |
qemu_get_be32s(f, &s->clkrt); |
487 |
qemu_get_be32s(f, &s->spi); |
488 |
qemu_get_be32s(f, &s->cmdat); |
489 |
qemu_get_be32s(f, &s->resp_tout); |
490 |
qemu_get_be32s(f, &s->read_tout); |
491 |
s->blklen = qemu_get_be32(f); |
492 |
s->numblk = qemu_get_be32(f); |
493 |
qemu_get_be32s(f, &s->intmask); |
494 |
qemu_get_be32s(f, &s->intreq); |
495 |
s->cmd = qemu_get_be32(f); |
496 |
qemu_get_be32s(f, &s->arg); |
497 |
s->cmdreq = qemu_get_be32(f); |
498 |
s->active = qemu_get_be32(f); |
499 |
s->bytesleft = qemu_get_be32(f); |
500 |
|
501 |
s->tx_len = qemu_get_byte(f); |
502 |
s->tx_start = 0;
|
503 |
if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0) |
504 |
return -EINVAL;
|
505 |
for (i = 0; i < s->tx_len; i ++) |
506 |
s->tx_fifo[i] = qemu_get_byte(f); |
507 |
|
508 |
s->rx_len = qemu_get_byte(f); |
509 |
s->rx_start = 0;
|
510 |
if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0) |
511 |
return -EINVAL;
|
512 |
for (i = 0; i < s->rx_len; i ++) |
513 |
s->rx_fifo[i] = qemu_get_byte(f); |
514 |
|
515 |
s->resp_len = qemu_get_byte(f); |
516 |
if (s->resp_len > 9 || s->resp_len < 0) |
517 |
return -EINVAL;
|
518 |
for (i = s->resp_len; i < 9; i ++) |
519 |
qemu_get_be16s(f, &s->resp_fifo[i]); |
520 |
|
521 |
return 0; |
522 |
} |
523 |
|
524 |
struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
|
525 |
qemu_irq irq, void *dma)
|
526 |
{ |
527 |
int iomemtype;
|
528 |
struct pxa2xx_mmci_s *s;
|
529 |
|
530 |
s = (struct pxa2xx_mmci_s *) qemu_mallocz(sizeof(struct pxa2xx_mmci_s)); |
531 |
s->base = base; |
532 |
s->irq = irq; |
533 |
s->dma = dma; |
534 |
|
535 |
iomemtype = cpu_register_io_memory(0, pxa2xx_mmci_readfn,
|
536 |
pxa2xx_mmci_writefn, s); |
537 |
cpu_register_physical_memory(base, 0x00100000, iomemtype);
|
538 |
|
539 |
/* Instantiate the actual storage */
|
540 |
s->card = sd_init(sd_bdrv); |
541 |
|
542 |
register_savevm("pxa2xx_mmci", 0, 0, |
543 |
pxa2xx_mmci_save, pxa2xx_mmci_load, s); |
544 |
|
545 |
return s;
|
546 |
} |
547 |
|
548 |
void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, void *opaque, |
549 |
void (*readonly_cb)(void *, int), |
550 |
void (*coverswitch_cb)(void *, int)) |
551 |
{ |
552 |
sd_set_cb(s->card, opaque, readonly_cb, coverswitch_cb); |
553 |
} |