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1 | 1ad2134f | Paul Brook | #ifndef CPU_COMMON_H
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2 | 1ad2134f | Paul Brook | #define CPU_COMMON_H 1 |
3 | 1ad2134f | Paul Brook | |
4 | 07f35073 | Dong Xu Wang | /* CPU interfaces that are target independent. */
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5 | 1ad2134f | Paul Brook | |
6 | 37b76cfd | Paolo Bonzini | #ifdef TARGET_PHYS_ADDR_BITS
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7 | 37b76cfd | Paolo Bonzini | #include "targphys.h" |
8 | 37b76cfd | Paolo Bonzini | #endif
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9 | 37b76cfd | Paolo Bonzini | |
10 | 37b76cfd | Paolo Bonzini | #ifndef NEED_CPU_H
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11 | 37b76cfd | Paolo Bonzini | #include "poison.h" |
12 | 37b76cfd | Paolo Bonzini | #endif
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13 | 37b76cfd | Paolo Bonzini | |
14 | 1ad2134f | Paul Brook | #include "bswap.h" |
15 | f6f3fbca | Michael S. Tsirkin | #include "qemu-queue.h" |
16 | 1ad2134f | Paul Brook | |
17 | b3755a91 | Paul Brook | #if !defined(CONFIG_USER_ONLY)
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18 | b3755a91 | Paul Brook | |
19 | dd310534 | Alexander Graf | enum device_endian {
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20 | dd310534 | Alexander Graf | DEVICE_NATIVE_ENDIAN, |
21 | dd310534 | Alexander Graf | DEVICE_BIG_ENDIAN, |
22 | dd310534 | Alexander Graf | DEVICE_LITTLE_ENDIAN, |
23 | dd310534 | Alexander Graf | }; |
24 | dd310534 | Alexander Graf | |
25 | 1ad2134f | Paul Brook | /* address in the RAM (different from a physical address) */
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26 | f15fbc4b | Anthony PERARD | #if defined(CONFIG_XEN_BACKEND) && TARGET_PHYS_ADDR_BITS == 64 |
27 | f15fbc4b | Anthony PERARD | typedef uint64_t ram_addr_t;
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28 | f15fbc4b | Anthony PERARD | # define RAM_ADDR_MAX UINT64_MAX
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29 | f15fbc4b | Anthony PERARD | # define RAM_ADDR_FMT "%" PRIx64 |
30 | f15fbc4b | Anthony PERARD | #else
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31 | 53576999 | Stefan Weil | typedef uintptr_t ram_addr_t;
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32 | 53576999 | Stefan Weil | # define RAM_ADDR_MAX UINTPTR_MAX
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33 | 53576999 | Stefan Weil | # define RAM_ADDR_FMT "%" PRIxPTR |
34 | f15fbc4b | Anthony PERARD | #endif
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35 | 1ad2134f | Paul Brook | |
36 | 1ad2134f | Paul Brook | /* memory API */
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37 | 1ad2134f | Paul Brook | |
38 | c227f099 | Anthony Liguori | typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); |
39 | c227f099 | Anthony Liguori | typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); |
40 | 1ad2134f | Paul Brook | |
41 | cd19cfa2 | Huang Ying | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
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42 | 1ad2134f | Paul Brook | /* This should only be used for ram local to a device. */
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43 | c227f099 | Anthony Liguori | void *qemu_get_ram_ptr(ram_addr_t addr);
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44 | 8ab934f9 | Stefano Stabellini | void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size);
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45 | b2e0a138 | Michael S. Tsirkin | /* Same but slower, to use for migration, where the order of
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46 | b2e0a138 | Michael S. Tsirkin | * RAMBlocks must not change. */
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47 | b2e0a138 | Michael S. Tsirkin | void *qemu_safe_ram_ptr(ram_addr_t addr);
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48 | 050a0ddf | Anthony PERARD | void qemu_put_ram_ptr(void *addr); |
49 | 1ad2134f | Paul Brook | /* This should not be used by devices. */
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50 | e890261f | Marcelo Tosatti | int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); |
51 | e890261f | Marcelo Tosatti | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
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52 | c5705a77 | Avi Kivity | void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev); |
53 | 1ad2134f | Paul Brook | |
54 | c227f099 | Anthony Liguori | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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55 | 1ad2134f | Paul Brook | int len, int is_write); |
56 | c227f099 | Anthony Liguori | static inline void cpu_physical_memory_read(target_phys_addr_t addr, |
57 | 3bad9814 | Stefan Weil | void *buf, int len) |
58 | 1ad2134f | Paul Brook | { |
59 | 1ad2134f | Paul Brook | cpu_physical_memory_rw(addr, buf, len, 0);
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60 | 1ad2134f | Paul Brook | } |
61 | c227f099 | Anthony Liguori | static inline void cpu_physical_memory_write(target_phys_addr_t addr, |
62 | 3bad9814 | Stefan Weil | const void *buf, int len) |
63 | 1ad2134f | Paul Brook | { |
64 | 3bad9814 | Stefan Weil | cpu_physical_memory_rw(addr, (void *)buf, len, 1); |
65 | 1ad2134f | Paul Brook | } |
66 | c227f099 | Anthony Liguori | void *cpu_physical_memory_map(target_phys_addr_t addr,
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67 | c227f099 | Anthony Liguori | target_phys_addr_t *plen, |
68 | 1ad2134f | Paul Brook | int is_write);
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69 | c227f099 | Anthony Liguori | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
70 | c227f099 | Anthony Liguori | int is_write, target_phys_addr_t access_len);
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71 | 1ad2134f | Paul Brook | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); |
72 | 1ad2134f | Paul Brook | void cpu_unregister_map_client(void *cookie); |
73 | 1ad2134f | Paul Brook | |
74 | 76f35538 | Wen Congyang | #ifndef CONFIG_USER_ONLY
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75 | 76f35538 | Wen Congyang | bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr);
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76 | 76f35538 | Wen Congyang | #endif
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77 | 76f35538 | Wen Congyang | |
78 | 6842a08e | Blue Swirl | /* Coalesced MMIO regions are areas where write operations can be reordered.
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79 | 6842a08e | Blue Swirl | * This usually implies that write operations are side-effect free. This allows
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80 | 6842a08e | Blue Swirl | * batching which can make a major impact on performance when using
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81 | 6842a08e | Blue Swirl | * virtualization.
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82 | 6842a08e | Blue Swirl | */
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83 | 6842a08e | Blue Swirl | void qemu_flush_coalesced_mmio_buffer(void); |
84 | 6842a08e | Blue Swirl | |
85 | c227f099 | Anthony Liguori | uint32_t ldub_phys(target_phys_addr_t addr); |
86 | 1e78bcc1 | Alexander Graf | uint32_t lduw_le_phys(target_phys_addr_t addr); |
87 | 1e78bcc1 | Alexander Graf | uint32_t lduw_be_phys(target_phys_addr_t addr); |
88 | 1e78bcc1 | Alexander Graf | uint32_t ldl_le_phys(target_phys_addr_t addr); |
89 | 1e78bcc1 | Alexander Graf | uint32_t ldl_be_phys(target_phys_addr_t addr); |
90 | 1e78bcc1 | Alexander Graf | uint64_t ldq_le_phys(target_phys_addr_t addr); |
91 | 1e78bcc1 | Alexander Graf | uint64_t ldq_be_phys(target_phys_addr_t addr); |
92 | c227f099 | Anthony Liguori | void stb_phys(target_phys_addr_t addr, uint32_t val);
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93 | 1e78bcc1 | Alexander Graf | void stw_le_phys(target_phys_addr_t addr, uint32_t val);
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94 | 1e78bcc1 | Alexander Graf | void stw_be_phys(target_phys_addr_t addr, uint32_t val);
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95 | 1e78bcc1 | Alexander Graf | void stl_le_phys(target_phys_addr_t addr, uint32_t val);
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96 | 1e78bcc1 | Alexander Graf | void stl_be_phys(target_phys_addr_t addr, uint32_t val);
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97 | 1e78bcc1 | Alexander Graf | void stq_le_phys(target_phys_addr_t addr, uint64_t val);
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98 | 1e78bcc1 | Alexander Graf | void stq_be_phys(target_phys_addr_t addr, uint64_t val);
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99 | c227f099 | Anthony Liguori | |
100 | 21673cde | Blue Swirl | #ifdef NEED_CPU_H
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101 | 21673cde | Blue Swirl | uint32_t lduw_phys(target_phys_addr_t addr); |
102 | 21673cde | Blue Swirl | uint32_t ldl_phys(target_phys_addr_t addr); |
103 | 21673cde | Blue Swirl | uint64_t ldq_phys(target_phys_addr_t addr); |
104 | 21673cde | Blue Swirl | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
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105 | 21673cde | Blue Swirl | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
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106 | 21673cde | Blue Swirl | void stw_phys(target_phys_addr_t addr, uint32_t val);
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107 | 21673cde | Blue Swirl | void stl_phys(target_phys_addr_t addr, uint32_t val);
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108 | 21673cde | Blue Swirl | void stq_phys(target_phys_addr_t addr, uint64_t val);
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109 | 21673cde | Blue Swirl | #endif
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110 | 21673cde | Blue Swirl | |
111 | c227f099 | Anthony Liguori | void cpu_physical_memory_write_rom(target_phys_addr_t addr,
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112 | 1ad2134f | Paul Brook | const uint8_t *buf, int len); |
113 | 1ad2134f | Paul Brook | |
114 | 0e0df1e2 | Avi Kivity | extern struct MemoryRegion io_mem_ram; |
115 | 0e0df1e2 | Avi Kivity | extern struct MemoryRegion io_mem_rom; |
116 | 0e0df1e2 | Avi Kivity | extern struct MemoryRegion io_mem_unassigned; |
117 | 0e0df1e2 | Avi Kivity | extern struct MemoryRegion io_mem_notdirty; |
118 | 1ad2134f | Paul Brook | |
119 | b3755a91 | Paul Brook | #endif
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120 | b3755a91 | Paul Brook | |
121 | 1ad2134f | Paul Brook | #endif /* !CPU_COMMON_H */ |