root / hw / acpi / piix4.c @ e4f308bb
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/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "hw/hw.h" |
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#include "hw/i386/pc.h" |
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#include "hw/isa/apm.h" |
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#include "hw/i2c/pm_smbus.h" |
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#include "hw/pci/pci.h" |
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#include "hw/acpi/acpi.h" |
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#include "sysemu/sysemu.h" |
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#include "qemu/range.h" |
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#include "exec/ioport.h" |
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#include "hw/nvram/fw_cfg.h" |
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#include "exec/address-spaces.h" |
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#include "hw/acpi/piix4.h" |
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//#define DEBUG
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#ifdef DEBUG
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# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
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#else
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# define PIIX4_DPRINTF(format, ...) do { } while (0) |
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#endif
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#define GPE_BASE 0xafe0 |
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#define GPE_LEN 4 |
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#define PCI_HOTPLUG_ADDR 0xae00 |
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#define PCI_HOTPLUG_SIZE 0x000f |
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#define PCI_UP_BASE 0xae00 |
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#define PCI_DOWN_BASE 0xae04 |
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#define PCI_EJ_BASE 0xae08 |
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#define PCI_RMV_BASE 0xae0c |
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#define PIIX4_PROC_BASE 0xaf00 |
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#define PIIX4_PROC_LEN 32 |
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#define PIIX4_PCI_HOTPLUG_STATUS 2 |
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#define PIIX4_CPU_HOTPLUG_STATUS 4 |
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struct pci_status {
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uint32_t up; /* deprecated, maintained for migration compatibility */
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uint32_t down; |
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}; |
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typedef struct CPUStatus { |
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uint8_t sts[PIIX4_PROC_LEN]; |
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} CPUStatus; |
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typedef struct PIIX4PMState { |
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/*< private >*/
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PCIDevice parent_obj; |
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/*< public >*/
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MemoryRegion io; |
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uint32_t io_base; |
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MemoryRegion io_gpe; |
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MemoryRegion io_pci; |
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MemoryRegion io_cpu; |
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ACPIREGS ar; |
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APMState apm; |
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PMSMBus smb; |
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uint32_t smb_io_base; |
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qemu_irq irq; |
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qemu_irq smi_irq; |
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int kvm_enabled;
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Notifier machine_ready; |
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Notifier powerdown_notifier; |
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/* for pci hotplug */
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struct pci_status pci0_status;
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uint32_t pci0_hotplug_enable; |
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uint32_t pci0_slot_device_present; |
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uint8_t disable_s3; |
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uint8_t disable_s4; |
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uint8_t s4_val; |
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CPUStatus gpe_cpu; |
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Notifier cpu_added_notifier; |
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} PIIX4PMState; |
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#define TYPE_PIIX4_PM "PIIX4_PM" |
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#define PIIX4_PM(obj) \
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OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) |
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static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
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PCIBus *bus, PIIX4PMState *s); |
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#define ACPI_ENABLE 0xf1 |
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#define ACPI_DISABLE 0xf0 |
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static void pm_update_sci(PIIX4PMState *s) |
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{ |
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int sci_level, pmsts;
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pmsts = acpi_pm1_evt_get_sts(&s->ar); |
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sci_level = (((pmsts & s->ar.pm1.evt.en) & |
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(ACPI_BITMASK_RT_CLOCK_ENABLE | |
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ACPI_BITMASK_POWER_BUTTON_ENABLE | |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE | |
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ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
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((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) != 0); |
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qemu_set_irq(s->irq, sci_level); |
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/* schedule a timer interruption if needed */
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acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
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!(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
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} |
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static void pm_tmr_timer(ACPIREGS *ar) |
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{ |
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PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
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pm_update_sci(s); |
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} |
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static void apm_ctrl_changed(uint32_t val, void *arg) |
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{ |
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PIIX4PMState *s = arg; |
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PCIDevice *d = PCI_DEVICE(s); |
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/* ACPI specs 3.0, 4.7.2.5 */
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acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
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if (d->config[0x5b] & (1 << 1)) { |
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if (s->smi_irq) {
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qemu_irq_raise(s->smi_irq); |
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} |
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} |
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} |
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static void pm_io_space_update(PIIX4PMState *s) |
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{ |
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PCIDevice *d = PCI_DEVICE(s); |
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s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
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s->io_base &= 0xffc0;
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memory_region_transaction_begin(); |
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memory_region_set_enabled(&s->io, d->config[0x80] & 1); |
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memory_region_set_address(&s->io, s->io_base); |
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memory_region_transaction_commit(); |
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} |
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static void smbus_io_space_update(PIIX4PMState *s) |
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{ |
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PCIDevice *d = PCI_DEVICE(s); |
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s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
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s->smb_io_base &= 0xffc0;
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memory_region_transaction_begin(); |
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memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); |
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memory_region_set_address(&s->smb.io, s->smb_io_base); |
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memory_region_transaction_commit(); |
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} |
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static void pm_write_config(PCIDevice *d, |
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uint32_t address, uint32_t val, int len)
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{ |
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pci_default_write_config(d, address, val, len); |
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if (range_covers_byte(address, len, 0x80) || |
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ranges_overlap(address, len, 0x40, 4)) { |
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pm_io_space_update((PIIX4PMState *)d); |
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} |
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if (range_covers_byte(address, len, 0xd2) || |
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ranges_overlap(address, len, 0x90, 4)) { |
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smbus_io_space_update((PIIX4PMState *)d); |
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} |
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} |
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static void vmstate_pci_status_pre_save(void *opaque) |
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{ |
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struct pci_status *pci0_status = opaque;
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PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); |
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/* We no longer track up, so build a safe value for migrating
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* to a version that still does... of course these might get lost
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* by an old buggy implementation, but we try. */
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pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; |
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} |
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static int vmstate_acpi_post_load(void *opaque, int version_id) |
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{ |
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PIIX4PMState *s = opaque; |
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pm_io_space_update(s); |
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return 0; |
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} |
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#define VMSTATE_GPE_ARRAY(_field, _state) \
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{ \ |
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.name = (stringify(_field)), \ |
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.version_id = 0, \
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.info = &vmstate_info_uint16, \ |
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.size = sizeof(uint16_t), \
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.flags = VMS_SINGLE | VMS_POINTER, \ |
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.offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
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} |
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static const VMStateDescription vmstate_gpe = { |
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.name = "gpe",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
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VMSTATE_GPE_ARRAY(en, ACPIGPE), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_pci_status = { |
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.name = "pci_status",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.pre_save = vmstate_pci_status_pre_save, |
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.fields = (VMStateField []) { |
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VMSTATE_UINT32(up, struct pci_status),
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VMSTATE_UINT32(down, struct pci_status),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) |
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{ |
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PIIX4PMState *s = opaque; |
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int ret, i;
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uint16_t temp; |
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ret = pci_device_load(PCI_DEVICE(s), f); |
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if (ret < 0) { |
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return ret;
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} |
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qemu_get_be16s(f, &s->ar.pm1.evt.sts); |
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qemu_get_be16s(f, &s->ar.pm1.evt.en); |
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qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); |
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ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
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if (ret) {
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return ret;
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} |
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timer_get(f, s->ar.tmr.timer); |
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qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); |
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qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); |
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for (i = 0; i < 3; i++) { |
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qemu_get_be16s(f, &temp); |
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} |
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qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); |
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for (i = 0; i < 3; i++) { |
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qemu_get_be16s(f, &temp); |
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} |
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ret = vmstate_load_state(f, &vmstate_pci_status, &s->pci0_status, 1);
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return ret;
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} |
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/* qemu-kvm 1.2 uses version 3 but advertised as 2
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* To support incoming qemu-kvm 1.2 migration, change version_id
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* and minimum_version_id to 2 below (which breaks migration from
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* qemu 1.2).
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*
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*/
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static const VMStateDescription vmstate_acpi = { |
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.name = "piix4_pm",
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.version_id = 3,
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.minimum_version_id = 3,
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.minimum_version_id_old = 1,
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.load_state_old = acpi_load_old, |
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.post_load = vmstate_acpi_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), |
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VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
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VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), |
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VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), |
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VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
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VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), |
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VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
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VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
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struct pci_status),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) |
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{ |
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BusChild *kid, *next; |
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BusState *bus = qdev_get_parent_bus(DEVICE(s)); |
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int slot = ffs(slots) - 1; |
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bool slot_free = true; |
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/* Mark request as complete */
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s->pci0_status.down &= ~(1U << slot);
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QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
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DeviceState *qdev = kid->child; |
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PCIDevice *dev = PCI_DEVICE(qdev); |
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
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if (PCI_SLOT(dev->devfn) == slot) {
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if (pc->no_hotplug) {
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slot_free = false;
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} else {
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object_unparent(OBJECT(qdev)); |
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} |
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} |
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} |
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if (slot_free) {
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s->pci0_slot_device_present &= ~(1U << slot);
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} |
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} |
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static void piix4_update_hotplug(PIIX4PMState *s) |
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{ |
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BusState *bus = qdev_get_parent_bus(DEVICE(s)); |
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BusChild *kid, *next; |
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/* Execute any pending removes during reset */
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while (s->pci0_status.down) {
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acpi_piix_eject_slot(s, s->pci0_status.down); |
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} |
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s->pci0_hotplug_enable = ~0;
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s->pci0_slot_device_present = 0;
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QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
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DeviceState *qdev = kid->child; |
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PCIDevice *pdev = PCI_DEVICE(qdev); |
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); |
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int slot = PCI_SLOT(pdev->devfn);
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if (pc->no_hotplug) {
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s->pci0_hotplug_enable &= ~(1U << slot);
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} |
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s->pci0_slot_device_present |= (1U << slot);
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} |
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} |
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static void piix4_reset(void *opaque) |
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{ |
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PIIX4PMState *s = opaque; |
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PCIDevice *d = PCI_DEVICE(s); |
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uint8_t *pci_conf = d->config; |
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pci_conf[0x58] = 0; |
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pci_conf[0x59] = 0; |
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pci_conf[0x5a] = 0; |
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pci_conf[0x5b] = 0; |
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pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
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pci_conf[0x80] = 0; |
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if (s->kvm_enabled) {
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/* Mark SMM as already inited (until KVM supports SMM). */
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pci_conf[0x5B] = 0x02; |
383 |
} |
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pm_io_space_update(s); |
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piix4_update_hotplug(s); |
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} |
387 |
|
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static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
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{ |
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PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
391 |
|
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assert(s != NULL);
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acpi_pm1_evt_power_down(&s->ar); |
394 |
} |
395 |
|
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static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
397 |
{ |
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PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); |
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PCIDevice *d = PCI_DEVICE(s); |
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MemoryRegion *io_as = pci_address_space_io(d); |
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uint8_t *pci_conf; |
402 |
|
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pci_conf = d->config; |
404 |
pci_conf[0x5f] = 0x10 | |
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(memory_region_present(io_as, 0x378) ? 0x80 : 0); |
406 |
pci_conf[0x63] = 0x60; |
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pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | |
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(memory_region_present(io_as, 0x2f8) ? 0x90 : 0); |
409 |
} |
410 |
|
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static void piix4_pm_add_propeties(PIIX4PMState *s) |
412 |
{ |
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static const uint8_t acpi_enable_cmd = ACPI_ENABLE; |
414 |
static const uint8_t acpi_disable_cmd = ACPI_DISABLE; |
415 |
static const uint32_t gpe0_blk = GPE_BASE; |
416 |
static const uint32_t gpe0_blk_len = GPE_LEN; |
417 |
static const uint16_t sci_int = 9; |
418 |
|
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object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, |
420 |
&acpi_enable_cmd, NULL);
|
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object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, |
422 |
&acpi_disable_cmd, NULL);
|
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object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, |
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&gpe0_blk, NULL);
|
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object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, |
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&gpe0_blk_len, NULL);
|
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object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, |
428 |
&sci_int, NULL);
|
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object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, |
430 |
&s->io_base, NULL);
|
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} |
432 |
|
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static int piix4_pm_initfn(PCIDevice *dev) |
434 |
{ |
435 |
PIIX4PMState *s = PIIX4_PM(dev); |
436 |
uint8_t *pci_conf; |
437 |
|
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pci_conf = dev->config; |
439 |
pci_conf[0x06] = 0x80; |
440 |
pci_conf[0x07] = 0x02; |
441 |
pci_conf[0x09] = 0x00; |
442 |
pci_conf[0x3d] = 0x01; // interrupt pin 1 |
443 |
|
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/* APM */
|
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apm_init(dev, &s->apm, apm_ctrl_changed, s); |
446 |
|
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if (s->kvm_enabled) {
|
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/* Mark SMM as already inited to prevent SMM from running. KVM does not
|
449 |
* support SMM mode. */
|
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pci_conf[0x5B] = 0x02; |
451 |
} |
452 |
|
453 |
/* XXX: which specification is used ? The i82731AB has different
|
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mappings */
|
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pci_conf[0x90] = s->smb_io_base | 1; |
456 |
pci_conf[0x91] = s->smb_io_base >> 8; |
457 |
pci_conf[0xd2] = 0x09; |
458 |
pm_smbus_init(DEVICE(dev), &s->smb); |
459 |
memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); |
460 |
memory_region_add_subregion(pci_address_space_io(dev), |
461 |
s->smb_io_base, &s->smb.io); |
462 |
|
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memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); |
464 |
memory_region_set_enabled(&s->io, false);
|
465 |
memory_region_add_subregion(pci_address_space_io(dev), |
466 |
0, &s->io);
|
467 |
|
468 |
acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
469 |
acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
470 |
acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); |
471 |
acpi_gpe_init(&s->ar, GPE_LEN); |
472 |
|
473 |
s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
474 |
qemu_register_powerdown_notifier(&s->powerdown_notifier); |
475 |
|
476 |
s->machine_ready.notify = piix4_pm_machine_ready; |
477 |
qemu_add_machine_init_done_notifier(&s->machine_ready); |
478 |
qemu_register_reset(piix4_reset, s); |
479 |
|
480 |
piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); |
481 |
|
482 |
piix4_pm_add_propeties(s); |
483 |
return 0; |
484 |
} |
485 |
|
486 |
Object *piix4_pm_find(void)
|
487 |
{ |
488 |
bool ambig;
|
489 |
Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
|
490 |
|
491 |
if (ambig || !o) {
|
492 |
return NULL; |
493 |
} |
494 |
return o;
|
495 |
} |
496 |
|
497 |
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
498 |
qemu_irq sci_irq, qemu_irq smi_irq, |
499 |
int kvm_enabled, FWCfgState *fw_cfg)
|
500 |
{ |
501 |
DeviceState *dev; |
502 |
PIIX4PMState *s; |
503 |
|
504 |
dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); |
505 |
qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
|
506 |
|
507 |
s = PIIX4_PM(dev); |
508 |
s->irq = sci_irq; |
509 |
s->smi_irq = smi_irq; |
510 |
s->kvm_enabled = kvm_enabled; |
511 |
|
512 |
qdev_init_nofail(dev); |
513 |
|
514 |
if (fw_cfg) {
|
515 |
uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; |
516 |
suspend[3] = 1 | ((!s->disable_s3) << 7); |
517 |
suspend[4] = s->s4_val | ((!s->disable_s4) << 7); |
518 |
|
519 |
fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); |
520 |
} |
521 |
|
522 |
return s->smb.smbus;
|
523 |
} |
524 |
|
525 |
static Property piix4_pm_properties[] = {
|
526 |
DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), |
527 |
DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
|
528 |
DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
|
529 |
DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
|
530 |
DEFINE_PROP_END_OF_LIST(), |
531 |
}; |
532 |
|
533 |
static void piix4_pm_class_init(ObjectClass *klass, void *data) |
534 |
{ |
535 |
DeviceClass *dc = DEVICE_CLASS(klass); |
536 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
537 |
|
538 |
k->no_hotplug = 1;
|
539 |
k->init = piix4_pm_initfn; |
540 |
k->config_write = pm_write_config; |
541 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
542 |
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; |
543 |
k->revision = 0x03;
|
544 |
k->class_id = PCI_CLASS_BRIDGE_OTHER; |
545 |
dc->desc = "PM";
|
546 |
dc->no_user = 1;
|
547 |
dc->vmsd = &vmstate_acpi; |
548 |
dc->props = piix4_pm_properties; |
549 |
} |
550 |
|
551 |
static const TypeInfo piix4_pm_info = { |
552 |
.name = TYPE_PIIX4_PM, |
553 |
.parent = TYPE_PCI_DEVICE, |
554 |
.instance_size = sizeof(PIIX4PMState),
|
555 |
.class_init = piix4_pm_class_init, |
556 |
}; |
557 |
|
558 |
static void piix4_pm_register_types(void) |
559 |
{ |
560 |
type_register_static(&piix4_pm_info); |
561 |
} |
562 |
|
563 |
type_init(piix4_pm_register_types) |
564 |
|
565 |
static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) |
566 |
{ |
567 |
PIIX4PMState *s = opaque; |
568 |
uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
569 |
|
570 |
PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); |
571 |
return val;
|
572 |
} |
573 |
|
574 |
static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, |
575 |
unsigned width)
|
576 |
{ |
577 |
PIIX4PMState *s = opaque; |
578 |
|
579 |
acpi_gpe_ioport_writeb(&s->ar, addr, val); |
580 |
pm_update_sci(s); |
581 |
|
582 |
PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); |
583 |
} |
584 |
|
585 |
static const MemoryRegionOps piix4_gpe_ops = { |
586 |
.read = gpe_readb, |
587 |
.write = gpe_writeb, |
588 |
.valid.min_access_size = 1,
|
589 |
.valid.max_access_size = 4,
|
590 |
.impl.min_access_size = 1,
|
591 |
.impl.max_access_size = 1,
|
592 |
.endianness = DEVICE_LITTLE_ENDIAN, |
593 |
}; |
594 |
|
595 |
static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) |
596 |
{ |
597 |
PIIX4PMState *s = opaque; |
598 |
uint32_t val = 0;
|
599 |
|
600 |
switch (addr) {
|
601 |
case PCI_UP_BASE - PCI_HOTPLUG_ADDR:
|
602 |
/* Manufacture an "up" value to cause a device check on any hotplug
|
603 |
* slot with a device. Extra device checks are harmless. */
|
604 |
val = s->pci0_slot_device_present & s->pci0_hotplug_enable; |
605 |
PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val); |
606 |
break;
|
607 |
case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR:
|
608 |
val = s->pci0_status.down; |
609 |
PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val); |
610 |
break;
|
611 |
case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
|
612 |
/* No feature defined yet */
|
613 |
PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val); |
614 |
break;
|
615 |
case PCI_RMV_BASE - PCI_HOTPLUG_ADDR:
|
616 |
val = s->pci0_hotplug_enable; |
617 |
break;
|
618 |
default:
|
619 |
break;
|
620 |
} |
621 |
|
622 |
return val;
|
623 |
} |
624 |
|
625 |
static void pci_write(void *opaque, hwaddr addr, uint64_t data, |
626 |
unsigned int size) |
627 |
{ |
628 |
switch (addr) {
|
629 |
case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
|
630 |
acpi_piix_eject_slot(opaque, (uint32_t)data); |
631 |
PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", |
632 |
addr, data); |
633 |
break;
|
634 |
default:
|
635 |
break;
|
636 |
} |
637 |
} |
638 |
|
639 |
static const MemoryRegionOps piix4_pci_ops = { |
640 |
.read = pci_read, |
641 |
.write = pci_write, |
642 |
.endianness = DEVICE_LITTLE_ENDIAN, |
643 |
.valid = { |
644 |
.min_access_size = 4,
|
645 |
.max_access_size = 4,
|
646 |
}, |
647 |
}; |
648 |
|
649 |
static uint64_t cpu_status_read(void *opaque, hwaddr addr, unsigned int size) |
650 |
{ |
651 |
PIIX4PMState *s = opaque; |
652 |
CPUStatus *cpus = &s->gpe_cpu; |
653 |
uint64_t val = cpus->sts[addr]; |
654 |
|
655 |
return val;
|
656 |
} |
657 |
|
658 |
static void cpu_status_write(void *opaque, hwaddr addr, uint64_t data, |
659 |
unsigned int size) |
660 |
{ |
661 |
/* TODO: implement VCPU removal on guest signal that CPU can be removed */
|
662 |
} |
663 |
|
664 |
static const MemoryRegionOps cpu_hotplug_ops = { |
665 |
.read = cpu_status_read, |
666 |
.write = cpu_status_write, |
667 |
.endianness = DEVICE_LITTLE_ENDIAN, |
668 |
.valid = { |
669 |
.min_access_size = 1,
|
670 |
.max_access_size = 1,
|
671 |
}, |
672 |
}; |
673 |
|
674 |
typedef enum { |
675 |
PLUG, |
676 |
UNPLUG, |
677 |
} HotplugEventType; |
678 |
|
679 |
static void piix4_cpu_hotplug_req(PIIX4PMState *s, CPUState *cpu, |
680 |
HotplugEventType action) |
681 |
{ |
682 |
CPUStatus *g = &s->gpe_cpu; |
683 |
ACPIGPE *gpe = &s->ar.gpe; |
684 |
CPUClass *k = CPU_GET_CLASS(cpu); |
685 |
int64_t cpu_id; |
686 |
|
687 |
assert(s != NULL);
|
688 |
|
689 |
*gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS; |
690 |
cpu_id = k->get_arch_id(CPU(cpu)); |
691 |
if (action == PLUG) {
|
692 |
g->sts[cpu_id / 8] |= (1 << (cpu_id % 8)); |
693 |
} else {
|
694 |
g->sts[cpu_id / 8] &= ~(1 << (cpu_id % 8)); |
695 |
} |
696 |
pm_update_sci(s); |
697 |
} |
698 |
|
699 |
static void piix4_cpu_added_req(Notifier *n, void *opaque) |
700 |
{ |
701 |
PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier); |
702 |
|
703 |
piix4_cpu_hotplug_req(s, CPU(opaque), PLUG); |
704 |
} |
705 |
|
706 |
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
707 |
PCIHotplugState state); |
708 |
|
709 |
static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
710 |
PCIBus *bus, PIIX4PMState *s) |
711 |
{ |
712 |
CPUState *cpu; |
713 |
|
714 |
memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, |
715 |
"acpi-gpe0", GPE_LEN);
|
716 |
memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); |
717 |
|
718 |
memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s, |
719 |
"acpi-pci-hotplug", PCI_HOTPLUG_SIZE);
|
720 |
memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR, |
721 |
&s->io_pci); |
722 |
pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s)); |
723 |
|
724 |
CPU_FOREACH(cpu) { |
725 |
CPUClass *cc = CPU_GET_CLASS(cpu); |
726 |
int64_t id = cc->get_arch_id(cpu); |
727 |
|
728 |
g_assert((id / 8) < PIIX4_PROC_LEN);
|
729 |
s->gpe_cpu.sts[id / 8] |= (1 << (id % 8)); |
730 |
} |
731 |
memory_region_init_io(&s->io_cpu, OBJECT(s), &cpu_hotplug_ops, s, |
732 |
"acpi-cpu-hotplug", PIIX4_PROC_LEN);
|
733 |
memory_region_add_subregion(parent, PIIX4_PROC_BASE, &s->io_cpu); |
734 |
s->cpu_added_notifier.notify = piix4_cpu_added_req; |
735 |
qemu_register_cpu_added_notifier(&s->cpu_added_notifier); |
736 |
} |
737 |
|
738 |
static void enable_device(PIIX4PMState *s, int slot) |
739 |
{ |
740 |
s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
|
741 |
s->pci0_slot_device_present |= (1U << slot);
|
742 |
} |
743 |
|
744 |
static void disable_device(PIIX4PMState *s, int slot) |
745 |
{ |
746 |
s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
|
747 |
s->pci0_status.down |= (1U << slot);
|
748 |
} |
749 |
|
750 |
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
751 |
PCIHotplugState state) |
752 |
{ |
753 |
int slot = PCI_SLOT(dev->devfn);
|
754 |
PIIX4PMState *s = PIIX4_PM(qdev); |
755 |
|
756 |
/* Don't send event when device is enabled during qemu machine creation:
|
757 |
* it is present on boot, no hotplug event is necessary. We do send an
|
758 |
* event when the device is disabled later. */
|
759 |
if (state == PCI_COLDPLUG_ENABLED) {
|
760 |
s->pci0_slot_device_present |= (1U << slot);
|
761 |
return 0; |
762 |
} |
763 |
|
764 |
if (state == PCI_HOTPLUG_ENABLED) {
|
765 |
enable_device(s, slot); |
766 |
} else {
|
767 |
disable_device(s, slot); |
768 |
} |
769 |
|
770 |
pm_update_sci(s); |
771 |
|
772 |
return 0; |
773 |
} |