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/*
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* QEMU i8255x (PRO100) emulation
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*
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* Copyright (C) 2006-2011 Stefan Weil
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*
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* Portions of the code are copies from grub / etherboot eepro100.c
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* and linux e100.c.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) version 3 or any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Tested features (i82559):
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* PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
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* Linux networking (i386) ok
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*
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* Untested:
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* Windows networking
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*
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* References:
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*
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* Intel 8255x 10/100 Mbps Ethernet Controller Family
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* Open Source Software Developer Manual
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*
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* TODO:
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* * PHY emulation should be separated from nic emulation.
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* Most nic emulations could share the same phy code.
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* * i82550 is untested. It is programmed like the i82559.
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* * i82562 is untested. It is programmed like the i82559.
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* * Power management (i82558 and later) is not implemented.
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* * Wake-on-LAN is not implemented.
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*/
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#include <stddef.h> /* offsetof */ |
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#include "hw.h" |
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#include "pci.h" |
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#include "net.h" |
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#include "eeprom93xx.h" |
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#include "sysemu.h" |
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/* QEMU sends frames smaller than 60 bytes to ethernet nics.
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* Such frames are rejected by real nics and their emulations.
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* To avoid this behaviour, other nic emulations pad received
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* frames. The following definition enables this padding for
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* eepro100, too. We keep the define around in case it might
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* become useful the future if the core networking is ever
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* changed to pad short packets itself. */
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#define CONFIG_PAD_RECEIVED_FRAMES
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#define KiB 1024 |
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/* Debug EEPRO100 card. */
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#if 0
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# define DEBUG_EEPRO100
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#endif
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#ifdef DEBUG_EEPRO100
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#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
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#else
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#define logout(fmt, ...) ((void)0) |
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#endif
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/* Set flags to 0 to disable debug output. */
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#define INT 1 /* interrupt related actions */ |
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#define MDI 1 /* mdi related actions */ |
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#define OTHER 1 |
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#define RXTX 1 |
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#define EEPROM 1 /* eeprom related actions */ |
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#define TRACE(flag, command) ((flag) ? (command) : (void)0) |
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#define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n") |
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#define MAX_ETH_FRAME_SIZE 1514 |
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/* This driver supports several different devices which are declared here. */
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#define i82550 0x82550 |
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#define i82551 0x82551 |
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#define i82557A 0x82557a |
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#define i82557B 0x82557b |
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#define i82557C 0x82557c |
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#define i82558A 0x82558a |
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#define i82558B 0x82558b |
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#define i82559A 0x82559a |
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#define i82559B 0x82559b |
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#define i82559C 0x82559c |
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#define i82559ER 0x82559e |
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#define i82562 0x82562 |
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#define i82801 0x82801 |
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|
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/* Use 64 word EEPROM. TODO: could be a runtime option. */
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#define EEPROM_SIZE 64 |
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#define PCI_MEM_SIZE (4 * KiB) |
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#define PCI_IO_SIZE 64 |
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#define PCI_FLASH_SIZE (128 * KiB) |
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#define BIT(n) (1 << (n)) |
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#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) |
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/* The SCB accepts the following controls for the Tx and Rx units: */
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#define CU_NOP 0x0000 /* No operation. */ |
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#define CU_START 0x0010 /* CU start. */ |
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#define CU_RESUME 0x0020 /* CU resume. */ |
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#define CU_STATSADDR 0x0040 /* Load dump counters address. */ |
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#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ |
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#define CU_CMD_BASE 0x0060 /* Load CU base address. */ |
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#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ |
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#define CU_SRESUME 0x00a0 /* CU static resume. */ |
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#define RU_NOP 0x0000 |
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#define RX_START 0x0001 |
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#define RX_RESUME 0x0002 |
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#define RU_ABORT 0x0004 |
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#define RX_ADDR_LOAD 0x0006 |
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#define RX_RESUMENR 0x0007 |
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#define INT_MASK 0x0100 |
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#define DRVR_INT 0x0200 /* Driver generated interrupt. */ |
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typedef struct { |
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PCIDeviceInfo pci; |
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uint32_t device; |
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uint16_t device_id; |
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uint8_t revision; |
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uint8_t stats_size; |
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bool has_extended_tcb_support;
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bool power_management;
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} E100PCIDeviceInfo; |
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/* Offsets to the various registers.
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All accesses need not be longword aligned. */
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typedef enum { |
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SCBStatus = 0, /* Status Word. */ |
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SCBAck = 1,
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SCBCmd = 2, /* Rx/Command Unit command and status. */ |
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SCBIntmask = 3,
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SCBPointer = 4, /* General purpose pointer. */ |
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SCBPort = 8, /* Misc. commands and operands. */ |
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SCBflash = 12, /* Flash memory control. */ |
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SCBeeprom = 14, /* EEPROM control. */ |
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SCBCtrlMDI = 16, /* MDI interface control. */ |
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SCBEarlyRx = 20, /* Early receive byte count. */ |
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SCBFlow = 24, /* Flow Control. */ |
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SCBpmdr = 27, /* Power Management Driver. */ |
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SCBgctrl = 28, /* General Control. */ |
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SCBgstat = 29, /* General Status. */ |
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} E100RegisterOffset; |
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/* A speedo3 transmit buffer descriptor with two buffers... */
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typedef struct { |
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uint16_t status; |
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uint16_t command; |
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uint32_t link; /* void * */
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uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
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uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
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uint8_t tx_threshold; /* transmit threshold */
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uint8_t tbd_count; /* TBD number */
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#if 0
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/* This constitutes two "TBD" entries: hdr and data */
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uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
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int32_t tx_buf_size0; /* Length of Tx hdr. */
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uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
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int32_t tx_buf_size1; /* Length of Tx data. */
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#endif
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} eepro100_tx_t; |
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/* Receive frame descriptor. */
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typedef struct { |
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int16_t status; |
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uint16_t command; |
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uint32_t link; /* struct RxFD * */
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uint32_t rx_buf_addr; /* void * */
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uint16_t count; |
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uint16_t size; |
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/* Ethernet frame data follows. */
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} eepro100_rx_t; |
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typedef enum { |
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COMMAND_EL = BIT(15),
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COMMAND_S = BIT(14),
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COMMAND_I = BIT(13),
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COMMAND_NC = BIT(4),
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COMMAND_SF = BIT(3),
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COMMAND_CMD = BITS(2, 0), |
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} scb_command_bit; |
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typedef enum { |
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STATUS_C = BIT(15),
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STATUS_OK = BIT(13),
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} scb_status_bit; |
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typedef struct { |
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uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, |
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tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, |
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tx_multiple_collisions, tx_total_collisions; |
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uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, |
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rx_resource_errors, rx_overrun_errors, rx_cdt_errors, |
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rx_short_frame_errors; |
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uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; |
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uint16_t xmt_tco_frames, rcv_tco_frames; |
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/* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
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uint32_t reserved[4];
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} eepro100_stats_t; |
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typedef enum { |
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cu_idle = 0,
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cu_suspended = 1,
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cu_active = 2,
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cu_lpq_active = 2,
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cu_hqp_active = 3
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} cu_state_t; |
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typedef enum { |
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ru_idle = 0,
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ru_suspended = 1,
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ru_no_resources = 2,
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ru_ready = 4
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} ru_state_t; |
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typedef struct { |
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PCIDevice dev; |
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/* Hash register (multicast mask array, multiple individual addresses). */
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uint8_t mult[8];
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int mmio_index;
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NICState *nic; |
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NICConf conf; |
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uint8_t scb_stat; /* SCB stat/ack byte */
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uint8_t int_stat; /* PCI interrupt status */
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/* region must not be saved by nic_save. */
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uint32_t region1; /* PCI region 1 address */
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uint16_t mdimem[32];
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eeprom_t *eeprom; |
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uint32_t device; /* device variant */
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uint32_t pointer; |
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/* (cu_base + cu_offset) address the next command block in the command block list. */
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uint32_t cu_base; /* CU base address */
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uint32_t cu_offset; /* CU address offset */
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/* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
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uint32_t ru_base; /* RU base address */
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uint32_t ru_offset; /* RU address offset */
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uint32_t statsaddr; /* pointer to eepro100_stats_t */
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/* Temporary status information (no need to save these values),
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* used while processing CU commands. */
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eepro100_tx_t tx; /* transmit buffer descriptor */
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uint32_t cb_address; /* = cu_base + cu_offset */
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/* Statistical counters. Also used for wake-up packet (i82559). */
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eepro100_stats_t statistics; |
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/* Data in mem is always in the byte order of the controller (le).
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* It must be dword aligned to allow direct access to 32 bit values. */
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uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));;
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/* Configuration bytes. */
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uint8_t configuration[22];
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/* vmstate for each particular nic */
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VMStateDescription *vmstate; |
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/* Quasi static device properties (no need to save them). */
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uint16_t stats_size; |
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bool has_extended_tcb_support;
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} EEPRO100State; |
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/* Word indices in EEPROM. */
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typedef enum { |
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EEPROM_CNFG_MDIX = 0x03,
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EEPROM_ID = 0x05,
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EEPROM_PHY_ID = 0x06,
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EEPROM_VENDOR_ID = 0x0c,
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EEPROM_CONFIG_ASF = 0x0d,
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EEPROM_DEVICE_ID = 0x23,
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EEPROM_SMBUS_ADDR = 0x90,
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} EEPROMOffset; |
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/* Bit values for EEPROM ID word. */
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typedef enum { |
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EEPROM_ID_MDM = BIT(0), /* Modem */ |
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EEPROM_ID_STB = BIT(1), /* Standby Enable */ |
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EEPROM_ID_WMR = BIT(2), /* ??? */ |
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EEPROM_ID_WOL = BIT(5), /* Wake on LAN */ |
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EEPROM_ID_DPD = BIT(6), /* Deep Power Down */ |
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EEPROM_ID_ALT = BIT(7), /* */ |
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/* BITS(10, 8) device revision */
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EEPROM_ID_BD = BIT(11), /* boot disable */ |
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EEPROM_ID_ID = BIT(13), /* id bit */ |
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/* BITS(15, 14) signature */
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EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */ |
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} eeprom_id_bit; |
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/* Default values for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_default[] = { |
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/* MDI Registers 0 - 6, 7 */
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0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, |
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/* MDI Registers 8 - 15 */
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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/* MDI Registers 16 - 31 */
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0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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}; |
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/* Readonly mask for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_mask[] = { |
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0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, |
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, |
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0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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}; |
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/* Read a 16 bit little endian value from physical memory. */
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static uint16_t e100_ldw_le_phys(target_phys_addr_t addr)
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{ |
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/* Load 16 bit (little endian) word from emulated hardware. */
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uint16_t val; |
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cpu_physical_memory_read(addr, &val, sizeof(val));
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return le16_to_cpu(val);
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} |
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|
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/* Read a 32 bit little endian value from physical memory. */
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static uint32_t e100_ldl_le_phys(target_phys_addr_t addr)
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{ |
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/* Load 32 bit (little endian) word from emulated hardware. */
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uint32_t val; |
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cpu_physical_memory_read(addr, &val, sizeof(val));
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return le32_to_cpu(val);
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} |
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|
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/* Write a 16 bit little endian value to physical memory. */
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static void e100_stw_le_phys(target_phys_addr_t addr, uint16_t val) |
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{ |
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val = cpu_to_le16(val); |
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cpu_physical_memory_write(addr, &val, sizeof(val));
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} |
344 |
|
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/* Write a 32 bit little endian value to physical memory. */
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static void e100_stl_le_phys(target_phys_addr_t addr, uint32_t val) |
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{ |
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val = cpu_to_le32(val); |
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cpu_physical_memory_write(addr, &val, sizeof(val));
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} |
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|
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#define POLYNOMIAL 0x04c11db6 |
353 |
|
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/* From FreeBSD */
|
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/* XXX: optimize */
|
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static unsigned compute_mcast_idx(const uint8_t * ep) |
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{ |
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uint32_t crc; |
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int carry, i, j;
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uint8_t b; |
361 |
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crc = 0xffffffff;
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for (i = 0; i < 6; i++) { |
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b = *ep++; |
365 |
for (j = 0; j < 8; j++) { |
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carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
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crc <<= 1;
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b >>= 1;
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if (carry) {
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crc = ((crc ^ POLYNOMIAL) | carry); |
371 |
} |
372 |
} |
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} |
374 |
return (crc & BITS(7, 2)) >> 2; |
375 |
} |
376 |
|
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/* Read a 16 bit control/status (CSR) register. */
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static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
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{ |
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assert(!((uintptr_t)&s->mem[addr] & 1));
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return le16_to_cpup((uint16_t *)&s->mem[addr]);
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} |
383 |
|
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/* Read a 32 bit control/status (CSR) register. */
|
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static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
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{ |
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assert(!((uintptr_t)&s->mem[addr] & 3));
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return le32_to_cpup((uint32_t *)&s->mem[addr]);
|
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} |
390 |
|
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/* Write a 16 bit control/status (CSR) register. */
|
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static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr, |
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uint16_t val) |
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{ |
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assert(!((uintptr_t)&s->mem[addr] & 1));
|
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cpu_to_le16w((uint16_t *)&s->mem[addr], val); |
397 |
} |
398 |
|
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/* Read a 32 bit control/status (CSR) register. */
|
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static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr, |
401 |
uint32_t val) |
402 |
{ |
403 |
assert(!((uintptr_t)&s->mem[addr] & 3));
|
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cpu_to_le32w((uint32_t *)&s->mem[addr], val); |
405 |
} |
406 |
|
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#if defined(DEBUG_EEPRO100)
|
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static const char *nic_dump(const uint8_t * buf, unsigned size) |
409 |
{ |
410 |
static char dump[3 * 16 + 1]; |
411 |
char *p = &dump[0]; |
412 |
if (size > 16) { |
413 |
size = 16;
|
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} |
415 |
while (size-- > 0) { |
416 |
p += sprintf(p, " %02x", *buf++);
|
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} |
418 |
return dump;
|
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} |
420 |
#endif /* DEBUG_EEPRO100 */ |
421 |
|
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enum scb_stat_ack {
|
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stat_ack_not_ours = 0x00,
|
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stat_ack_sw_gen = 0x04,
|
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stat_ack_rnr = 0x10,
|
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stat_ack_cu_idle = 0x20,
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stat_ack_frame_rx = 0x40,
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stat_ack_cu_cmd_done = 0x80,
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stat_ack_not_present = 0xFF,
|
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stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), |
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stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), |
432 |
}; |
433 |
|
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static void disable_interrupt(EEPRO100State * s) |
435 |
{ |
436 |
if (s->int_stat) {
|
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TRACE(INT, logout("interrupt disabled\n"));
|
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qemu_irq_lower(s->dev.irq[0]);
|
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s->int_stat = 0;
|
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} |
441 |
} |
442 |
|
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static void enable_interrupt(EEPRO100State * s) |
444 |
{ |
445 |
if (!s->int_stat) {
|
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TRACE(INT, logout("interrupt enabled\n"));
|
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qemu_irq_raise(s->dev.irq[0]);
|
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s->int_stat = 1;
|
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} |
450 |
} |
451 |
|
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static void eepro100_acknowledge(EEPRO100State * s) |
453 |
{ |
454 |
s->scb_stat &= ~s->mem[SCBAck]; |
455 |
s->mem[SCBAck] = s->scb_stat; |
456 |
if (s->scb_stat == 0) { |
457 |
disable_interrupt(s); |
458 |
} |
459 |
} |
460 |
|
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static void eepro100_interrupt(EEPRO100State * s, uint8_t status) |
462 |
{ |
463 |
uint8_t mask = ~s->mem[SCBIntmask]; |
464 |
s->mem[SCBAck] |= status; |
465 |
status = s->scb_stat = s->mem[SCBAck]; |
466 |
status &= (mask | 0x0f);
|
467 |
#if 0
|
468 |
status &= (~s->mem[SCBIntmask] | 0x0xf);
|
469 |
#endif
|
470 |
if (status && (mask & 0x01)) { |
471 |
/* SCB mask and SCB Bit M do not disable interrupt. */
|
472 |
enable_interrupt(s); |
473 |
} else if (s->int_stat) { |
474 |
disable_interrupt(s); |
475 |
} |
476 |
} |
477 |
|
478 |
static void eepro100_cx_interrupt(EEPRO100State * s) |
479 |
{ |
480 |
/* CU completed action command. */
|
481 |
/* Transmit not ok (82557 only, not in emulation). */
|
482 |
eepro100_interrupt(s, 0x80);
|
483 |
} |
484 |
|
485 |
static void eepro100_cna_interrupt(EEPRO100State * s) |
486 |
{ |
487 |
/* CU left the active state. */
|
488 |
eepro100_interrupt(s, 0x20);
|
489 |
} |
490 |
|
491 |
static void eepro100_fr_interrupt(EEPRO100State * s) |
492 |
{ |
493 |
/* RU received a complete frame. */
|
494 |
eepro100_interrupt(s, 0x40);
|
495 |
} |
496 |
|
497 |
static void eepro100_rnr_interrupt(EEPRO100State * s) |
498 |
{ |
499 |
/* RU is not ready. */
|
500 |
eepro100_interrupt(s, 0x10);
|
501 |
} |
502 |
|
503 |
static void eepro100_mdi_interrupt(EEPRO100State * s) |
504 |
{ |
505 |
/* MDI completed read or write cycle. */
|
506 |
eepro100_interrupt(s, 0x08);
|
507 |
} |
508 |
|
509 |
static void eepro100_swi_interrupt(EEPRO100State * s) |
510 |
{ |
511 |
/* Software has requested an interrupt. */
|
512 |
eepro100_interrupt(s, 0x04);
|
513 |
} |
514 |
|
515 |
#if 0
|
516 |
static void eepro100_fcp_interrupt(EEPRO100State * s)
|
517 |
{
|
518 |
/* Flow control pause interrupt (82558 and later). */
|
519 |
eepro100_interrupt(s, 0x01);
|
520 |
}
|
521 |
#endif
|
522 |
|
523 |
static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device) |
524 |
{ |
525 |
uint32_t device = s->device; |
526 |
uint8_t *pci_conf = s->dev.config; |
527 |
|
528 |
TRACE(OTHER, logout("%p\n", s));
|
529 |
|
530 |
/* PCI Vendor ID */
|
531 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
532 |
/* PCI Device ID */
|
533 |
pci_config_set_device_id(pci_conf, e100_device->device_id); |
534 |
/* PCI Status */
|
535 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
536 |
PCI_STATUS_FAST_BACK); |
537 |
/* PCI Revision ID */
|
538 |
pci_config_set_revision(pci_conf, e100_device->revision); |
539 |
pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
540 |
/* PCI Latency Timer */
|
541 |
pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */ |
542 |
/* Capability Pointer is set by PCI framework. */
|
543 |
/* Interrupt Line */
|
544 |
/* Interrupt Pin */
|
545 |
pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */ |
546 |
/* Minimum Grant */
|
547 |
pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
|
548 |
/* Maximum Latency */
|
549 |
pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
|
550 |
|
551 |
s->stats_size = e100_device->stats_size; |
552 |
s->has_extended_tcb_support = e100_device->has_extended_tcb_support; |
553 |
|
554 |
switch (device) {
|
555 |
case i82550:
|
556 |
case i82551:
|
557 |
case i82557A:
|
558 |
case i82557B:
|
559 |
case i82557C:
|
560 |
case i82558A:
|
561 |
case i82558B:
|
562 |
case i82559A:
|
563 |
case i82559B:
|
564 |
case i82559ER:
|
565 |
case i82562:
|
566 |
case i82801:
|
567 |
break;
|
568 |
case i82559C:
|
569 |
#if EEPROM_SIZE > 0 |
570 |
pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL); |
571 |
pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
|
572 |
#endif
|
573 |
break;
|
574 |
default:
|
575 |
logout("Device %X is undefined!\n", device);
|
576 |
} |
577 |
|
578 |
/* Standard TxCB. */
|
579 |
s->configuration[6] |= BIT(4); |
580 |
|
581 |
/* Standard statistical counters. */
|
582 |
s->configuration[6] |= BIT(5); |
583 |
|
584 |
if (s->stats_size == 80) { |
585 |
/* TODO: check TCO Statistical Counters bit. Documentation not clear. */
|
586 |
if (s->configuration[6] & BIT(2)) { |
587 |
/* TCO statistical counters. */
|
588 |
assert(s->configuration[6] & BIT(5)); |
589 |
} else {
|
590 |
if (s->configuration[6] & BIT(5)) { |
591 |
/* No extended statistical counters, i82557 compatible. */
|
592 |
s->stats_size = 64;
|
593 |
} else {
|
594 |
/* i82558 compatible. */
|
595 |
s->stats_size = 76;
|
596 |
} |
597 |
} |
598 |
} else {
|
599 |
if (s->configuration[6] & BIT(5)) { |
600 |
/* No extended statistical counters. */
|
601 |
s->stats_size = 64;
|
602 |
} |
603 |
} |
604 |
assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics)); |
605 |
|
606 |
if (e100_device->power_management) {
|
607 |
/* Power Management Capabilities */
|
608 |
int cfg_offset = 0xdc; |
609 |
int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
|
610 |
cfg_offset, PCI_PM_SIZEOF); |
611 |
assert(r >= 0);
|
612 |
pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
|
613 |
#if 0 /* TODO: replace dummy code for power management emulation. */
|
614 |
/* TODO: Power Management Control / Status. */
|
615 |
pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
|
616 |
/* TODO: Ethernet Power Consumption Registers (i82559 and later). */
|
617 |
pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
|
618 |
#endif
|
619 |
} |
620 |
|
621 |
#if EEPROM_SIZE > 0 |
622 |
if (device == i82557C || device == i82558B || device == i82559C) {
|
623 |
/*
|
624 |
TODO: get vendor id from EEPROM for i82557C or later.
|
625 |
TODO: get device id from EEPROM for i82557C or later.
|
626 |
TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
|
627 |
TODO: header type is determined by EEPROM for i82559.
|
628 |
TODO: get subsystem id from EEPROM for i82557C or later.
|
629 |
TODO: get subsystem vendor id from EEPROM for i82557C or later.
|
630 |
TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
|
631 |
TODO: capability pointer depends on EEPROM for i82558.
|
632 |
*/
|
633 |
logout("Get device id and revision from EEPROM!!!\n");
|
634 |
} |
635 |
#endif /* EEPROM_SIZE > 0 */ |
636 |
} |
637 |
|
638 |
static void nic_selective_reset(EEPRO100State * s) |
639 |
{ |
640 |
size_t i; |
641 |
uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); |
642 |
#if 0
|
643 |
eeprom93xx_reset(s->eeprom);
|
644 |
#endif
|
645 |
memcpy(eeprom_contents, s->conf.macaddr.a, 6);
|
646 |
eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID; |
647 |
if (s->device == i82557B || s->device == i82557C)
|
648 |
eeprom_contents[5] = 0x0100; |
649 |
eeprom_contents[EEPROM_PHY_ID] = 1;
|
650 |
uint16_t sum = 0;
|
651 |
for (i = 0; i < EEPROM_SIZE - 1; i++) { |
652 |
sum += eeprom_contents[i]; |
653 |
} |
654 |
eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; |
655 |
TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); |
656 |
|
657 |
memset(s->mem, 0, sizeof(s->mem)); |
658 |
e100_write_reg4(s, SCBCtrlMDI, BIT(21));
|
659 |
|
660 |
assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); |
661 |
memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); |
662 |
} |
663 |
|
664 |
static void nic_reset(void *opaque) |
665 |
{ |
666 |
EEPRO100State *s = opaque; |
667 |
TRACE(OTHER, logout("%p\n", s));
|
668 |
/* TODO: Clearing of hash register for selective reset, too? */
|
669 |
memset(&s->mult[0], 0, sizeof(s->mult)); |
670 |
nic_selective_reset(s); |
671 |
} |
672 |
|
673 |
#if defined(DEBUG_EEPRO100)
|
674 |
static const char * const e100_reg[PCI_IO_SIZE / 4] = { |
675 |
"Command/Status",
|
676 |
"General Pointer",
|
677 |
"Port",
|
678 |
"EEPROM/Flash Control",
|
679 |
"MDI Control",
|
680 |
"Receive DMA Byte Count",
|
681 |
"Flow Control",
|
682 |
"General Status/Control"
|
683 |
}; |
684 |
|
685 |
static char *regname(uint32_t addr) |
686 |
{ |
687 |
static char buf[32]; |
688 |
if (addr < PCI_IO_SIZE) {
|
689 |
const char *r = e100_reg[addr / 4]; |
690 |
if (r != 0) { |
691 |
snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); |
692 |
} else {
|
693 |
snprintf(buf, sizeof(buf), "0x%02x", addr); |
694 |
} |
695 |
} else {
|
696 |
snprintf(buf, sizeof(buf), "??? 0x%08x", addr); |
697 |
} |
698 |
return buf;
|
699 |
} |
700 |
#endif /* DEBUG_EEPRO100 */ |
701 |
|
702 |
/*****************************************************************************
|
703 |
*
|
704 |
* Command emulation.
|
705 |
*
|
706 |
****************************************************************************/
|
707 |
|
708 |
#if 0
|
709 |
static uint16_t eepro100_read_command(EEPRO100State * s)
|
710 |
{
|
711 |
uint16_t val = 0xffff;
|
712 |
TRACE(OTHER, logout("val=0x%04x\n", val));
|
713 |
return val;
|
714 |
}
|
715 |
#endif
|
716 |
|
717 |
/* Commands that can be put in a command list entry. */
|
718 |
enum commands {
|
719 |
CmdNOp = 0,
|
720 |
CmdIASetup = 1,
|
721 |
CmdConfigure = 2,
|
722 |
CmdMulticastList = 3,
|
723 |
CmdTx = 4,
|
724 |
CmdTDR = 5, /* load microcode */ |
725 |
CmdDump = 6,
|
726 |
CmdDiagnose = 7,
|
727 |
|
728 |
/* And some extra flags: */
|
729 |
CmdSuspend = 0x4000, /* Suspend after completion. */ |
730 |
CmdIntr = 0x2000, /* Interrupt after completion. */ |
731 |
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ |
732 |
}; |
733 |
|
734 |
static cu_state_t get_cu_state(EEPRO100State * s)
|
735 |
{ |
736 |
return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6); |
737 |
} |
738 |
|
739 |
static void set_cu_state(EEPRO100State * s, cu_state_t state) |
740 |
{ |
741 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6); |
742 |
} |
743 |
|
744 |
static ru_state_t get_ru_state(EEPRO100State * s)
|
745 |
{ |
746 |
return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2); |
747 |
} |
748 |
|
749 |
static void set_ru_state(EEPRO100State * s, ru_state_t state) |
750 |
{ |
751 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2); |
752 |
} |
753 |
|
754 |
static void dump_statistics(EEPRO100State * s) |
755 |
{ |
756 |
/* Dump statistical data. Most data is never changed by the emulation
|
757 |
* and always 0, so we first just copy the whole block and then those
|
758 |
* values which really matter.
|
759 |
* Number of data should check configuration!!!
|
760 |
*/
|
761 |
cpu_physical_memory_write(s->statsaddr, &s->statistics, s->stats_size); |
762 |
e100_stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
|
763 |
e100_stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
|
764 |
e100_stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
|
765 |
e100_stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
|
766 |
#if 0
|
767 |
e100_stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
|
768 |
e100_stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
|
769 |
missing("CU dump statistical counters");
|
770 |
#endif
|
771 |
} |
772 |
|
773 |
static void read_cb(EEPRO100State *s) |
774 |
{ |
775 |
cpu_physical_memory_read(s->cb_address, &s->tx, sizeof(s->tx));
|
776 |
s->tx.status = le16_to_cpu(s->tx.status); |
777 |
s->tx.command = le16_to_cpu(s->tx.command); |
778 |
s->tx.link = le32_to_cpu(s->tx.link); |
779 |
s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr); |
780 |
s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes); |
781 |
} |
782 |
|
783 |
static void tx_command(EEPRO100State *s) |
784 |
{ |
785 |
uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr); |
786 |
uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
|
787 |
/* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
|
788 |
uint8_t buf[2600];
|
789 |
uint16_t size = 0;
|
790 |
uint32_t tbd_address = s->cb_address + 0x10;
|
791 |
TRACE(RXTX, logout |
792 |
("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
|
793 |
tbd_array, tcb_bytes, s->tx.tbd_count)); |
794 |
|
795 |
if (tcb_bytes > 2600) { |
796 |
logout("TCB byte count too large, using 2600\n");
|
797 |
tcb_bytes = 2600;
|
798 |
} |
799 |
if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { |
800 |
logout |
801 |
("illegal values of TBD array address and TCB byte count!\n");
|
802 |
} |
803 |
assert(tcb_bytes <= sizeof(buf));
|
804 |
while (size < tcb_bytes) {
|
805 |
uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address); |
806 |
uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
|
807 |
#if 0
|
808 |
uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
|
809 |
#endif
|
810 |
tbd_address += 8;
|
811 |
TRACE(RXTX, logout |
812 |
("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
|
813 |
tx_buffer_address, tx_buffer_size)); |
814 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
815 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
816 |
tx_buffer_size); |
817 |
size += tx_buffer_size; |
818 |
} |
819 |
if (tbd_array == 0xffffffff) { |
820 |
/* Simplified mode. Was already handled by code above. */
|
821 |
} else {
|
822 |
/* Flexible mode. */
|
823 |
uint8_t tbd_count = 0;
|
824 |
if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { |
825 |
/* Extended Flexible TCB. */
|
826 |
for (; tbd_count < 2; tbd_count++) { |
827 |
uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address); |
828 |
uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
|
829 |
uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
|
830 |
tbd_address += 8;
|
831 |
TRACE(RXTX, logout |
832 |
("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
833 |
tx_buffer_address, tx_buffer_size)); |
834 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
835 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
836 |
tx_buffer_size); |
837 |
size += tx_buffer_size; |
838 |
if (tx_buffer_el & 1) { |
839 |
break;
|
840 |
} |
841 |
} |
842 |
} |
843 |
tbd_address = tbd_array; |
844 |
for (; tbd_count < s->tx.tbd_count; tbd_count++) {
|
845 |
uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address); |
846 |
uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
|
847 |
uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
|
848 |
tbd_address += 8;
|
849 |
TRACE(RXTX, logout |
850 |
("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
851 |
tx_buffer_address, tx_buffer_size)); |
852 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
853 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
854 |
tx_buffer_size); |
855 |
size += tx_buffer_size; |
856 |
if (tx_buffer_el & 1) { |
857 |
break;
|
858 |
} |
859 |
} |
860 |
} |
861 |
TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
|
862 |
qemu_send_packet(&s->nic->nc, buf, size); |
863 |
s->statistics.tx_good_frames++; |
864 |
/* Transmit with bad status would raise an CX/TNO interrupt.
|
865 |
* (82557 only). Emulation never has bad status. */
|
866 |
#if 0
|
867 |
eepro100_cx_interrupt(s);
|
868 |
#endif
|
869 |
} |
870 |
|
871 |
static void set_multicast_list(EEPRO100State *s) |
872 |
{ |
873 |
uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0); |
874 |
uint16_t i; |
875 |
memset(&s->mult[0], 0, sizeof(s->mult)); |
876 |
TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
|
877 |
for (i = 0; i < multicast_count; i += 6) { |
878 |
uint8_t multicast_addr[6];
|
879 |
cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6); |
880 |
TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6))); |
881 |
unsigned mcast_idx = compute_mcast_idx(multicast_addr);
|
882 |
assert(mcast_idx < 64);
|
883 |
s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7)); |
884 |
} |
885 |
} |
886 |
|
887 |
static void action_command(EEPRO100State *s) |
888 |
{ |
889 |
for (;;) {
|
890 |
bool bit_el;
|
891 |
bool bit_s;
|
892 |
bool bit_i;
|
893 |
bool bit_nc;
|
894 |
uint16_t ok_status = STATUS_OK; |
895 |
s->cb_address = s->cu_base + s->cu_offset; |
896 |
read_cb(s); |
897 |
bit_el = ((s->tx.command & COMMAND_EL) != 0);
|
898 |
bit_s = ((s->tx.command & COMMAND_S) != 0);
|
899 |
bit_i = ((s->tx.command & COMMAND_I) != 0);
|
900 |
bit_nc = ((s->tx.command & COMMAND_NC) != 0);
|
901 |
#if 0
|
902 |
bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
|
903 |
#endif
|
904 |
s->cu_offset = s->tx.link; |
905 |
TRACE(OTHER, |
906 |
logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
|
907 |
s->tx.status, s->tx.command, s->tx.link)); |
908 |
switch (s->tx.command & COMMAND_CMD) {
|
909 |
case CmdNOp:
|
910 |
/* Do nothing. */
|
911 |
break;
|
912 |
case CmdIASetup:
|
913 |
cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6); |
914 |
TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6))); |
915 |
break;
|
916 |
case CmdConfigure:
|
917 |
cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0], |
918 |
sizeof(s->configuration));
|
919 |
TRACE(OTHER, logout("configuration: %s\n",
|
920 |
nic_dump(&s->configuration[0], 16))); |
921 |
TRACE(OTHER, logout("configuration: %s\n",
|
922 |
nic_dump(&s->configuration[16],
|
923 |
ARRAY_SIZE(s->configuration) - 16)));
|
924 |
if (s->configuration[20] & BIT(6)) { |
925 |
TRACE(OTHER, logout("Multiple IA bit\n"));
|
926 |
} |
927 |
break;
|
928 |
case CmdMulticastList:
|
929 |
set_multicast_list(s); |
930 |
break;
|
931 |
case CmdTx:
|
932 |
if (bit_nc) {
|
933 |
missing("CmdTx: NC = 0");
|
934 |
ok_status = 0;
|
935 |
break;
|
936 |
} |
937 |
tx_command(s); |
938 |
break;
|
939 |
case CmdTDR:
|
940 |
TRACE(OTHER, logout("load microcode\n"));
|
941 |
/* Starting with offset 8, the command contains
|
942 |
* 64 dwords microcode which we just ignore here. */
|
943 |
break;
|
944 |
case CmdDiagnose:
|
945 |
TRACE(OTHER, logout("diagnose\n"));
|
946 |
/* Make sure error flag is not set. */
|
947 |
s->tx.status = 0;
|
948 |
break;
|
949 |
default:
|
950 |
missing("undefined command");
|
951 |
ok_status = 0;
|
952 |
break;
|
953 |
} |
954 |
/* Write new status. */
|
955 |
e100_stw_le_phys(s->cb_address, s->tx.status | ok_status | STATUS_C); |
956 |
if (bit_i) {
|
957 |
/* CU completed action. */
|
958 |
eepro100_cx_interrupt(s); |
959 |
} |
960 |
if (bit_el) {
|
961 |
/* CU becomes idle. Terminate command loop. */
|
962 |
set_cu_state(s, cu_idle); |
963 |
eepro100_cna_interrupt(s); |
964 |
break;
|
965 |
} else if (bit_s) { |
966 |
/* CU becomes suspended. Terminate command loop. */
|
967 |
set_cu_state(s, cu_suspended); |
968 |
eepro100_cna_interrupt(s); |
969 |
break;
|
970 |
} else {
|
971 |
/* More entries in list. */
|
972 |
TRACE(OTHER, logout("CU list with at least one more entry\n"));
|
973 |
} |
974 |
} |
975 |
TRACE(OTHER, logout("CU list empty\n"));
|
976 |
/* List is empty. Now CU is idle or suspended. */
|
977 |
} |
978 |
|
979 |
static void eepro100_cu_command(EEPRO100State * s, uint8_t val) |
980 |
{ |
981 |
cu_state_t cu_state; |
982 |
switch (val) {
|
983 |
case CU_NOP:
|
984 |
/* No operation. */
|
985 |
break;
|
986 |
case CU_START:
|
987 |
cu_state = get_cu_state(s); |
988 |
if (cu_state != cu_idle && cu_state != cu_suspended) {
|
989 |
/* Intel documentation says that CU must be idle or suspended
|
990 |
* for the CU start command. */
|
991 |
logout("unexpected CU state is %u\n", cu_state);
|
992 |
} |
993 |
set_cu_state(s, cu_active); |
994 |
s->cu_offset = s->pointer; |
995 |
action_command(s); |
996 |
break;
|
997 |
case CU_RESUME:
|
998 |
if (get_cu_state(s) != cu_suspended) {
|
999 |
logout("bad CU resume from CU state %u\n", get_cu_state(s));
|
1000 |
/* Workaround for bad Linux eepro100 driver which resumes
|
1001 |
* from idle state. */
|
1002 |
#if 0
|
1003 |
missing("cu resume");
|
1004 |
#endif
|
1005 |
set_cu_state(s, cu_suspended); |
1006 |
} |
1007 |
if (get_cu_state(s) == cu_suspended) {
|
1008 |
TRACE(OTHER, logout("CU resuming\n"));
|
1009 |
set_cu_state(s, cu_active); |
1010 |
action_command(s); |
1011 |
} |
1012 |
break;
|
1013 |
case CU_STATSADDR:
|
1014 |
/* Load dump counters address. */
|
1015 |
s->statsaddr = s->pointer; |
1016 |
TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
|
1017 |
break;
|
1018 |
case CU_SHOWSTATS:
|
1019 |
/* Dump statistical counters. */
|
1020 |
TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
|
1021 |
dump_statistics(s); |
1022 |
e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
|
1023 |
break;
|
1024 |
case CU_CMD_BASE:
|
1025 |
/* Load CU base. */
|
1026 |
TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
|
1027 |
s->cu_base = s->pointer; |
1028 |
break;
|
1029 |
case CU_DUMPSTATS:
|
1030 |
/* Dump and reset statistical counters. */
|
1031 |
TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
|
1032 |
dump_statistics(s); |
1033 |
e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
|
1034 |
memset(&s->statistics, 0, sizeof(s->statistics)); |
1035 |
break;
|
1036 |
case CU_SRESUME:
|
1037 |
/* CU static resume. */
|
1038 |
missing("CU static resume");
|
1039 |
break;
|
1040 |
default:
|
1041 |
missing("Undefined CU command");
|
1042 |
} |
1043 |
} |
1044 |
|
1045 |
static void eepro100_ru_command(EEPRO100State * s, uint8_t val) |
1046 |
{ |
1047 |
switch (val) {
|
1048 |
case RU_NOP:
|
1049 |
/* No operation. */
|
1050 |
break;
|
1051 |
case RX_START:
|
1052 |
/* RU start. */
|
1053 |
if (get_ru_state(s) != ru_idle) {
|
1054 |
logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
|
1055 |
#if 0
|
1056 |
assert(!"wrong RU state");
|
1057 |
#endif
|
1058 |
} |
1059 |
set_ru_state(s, ru_ready); |
1060 |
s->ru_offset = s->pointer; |
1061 |
TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
|
1062 |
break;
|
1063 |
case RX_RESUME:
|
1064 |
/* Restart RU. */
|
1065 |
if (get_ru_state(s) != ru_suspended) {
|
1066 |
logout("RU state is %u, should be %u\n", get_ru_state(s),
|
1067 |
ru_suspended); |
1068 |
#if 0
|
1069 |
assert(!"wrong RU state");
|
1070 |
#endif
|
1071 |
} |
1072 |
set_ru_state(s, ru_ready); |
1073 |
break;
|
1074 |
case RU_ABORT:
|
1075 |
/* RU abort. */
|
1076 |
if (get_ru_state(s) == ru_ready) {
|
1077 |
eepro100_rnr_interrupt(s); |
1078 |
} |
1079 |
set_ru_state(s, ru_idle); |
1080 |
break;
|
1081 |
case RX_ADDR_LOAD:
|
1082 |
/* Load RU base. */
|
1083 |
TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
|
1084 |
s->ru_base = s->pointer; |
1085 |
break;
|
1086 |
default:
|
1087 |
logout("val=0x%02x (undefined RU command)\n", val);
|
1088 |
missing("Undefined SU command");
|
1089 |
} |
1090 |
} |
1091 |
|
1092 |
static void eepro100_write_command(EEPRO100State * s, uint8_t val) |
1093 |
{ |
1094 |
eepro100_ru_command(s, val & 0x0f);
|
1095 |
eepro100_cu_command(s, val & 0xf0);
|
1096 |
if ((val) == 0) { |
1097 |
TRACE(OTHER, logout("val=0x%02x\n", val));
|
1098 |
} |
1099 |
/* Clear command byte after command was accepted. */
|
1100 |
s->mem[SCBCmd] = 0;
|
1101 |
} |
1102 |
|
1103 |
/*****************************************************************************
|
1104 |
*
|
1105 |
* EEPROM emulation.
|
1106 |
*
|
1107 |
****************************************************************************/
|
1108 |
|
1109 |
#define EEPROM_CS 0x02 |
1110 |
#define EEPROM_SK 0x01 |
1111 |
#define EEPROM_DI 0x04 |
1112 |
#define EEPROM_DO 0x08 |
1113 |
|
1114 |
static uint16_t eepro100_read_eeprom(EEPRO100State * s)
|
1115 |
{ |
1116 |
uint16_t val = e100_read_reg2(s, SCBeeprom); |
1117 |
if (eeprom93xx_read(s->eeprom)) {
|
1118 |
val |= EEPROM_DO; |
1119 |
} else {
|
1120 |
val &= ~EEPROM_DO; |
1121 |
} |
1122 |
TRACE(EEPROM, logout("val=0x%04x\n", val));
|
1123 |
return val;
|
1124 |
} |
1125 |
|
1126 |
static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
1127 |
{ |
1128 |
TRACE(EEPROM, logout("val=0x%02x\n", val));
|
1129 |
|
1130 |
/* mask unwriteable bits */
|
1131 |
#if 0
|
1132 |
val = SET_MASKED(val, 0x31, eeprom->value);
|
1133 |
#endif
|
1134 |
|
1135 |
int eecs = ((val & EEPROM_CS) != 0); |
1136 |
int eesk = ((val & EEPROM_SK) != 0); |
1137 |
int eedi = ((val & EEPROM_DI) != 0); |
1138 |
eeprom93xx_write(eeprom, eecs, eesk, eedi); |
1139 |
} |
1140 |
|
1141 |
static void eepro100_write_pointer(EEPRO100State * s, uint32_t val) |
1142 |
{ |
1143 |
s->pointer = le32_to_cpu(val); |
1144 |
TRACE(OTHER, logout("val=0x%08x\n", val));
|
1145 |
} |
1146 |
|
1147 |
/*****************************************************************************
|
1148 |
*
|
1149 |
* MDI emulation.
|
1150 |
*
|
1151 |
****************************************************************************/
|
1152 |
|
1153 |
#if defined(DEBUG_EEPRO100)
|
1154 |
static const char * const mdi_op_name[] = { |
1155 |
"opcode 0",
|
1156 |
"write",
|
1157 |
"read",
|
1158 |
"opcode 3"
|
1159 |
}; |
1160 |
|
1161 |
static const char * const mdi_reg_name[] = { |
1162 |
"Control",
|
1163 |
"Status",
|
1164 |
"PHY Identification (Word 1)",
|
1165 |
"PHY Identification (Word 2)",
|
1166 |
"Auto-Negotiation Advertisement",
|
1167 |
"Auto-Negotiation Link Partner Ability",
|
1168 |
"Auto-Negotiation Expansion"
|
1169 |
}; |
1170 |
|
1171 |
static const char *reg2name(uint8_t reg) |
1172 |
{ |
1173 |
static char buffer[10]; |
1174 |
const char *p = buffer; |
1175 |
if (reg < ARRAY_SIZE(mdi_reg_name)) {
|
1176 |
p = mdi_reg_name[reg]; |
1177 |
} else {
|
1178 |
snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); |
1179 |
} |
1180 |
return p;
|
1181 |
} |
1182 |
#endif /* DEBUG_EEPRO100 */ |
1183 |
|
1184 |
static uint32_t eepro100_read_mdi(EEPRO100State * s)
|
1185 |
{ |
1186 |
uint32_t val = e100_read_reg4(s, SCBCtrlMDI); |
1187 |
|
1188 |
#ifdef DEBUG_EEPRO100
|
1189 |
uint8_t raiseint = (val & BIT(29)) >> 29; |
1190 |
uint8_t opcode = (val & BITS(27, 26)) >> 26; |
1191 |
uint8_t phy = (val & BITS(25, 21)) >> 21; |
1192 |
uint8_t reg = (val & BITS(20, 16)) >> 16; |
1193 |
uint16_t data = (val & BITS(15, 0)); |
1194 |
#endif
|
1195 |
/* Emulation takes no time to finish MDI transaction. */
|
1196 |
val |= BIT(28);
|
1197 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
1198 |
val, raiseint, mdi_op_name[opcode], phy, |
1199 |
reg2name(reg), data)); |
1200 |
return val;
|
1201 |
} |
1202 |
|
1203 |
static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) |
1204 |
{ |
1205 |
uint8_t raiseint = (val & BIT(29)) >> 29; |
1206 |
uint8_t opcode = (val & BITS(27, 26)) >> 26; |
1207 |
uint8_t phy = (val & BITS(25, 21)) >> 21; |
1208 |
uint8_t reg = (val & BITS(20, 16)) >> 16; |
1209 |
uint16_t data = (val & BITS(15, 0)); |
1210 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
1211 |
val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); |
1212 |
if (phy != 1) { |
1213 |
/* Unsupported PHY address. */
|
1214 |
#if 0
|
1215 |
logout("phy must be 1 but is %u\n", phy);
|
1216 |
#endif
|
1217 |
data = 0;
|
1218 |
} else if (opcode != 1 && opcode != 2) { |
1219 |
/* Unsupported opcode. */
|
1220 |
logout("opcode must be 1 or 2 but is %u\n", opcode);
|
1221 |
data = 0;
|
1222 |
} else if (reg > 6) { |
1223 |
/* Unsupported register. */
|
1224 |
logout("register must be 0...6 but is %u\n", reg);
|
1225 |
data = 0;
|
1226 |
} else {
|
1227 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
1228 |
val, raiseint, mdi_op_name[opcode], phy, |
1229 |
reg2name(reg), data)); |
1230 |
if (opcode == 1) { |
1231 |
/* MDI write */
|
1232 |
switch (reg) {
|
1233 |
case 0: /* Control Register */ |
1234 |
if (data & 0x8000) { |
1235 |
/* Reset status and control registers to default. */
|
1236 |
s->mdimem[0] = eepro100_mdi_default[0]; |
1237 |
s->mdimem[1] = eepro100_mdi_default[1]; |
1238 |
data = s->mdimem[reg]; |
1239 |
} else {
|
1240 |
/* Restart Auto Configuration = Normal Operation */
|
1241 |
data &= ~0x0200;
|
1242 |
} |
1243 |
break;
|
1244 |
case 1: /* Status Register */ |
1245 |
missing("not writable");
|
1246 |
data = s->mdimem[reg]; |
1247 |
break;
|
1248 |
case 2: /* PHY Identification Register (Word 1) */ |
1249 |
case 3: /* PHY Identification Register (Word 2) */ |
1250 |
missing("not implemented");
|
1251 |
break;
|
1252 |
case 4: /* Auto-Negotiation Advertisement Register */ |
1253 |
case 5: /* Auto-Negotiation Link Partner Ability Register */ |
1254 |
break;
|
1255 |
case 6: /* Auto-Negotiation Expansion Register */ |
1256 |
default:
|
1257 |
missing("not implemented");
|
1258 |
} |
1259 |
s->mdimem[reg] = data; |
1260 |
} else if (opcode == 2) { |
1261 |
/* MDI read */
|
1262 |
switch (reg) {
|
1263 |
case 0: /* Control Register */ |
1264 |
if (data & 0x8000) { |
1265 |
/* Reset status and control registers to default. */
|
1266 |
s->mdimem[0] = eepro100_mdi_default[0]; |
1267 |
s->mdimem[1] = eepro100_mdi_default[1]; |
1268 |
} |
1269 |
break;
|
1270 |
case 1: /* Status Register */ |
1271 |
s->mdimem[reg] |= 0x0020;
|
1272 |
break;
|
1273 |
case 2: /* PHY Identification Register (Word 1) */ |
1274 |
case 3: /* PHY Identification Register (Word 2) */ |
1275 |
case 4: /* Auto-Negotiation Advertisement Register */ |
1276 |
break;
|
1277 |
case 5: /* Auto-Negotiation Link Partner Ability Register */ |
1278 |
s->mdimem[reg] = 0x41fe;
|
1279 |
break;
|
1280 |
case 6: /* Auto-Negotiation Expansion Register */ |
1281 |
s->mdimem[reg] = 0x0001;
|
1282 |
break;
|
1283 |
} |
1284 |
data = s->mdimem[reg]; |
1285 |
} |
1286 |
/* Emulation takes no time to finish MDI transaction.
|
1287 |
* Set MDI bit in SCB status register. */
|
1288 |
s->mem[SCBAck] |= 0x08;
|
1289 |
val |= BIT(28);
|
1290 |
if (raiseint) {
|
1291 |
eepro100_mdi_interrupt(s); |
1292 |
} |
1293 |
} |
1294 |
val = (val & 0xffff0000) + data;
|
1295 |
e100_write_reg4(s, SCBCtrlMDI, val); |
1296 |
} |
1297 |
|
1298 |
/*****************************************************************************
|
1299 |
*
|
1300 |
* Port emulation.
|
1301 |
*
|
1302 |
****************************************************************************/
|
1303 |
|
1304 |
#define PORT_SOFTWARE_RESET 0 |
1305 |
#define PORT_SELFTEST 1 |
1306 |
#define PORT_SELECTIVE_RESET 2 |
1307 |
#define PORT_DUMP 3 |
1308 |
#define PORT_SELECTION_MASK 3 |
1309 |
|
1310 |
typedef struct { |
1311 |
uint32_t st_sign; /* Self Test Signature */
|
1312 |
uint32_t st_result; /* Self Test Results */
|
1313 |
} eepro100_selftest_t; |
1314 |
|
1315 |
static uint32_t eepro100_read_port(EEPRO100State * s)
|
1316 |
{ |
1317 |
return 0; |
1318 |
} |
1319 |
|
1320 |
static void eepro100_write_port(EEPRO100State * s, uint32_t val) |
1321 |
{ |
1322 |
uint32_t address = (val & ~PORT_SELECTION_MASK); |
1323 |
uint8_t selection = (val & PORT_SELECTION_MASK); |
1324 |
switch (selection) {
|
1325 |
case PORT_SOFTWARE_RESET:
|
1326 |
nic_reset(s); |
1327 |
break;
|
1328 |
case PORT_SELFTEST:
|
1329 |
TRACE(OTHER, logout("selftest address=0x%08x\n", address));
|
1330 |
eepro100_selftest_t data; |
1331 |
cpu_physical_memory_read(address, &data, sizeof(data));
|
1332 |
data.st_sign = 0xffffffff;
|
1333 |
data.st_result = 0;
|
1334 |
cpu_physical_memory_write(address, &data, sizeof(data));
|
1335 |
break;
|
1336 |
case PORT_SELECTIVE_RESET:
|
1337 |
TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
|
1338 |
nic_selective_reset(s); |
1339 |
break;
|
1340 |
default:
|
1341 |
logout("val=0x%08x\n", val);
|
1342 |
missing("unknown port selection");
|
1343 |
} |
1344 |
} |
1345 |
|
1346 |
/*****************************************************************************
|
1347 |
*
|
1348 |
* General hardware emulation.
|
1349 |
*
|
1350 |
****************************************************************************/
|
1351 |
|
1352 |
static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
|
1353 |
{ |
1354 |
uint8_t val = 0;
|
1355 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1356 |
val = s->mem[addr]; |
1357 |
} |
1358 |
|
1359 |
switch (addr) {
|
1360 |
case SCBStatus:
|
1361 |
case SCBAck:
|
1362 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1363 |
break;
|
1364 |
case SCBCmd:
|
1365 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1366 |
#if 0
|
1367 |
val = eepro100_read_command(s);
|
1368 |
#endif
|
1369 |
break;
|
1370 |
case SCBIntmask:
|
1371 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1372 |
break;
|
1373 |
case SCBPort + 3: |
1374 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1375 |
break;
|
1376 |
case SCBeeprom:
|
1377 |
val = eepro100_read_eeprom(s); |
1378 |
break;
|
1379 |
case SCBpmdr: /* Power Management Driver Register */ |
1380 |
val = 0;
|
1381 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1382 |
break;
|
1383 |
case SCBgstat: /* General Status Register */ |
1384 |
/* 100 Mbps full duplex, valid link */
|
1385 |
val = 0x07;
|
1386 |
TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
|
1387 |
break;
|
1388 |
default:
|
1389 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1390 |
missing("unknown byte read");
|
1391 |
} |
1392 |
return val;
|
1393 |
} |
1394 |
|
1395 |
static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
|
1396 |
{ |
1397 |
uint16_t val = 0;
|
1398 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1399 |
val = e100_read_reg2(s, addr); |
1400 |
} |
1401 |
|
1402 |
switch (addr) {
|
1403 |
case SCBStatus:
|
1404 |
case SCBCmd:
|
1405 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
1406 |
break;
|
1407 |
case SCBeeprom:
|
1408 |
val = eepro100_read_eeprom(s); |
1409 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
1410 |
break;
|
1411 |
default:
|
1412 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1413 |
missing("unknown word read");
|
1414 |
} |
1415 |
return val;
|
1416 |
} |
1417 |
|
1418 |
static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
|
1419 |
{ |
1420 |
uint32_t val = 0;
|
1421 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1422 |
val = e100_read_reg4(s, addr); |
1423 |
} |
1424 |
|
1425 |
switch (addr) {
|
1426 |
case SCBStatus:
|
1427 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
1428 |
break;
|
1429 |
case SCBPointer:
|
1430 |
#if 0
|
1431 |
val = eepro100_read_pointer(s);
|
1432 |
#endif
|
1433 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
1434 |
break;
|
1435 |
case SCBPort:
|
1436 |
val = eepro100_read_port(s); |
1437 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
1438 |
break;
|
1439 |
case SCBCtrlMDI:
|
1440 |
val = eepro100_read_mdi(s); |
1441 |
break;
|
1442 |
default:
|
1443 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1444 |
missing("unknown longword read");
|
1445 |
} |
1446 |
return val;
|
1447 |
} |
1448 |
|
1449 |
static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) |
1450 |
{ |
1451 |
/* SCBStatus is readonly. */
|
1452 |
if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { |
1453 |
s->mem[addr] = val; |
1454 |
} |
1455 |
|
1456 |
switch (addr) {
|
1457 |
case SCBStatus:
|
1458 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1459 |
break;
|
1460 |
case SCBAck:
|
1461 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1462 |
eepro100_acknowledge(s); |
1463 |
break;
|
1464 |
case SCBCmd:
|
1465 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1466 |
eepro100_write_command(s, val); |
1467 |
break;
|
1468 |
case SCBIntmask:
|
1469 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1470 |
if (val & BIT(1)) { |
1471 |
eepro100_swi_interrupt(s); |
1472 |
} |
1473 |
eepro100_interrupt(s, 0);
|
1474 |
break;
|
1475 |
case SCBPort + 3: |
1476 |
case SCBFlow: /* does not exist on 82557 */ |
1477 |
case SCBFlow + 1: |
1478 |
case SCBFlow + 2: |
1479 |
case SCBpmdr: /* does not exist on 82557 */ |
1480 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1481 |
break;
|
1482 |
case SCBeeprom:
|
1483 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
1484 |
eepro100_write_eeprom(s->eeprom, val); |
1485 |
break;
|
1486 |
default:
|
1487 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1488 |
missing("unknown byte write");
|
1489 |
} |
1490 |
} |
1491 |
|
1492 |
static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) |
1493 |
{ |
1494 |
/* SCBStatus is readonly. */
|
1495 |
if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { |
1496 |
e100_write_reg2(s, addr, val); |
1497 |
} |
1498 |
|
1499 |
switch (addr) {
|
1500 |
case SCBStatus:
|
1501 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
1502 |
s->mem[SCBAck] = (val >> 8);
|
1503 |
eepro100_acknowledge(s); |
1504 |
break;
|
1505 |
case SCBCmd:
|
1506 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
1507 |
eepro100_write_command(s, val); |
1508 |
eepro100_write1(s, SCBIntmask, val >> 8);
|
1509 |
break;
|
1510 |
case SCBeeprom:
|
1511 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
1512 |
eepro100_write_eeprom(s->eeprom, val); |
1513 |
break;
|
1514 |
default:
|
1515 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1516 |
missing("unknown word write");
|
1517 |
} |
1518 |
} |
1519 |
|
1520 |
static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) |
1521 |
{ |
1522 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1523 |
e100_write_reg4(s, addr, val); |
1524 |
} |
1525 |
|
1526 |
switch (addr) {
|
1527 |
case SCBPointer:
|
1528 |
eepro100_write_pointer(s, val); |
1529 |
break;
|
1530 |
case SCBPort:
|
1531 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
1532 |
eepro100_write_port(s, val); |
1533 |
break;
|
1534 |
case SCBCtrlMDI:
|
1535 |
eepro100_write_mdi(s, val); |
1536 |
break;
|
1537 |
default:
|
1538 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1539 |
missing("unknown longword write");
|
1540 |
} |
1541 |
} |
1542 |
|
1543 |
/*****************************************************************************
|
1544 |
*
|
1545 |
* Port mapped I/O.
|
1546 |
*
|
1547 |
****************************************************************************/
|
1548 |
|
1549 |
static uint32_t ioport_read1(void *opaque, uint32_t addr) |
1550 |
{ |
1551 |
EEPRO100State *s = opaque; |
1552 |
#if 0
|
1553 |
logout("addr=%s\n", regname(addr));
|
1554 |
#endif
|
1555 |
return eepro100_read1(s, addr - s->region1);
|
1556 |
} |
1557 |
|
1558 |
static uint32_t ioport_read2(void *opaque, uint32_t addr) |
1559 |
{ |
1560 |
EEPRO100State *s = opaque; |
1561 |
return eepro100_read2(s, addr - s->region1);
|
1562 |
} |
1563 |
|
1564 |
static uint32_t ioport_read4(void *opaque, uint32_t addr) |
1565 |
{ |
1566 |
EEPRO100State *s = opaque; |
1567 |
return eepro100_read4(s, addr - s->region1);
|
1568 |
} |
1569 |
|
1570 |
static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) |
1571 |
{ |
1572 |
EEPRO100State *s = opaque; |
1573 |
#if 0
|
1574 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1575 |
#endif
|
1576 |
eepro100_write1(s, addr - s->region1, val); |
1577 |
} |
1578 |
|
1579 |
static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) |
1580 |
{ |
1581 |
EEPRO100State *s = opaque; |
1582 |
eepro100_write2(s, addr - s->region1, val); |
1583 |
} |
1584 |
|
1585 |
static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) |
1586 |
{ |
1587 |
EEPRO100State *s = opaque; |
1588 |
eepro100_write4(s, addr - s->region1, val); |
1589 |
} |
1590 |
|
1591 |
/***********************************************************/
|
1592 |
/* PCI EEPRO100 definitions */
|
1593 |
|
1594 |
static void pci_map(PCIDevice * pci_dev, int region_num, |
1595 |
pcibus_t addr, pcibus_t size, int type)
|
1596 |
{ |
1597 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
1598 |
|
1599 |
TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1600 |
"size=0x%08"FMT_PCIBUS", type=%d\n", |
1601 |
region_num, addr, size, type)); |
1602 |
|
1603 |
assert(region_num == 1);
|
1604 |
register_ioport_write(addr, size, 1, ioport_write1, s);
|
1605 |
register_ioport_read(addr, size, 1, ioport_read1, s);
|
1606 |
register_ioport_write(addr, size, 2, ioport_write2, s);
|
1607 |
register_ioport_read(addr, size, 2, ioport_read2, s);
|
1608 |
register_ioport_write(addr, size, 4, ioport_write4, s);
|
1609 |
register_ioport_read(addr, size, 4, ioport_read4, s);
|
1610 |
|
1611 |
s->region1 = addr; |
1612 |
} |
1613 |
|
1614 |
/*****************************************************************************
|
1615 |
*
|
1616 |
* Memory mapped I/O.
|
1617 |
*
|
1618 |
****************************************************************************/
|
1619 |
|
1620 |
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
1621 |
{ |
1622 |
EEPRO100State *s = opaque; |
1623 |
#if 0
|
1624 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1625 |
#endif
|
1626 |
eepro100_write1(s, addr, val); |
1627 |
} |
1628 |
|
1629 |
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
1630 |
{ |
1631 |
EEPRO100State *s = opaque; |
1632 |
#if 0
|
1633 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1634 |
#endif
|
1635 |
eepro100_write2(s, addr, val); |
1636 |
} |
1637 |
|
1638 |
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1639 |
{ |
1640 |
EEPRO100State *s = opaque; |
1641 |
#if 0
|
1642 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1643 |
#endif
|
1644 |
eepro100_write4(s, addr, val); |
1645 |
} |
1646 |
|
1647 |
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
1648 |
{ |
1649 |
EEPRO100State *s = opaque; |
1650 |
#if 0
|
1651 |
logout("addr=%s\n", regname(addr));
|
1652 |
#endif
|
1653 |
return eepro100_read1(s, addr);
|
1654 |
} |
1655 |
|
1656 |
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
1657 |
{ |
1658 |
EEPRO100State *s = opaque; |
1659 |
#if 0
|
1660 |
logout("addr=%s\n", regname(addr));
|
1661 |
#endif
|
1662 |
return eepro100_read2(s, addr);
|
1663 |
} |
1664 |
|
1665 |
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
1666 |
{ |
1667 |
EEPRO100State *s = opaque; |
1668 |
#if 0
|
1669 |
logout("addr=%s\n", regname(addr));
|
1670 |
#endif
|
1671 |
return eepro100_read4(s, addr);
|
1672 |
} |
1673 |
|
1674 |
static CPUWriteMemoryFunc * const pci_mmio_write[] = { |
1675 |
pci_mmio_writeb, |
1676 |
pci_mmio_writew, |
1677 |
pci_mmio_writel |
1678 |
}; |
1679 |
|
1680 |
static CPUReadMemoryFunc * const pci_mmio_read[] = { |
1681 |
pci_mmio_readb, |
1682 |
pci_mmio_readw, |
1683 |
pci_mmio_readl |
1684 |
}; |
1685 |
|
1686 |
static int nic_can_receive(VLANClientState *nc) |
1687 |
{ |
1688 |
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
1689 |
TRACE(RXTX, logout("%p\n", s));
|
1690 |
return get_ru_state(s) == ru_ready;
|
1691 |
#if 0
|
1692 |
return !eepro100_buffer_full(s);
|
1693 |
#endif
|
1694 |
} |
1695 |
|
1696 |
static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size) |
1697 |
{ |
1698 |
/* TODO:
|
1699 |
* - Magic packets should set bit 30 in power management driver register.
|
1700 |
* - Interesting packets should set bit 29 in power management driver register.
|
1701 |
*/
|
1702 |
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
1703 |
uint16_t rfd_status = 0xa000;
|
1704 |
#if defined(CONFIG_PAD_RECEIVED_FRAMES)
|
1705 |
uint8_t min_buf[60];
|
1706 |
#endif
|
1707 |
static const uint8_t broadcast_macaddr[6] = |
1708 |
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
1709 |
|
1710 |
#if defined(CONFIG_PAD_RECEIVED_FRAMES)
|
1711 |
/* Pad to minimum Ethernet frame length */
|
1712 |
if (size < sizeof(min_buf)) { |
1713 |
memcpy(min_buf, buf, size); |
1714 |
memset(&min_buf[size], 0, sizeof(min_buf) - size); |
1715 |
buf = min_buf; |
1716 |
size = sizeof(min_buf);
|
1717 |
} |
1718 |
#endif
|
1719 |
|
1720 |
if (s->configuration[8] & 0x80) { |
1721 |
/* CSMA is disabled. */
|
1722 |
logout("%p received while CSMA is disabled\n", s);
|
1723 |
return -1; |
1724 |
#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
|
1725 |
} else if (size < 64 && (s->configuration[7] & BIT(0))) { |
1726 |
/* Short frame and configuration byte 7/0 (discard short receive) set:
|
1727 |
* Short frame is discarded */
|
1728 |
logout("%p received short frame (%zu byte)\n", s, size);
|
1729 |
s->statistics.rx_short_frame_errors++; |
1730 |
return -1; |
1731 |
#endif
|
1732 |
} else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) { |
1733 |
/* Long frame and configuration byte 18/3 (long receive ok) not set:
|
1734 |
* Long frames are discarded. */
|
1735 |
logout("%p received long frame (%zu byte), ignored\n", s, size);
|
1736 |
return -1; |
1737 |
} else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */ |
1738 |
/* Frame matches individual address. */
|
1739 |
/* TODO: check configuration byte 15/4 (ignore U/L). */
|
1740 |
TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
|
1741 |
} else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1742 |
/* Broadcast frame. */
|
1743 |
TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
|
1744 |
rfd_status |= 0x0002;
|
1745 |
} else if (buf[0] & 0x01) { |
1746 |
/* Multicast frame. */
|
1747 |
TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
|
1748 |
if (s->configuration[21] & BIT(3)) { |
1749 |
/* Multicast all bit is set, receive all multicast frames. */
|
1750 |
} else {
|
1751 |
unsigned mcast_idx = compute_mcast_idx(buf);
|
1752 |
assert(mcast_idx < 64);
|
1753 |
if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { |
1754 |
/* Multicast frame is allowed in hash table. */
|
1755 |
} else if (s->configuration[15] & BIT(0)) { |
1756 |
/* Promiscuous: receive all. */
|
1757 |
rfd_status |= 0x0004;
|
1758 |
} else {
|
1759 |
TRACE(RXTX, logout("%p multicast ignored\n", s));
|
1760 |
return -1; |
1761 |
} |
1762 |
} |
1763 |
/* TODO: Next not for promiscuous mode? */
|
1764 |
rfd_status |= 0x0002;
|
1765 |
} else if (s->configuration[15] & BIT(0)) { |
1766 |
/* Promiscuous: receive all. */
|
1767 |
TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
|
1768 |
rfd_status |= 0x0004;
|
1769 |
} else if (s->configuration[20] & BIT(6)) { |
1770 |
/* Multiple IA bit set. */
|
1771 |
unsigned mcast_idx = compute_mcast_idx(buf);
|
1772 |
assert(mcast_idx < 64);
|
1773 |
if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { |
1774 |
TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
|
1775 |
} else {
|
1776 |
TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
|
1777 |
return -1; |
1778 |
} |
1779 |
} else {
|
1780 |
TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
|
1781 |
nic_dump(buf, size))); |
1782 |
return size;
|
1783 |
} |
1784 |
|
1785 |
if (get_ru_state(s) != ru_ready) {
|
1786 |
/* No resources available. */
|
1787 |
logout("no resources, state=%u\n", get_ru_state(s));
|
1788 |
/* TODO: RNR interrupt only at first failed frame? */
|
1789 |
eepro100_rnr_interrupt(s); |
1790 |
s->statistics.rx_resource_errors++; |
1791 |
#if 0
|
1792 |
assert(!"no resources");
|
1793 |
#endif
|
1794 |
return -1; |
1795 |
} |
1796 |
/* !!! */
|
1797 |
eepro100_rx_t rx; |
1798 |
cpu_physical_memory_read(s->ru_base + s->ru_offset, &rx, |
1799 |
sizeof(eepro100_rx_t));
|
1800 |
uint16_t rfd_command = le16_to_cpu(rx.command); |
1801 |
uint16_t rfd_size = le16_to_cpu(rx.size); |
1802 |
|
1803 |
if (size > rfd_size) {
|
1804 |
logout("Receive buffer (%" PRId16 " bytes) too small for data " |
1805 |
"(%zu bytes); data truncated\n", rfd_size, size);
|
1806 |
size = rfd_size; |
1807 |
} |
1808 |
#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
|
1809 |
if (size < 64) { |
1810 |
rfd_status |= 0x0080;
|
1811 |
} |
1812 |
#endif
|
1813 |
TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
|
1814 |
rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); |
1815 |
e100_stw_le_phys(s->ru_base + s->ru_offset + |
1816 |
offsetof(eepro100_rx_t, status), rfd_status); |
1817 |
e100_stw_le_phys(s->ru_base + s->ru_offset + |
1818 |
offsetof(eepro100_rx_t, count), size); |
1819 |
/* Early receive interrupt not supported. */
|
1820 |
#if 0
|
1821 |
eepro100_er_interrupt(s);
|
1822 |
#endif
|
1823 |
/* Receive CRC Transfer not supported. */
|
1824 |
if (s->configuration[18] & BIT(2)) { |
1825 |
missing("Receive CRC Transfer");
|
1826 |
return -1; |
1827 |
} |
1828 |
/* TODO: check stripping enable bit. */
|
1829 |
#if 0
|
1830 |
assert(!(s->configuration[17] & BIT(0)));
|
1831 |
#endif
|
1832 |
cpu_physical_memory_write(s->ru_base + s->ru_offset + |
1833 |
sizeof(eepro100_rx_t), buf, size);
|
1834 |
s->statistics.rx_good_frames++; |
1835 |
eepro100_fr_interrupt(s); |
1836 |
s->ru_offset = le32_to_cpu(rx.link); |
1837 |
if (rfd_command & COMMAND_EL) {
|
1838 |
/* EL bit is set, so this was the last frame. */
|
1839 |
logout("receive: Running out of frames\n");
|
1840 |
set_ru_state(s, ru_suspended); |
1841 |
} |
1842 |
if (rfd_command & COMMAND_S) {
|
1843 |
/* S bit is set. */
|
1844 |
set_ru_state(s, ru_suspended); |
1845 |
} |
1846 |
return size;
|
1847 |
} |
1848 |
|
1849 |
static const VMStateDescription vmstate_eepro100 = { |
1850 |
.version_id = 3,
|
1851 |
.minimum_version_id = 2,
|
1852 |
.minimum_version_id_old = 2,
|
1853 |
.fields = (VMStateField []) { |
1854 |
VMSTATE_PCI_DEVICE(dev, EEPRO100State), |
1855 |
VMSTATE_UNUSED(32),
|
1856 |
VMSTATE_BUFFER(mult, EEPRO100State), |
1857 |
VMSTATE_BUFFER(mem, EEPRO100State), |
1858 |
/* Save all members of struct between scb_stat and mem. */
|
1859 |
VMSTATE_UINT8(scb_stat, EEPRO100State), |
1860 |
VMSTATE_UINT8(int_stat, EEPRO100State), |
1861 |
VMSTATE_UNUSED(3*4), |
1862 |
VMSTATE_MACADDR(conf.macaddr, EEPRO100State), |
1863 |
VMSTATE_UNUSED(19*4), |
1864 |
VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
|
1865 |
/* The eeprom should be saved and restored by its own routines. */
|
1866 |
VMSTATE_UINT32(device, EEPRO100State), |
1867 |
/* TODO check device. */
|
1868 |
VMSTATE_UINT32(pointer, EEPRO100State), |
1869 |
VMSTATE_UINT32(cu_base, EEPRO100State), |
1870 |
VMSTATE_UINT32(cu_offset, EEPRO100State), |
1871 |
VMSTATE_UINT32(ru_base, EEPRO100State), |
1872 |
VMSTATE_UINT32(ru_offset, EEPRO100State), |
1873 |
VMSTATE_UINT32(statsaddr, EEPRO100State), |
1874 |
/* Save eepro100_stats_t statistics. */
|
1875 |
VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State), |
1876 |
VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State), |
1877 |
VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State), |
1878 |
VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State), |
1879 |
VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State), |
1880 |
VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State), |
1881 |
VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State), |
1882 |
VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State), |
1883 |
VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State), |
1884 |
VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State), |
1885 |
VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State), |
1886 |
VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State), |
1887 |
VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State), |
1888 |
VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State), |
1889 |
VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State), |
1890 |
VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State), |
1891 |
VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State), |
1892 |
VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State), |
1893 |
VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State), |
1894 |
VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State), |
1895 |
VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State), |
1896 |
/* Configuration bytes. */
|
1897 |
VMSTATE_BUFFER(configuration, EEPRO100State), |
1898 |
VMSTATE_END_OF_LIST() |
1899 |
} |
1900 |
}; |
1901 |
|
1902 |
static void nic_cleanup(VLANClientState *nc) |
1903 |
{ |
1904 |
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
1905 |
|
1906 |
s->nic = NULL;
|
1907 |
} |
1908 |
|
1909 |
static int pci_nic_uninit(PCIDevice *pci_dev) |
1910 |
{ |
1911 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
1912 |
|
1913 |
cpu_unregister_io_memory(s->mmio_index); |
1914 |
vmstate_unregister(&pci_dev->qdev, s->vmstate, s); |
1915 |
eeprom93xx_free(&pci_dev->qdev, s->eeprom); |
1916 |
qemu_del_vlan_client(&s->nic->nc); |
1917 |
return 0; |
1918 |
} |
1919 |
|
1920 |
static NetClientInfo net_eepro100_info = {
|
1921 |
.type = NET_CLIENT_TYPE_NIC, |
1922 |
.size = sizeof(NICState),
|
1923 |
.can_receive = nic_can_receive, |
1924 |
.receive = nic_receive, |
1925 |
.cleanup = nic_cleanup, |
1926 |
}; |
1927 |
|
1928 |
static int e100_nic_init(PCIDevice *pci_dev) |
1929 |
{ |
1930 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
1931 |
E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev, |
1932 |
pci_dev->qdev.info); |
1933 |
|
1934 |
TRACE(OTHER, logout("\n"));
|
1935 |
|
1936 |
s->device = e100_device->device; |
1937 |
|
1938 |
e100_pci_reset(s, e100_device); |
1939 |
|
1940 |
/* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
|
1941 |
* i82559 and later support 64 or 256 word EEPROM. */
|
1942 |
s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE); |
1943 |
|
1944 |
/* Handler for memory-mapped I/O */
|
1945 |
s->mmio_index = |
1946 |
cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s, |
1947 |
DEVICE_LITTLE_ENDIAN); |
1948 |
|
1949 |
pci_register_bar_simple(&s->dev, 0, PCI_MEM_SIZE,
|
1950 |
PCI_BASE_ADDRESS_MEM_PREFETCH, s->mmio_index); |
1951 |
|
1952 |
pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
|
1953 |
pci_map); |
1954 |
pci_register_bar_simple(&s->dev, 2, PCI_FLASH_SIZE, 0, s->mmio_index); |
1955 |
|
1956 |
qemu_macaddr_default_if_unset(&s->conf.macaddr); |
1957 |
logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)); |
1958 |
assert(s->region1 == 0);
|
1959 |
|
1960 |
nic_reset(s); |
1961 |
|
1962 |
s->nic = qemu_new_nic(&net_eepro100_info, &s->conf, |
1963 |
pci_dev->qdev.info->name, pci_dev->qdev.id, s); |
1964 |
|
1965 |
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
1966 |
TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
|
1967 |
|
1968 |
qemu_register_reset(nic_reset, s); |
1969 |
|
1970 |
s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
|
1971 |
memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
|
1972 |
s->vmstate->name = s->nic->nc.model; |
1973 |
vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
|
1974 |
|
1975 |
add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
|
1976 |
|
1977 |
return 0; |
1978 |
} |
1979 |
|
1980 |
static E100PCIDeviceInfo e100_devices[] = {
|
1981 |
{ |
1982 |
.pci.qdev.name = "i82550",
|
1983 |
.pci.qdev.desc = "Intel i82550 Ethernet",
|
1984 |
.device = i82550, |
1985 |
/* TODO: check device id. */
|
1986 |
.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
1987 |
/* Revision ID: 0x0c, 0x0d, 0x0e. */
|
1988 |
.revision = 0x0e,
|
1989 |
/* TODO: check size of statistical counters. */
|
1990 |
.stats_size = 80,
|
1991 |
/* TODO: check extended tcb support. */
|
1992 |
.has_extended_tcb_support = true,
|
1993 |
.power_management = true,
|
1994 |
},{ |
1995 |
.pci.qdev.name = "i82551",
|
1996 |
.pci.qdev.desc = "Intel i82551 Ethernet",
|
1997 |
.device = i82551, |
1998 |
.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
1999 |
/* Revision ID: 0x0f, 0x10. */
|
2000 |
.revision = 0x0f,
|
2001 |
/* TODO: check size of statistical counters. */
|
2002 |
.stats_size = 80,
|
2003 |
.has_extended_tcb_support = true,
|
2004 |
.power_management = true,
|
2005 |
},{ |
2006 |
.pci.qdev.name = "i82557a",
|
2007 |
.pci.qdev.desc = "Intel i82557A Ethernet",
|
2008 |
.device = i82557A, |
2009 |
.device_id = PCI_DEVICE_ID_INTEL_82557, |
2010 |
.revision = 0x01,
|
2011 |
.power_management = false,
|
2012 |
},{ |
2013 |
.pci.qdev.name = "i82557b",
|
2014 |
.pci.qdev.desc = "Intel i82557B Ethernet",
|
2015 |
.device = i82557B, |
2016 |
.device_id = PCI_DEVICE_ID_INTEL_82557, |
2017 |
.revision = 0x02,
|
2018 |
.power_management = false,
|
2019 |
},{ |
2020 |
.pci.qdev.name = "i82557c",
|
2021 |
.pci.qdev.desc = "Intel i82557C Ethernet",
|
2022 |
.device = i82557C, |
2023 |
.device_id = PCI_DEVICE_ID_INTEL_82557, |
2024 |
.revision = 0x03,
|
2025 |
.power_management = false,
|
2026 |
},{ |
2027 |
.pci.qdev.name = "i82558a",
|
2028 |
.pci.qdev.desc = "Intel i82558A Ethernet",
|
2029 |
.device = i82558A, |
2030 |
.device_id = PCI_DEVICE_ID_INTEL_82557, |
2031 |
.revision = 0x04,
|
2032 |
.stats_size = 76,
|
2033 |
.has_extended_tcb_support = true,
|
2034 |
.power_management = true,
|
2035 |
},{ |
2036 |
.pci.qdev.name = "i82558b",
|
2037 |
.pci.qdev.desc = "Intel i82558B Ethernet",
|
2038 |
.device = i82558B, |
2039 |
.device_id = PCI_DEVICE_ID_INTEL_82557, |
2040 |
.revision = 0x05,
|
2041 |
.stats_size = 76,
|
2042 |
.has_extended_tcb_support = true,
|
2043 |
.power_management = true,
|
2044 |
},{ |
2045 |
.pci.qdev.name = "i82559a",
|
2046 |
.pci.qdev.desc = "Intel i82559A Ethernet",
|
2047 |
.device = i82559A, |
2048 |
.device_id = PCI_DEVICE_ID_INTEL_82557, |
2049 |
.revision = 0x06,
|
2050 |
.stats_size = 80,
|
2051 |
.has_extended_tcb_support = true,
|
2052 |
.power_management = true,
|
2053 |
},{ |
2054 |
.pci.qdev.name = "i82559b",
|
2055 |
.pci.qdev.desc = "Intel i82559B Ethernet",
|
2056 |
.device = i82559B, |
2057 |
.device_id = PCI_DEVICE_ID_INTEL_82557, |
2058 |
.revision = 0x07,
|
2059 |
.stats_size = 80,
|
2060 |
.has_extended_tcb_support = true,
|
2061 |
.power_management = true,
|
2062 |
},{ |
2063 |
.pci.qdev.name = "i82559c",
|
2064 |
.pci.qdev.desc = "Intel i82559C Ethernet",
|
2065 |
.device = i82559C, |
2066 |
.device_id = PCI_DEVICE_ID_INTEL_82557, |
2067 |
#if 0
|
2068 |
.revision = 0x08,
|
2069 |
#endif
|
2070 |
/* TODO: Windows wants revision id 0x0c. */
|
2071 |
.revision = 0x0c,
|
2072 |
.stats_size = 80,
|
2073 |
.has_extended_tcb_support = true,
|
2074 |
.power_management = true,
|
2075 |
},{ |
2076 |
.pci.qdev.name = "i82559er",
|
2077 |
.pci.qdev.desc = "Intel i82559ER Ethernet",
|
2078 |
.device = i82559ER, |
2079 |
.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
2080 |
.revision = 0x09,
|
2081 |
.stats_size = 80,
|
2082 |
.has_extended_tcb_support = true,
|
2083 |
.power_management = true,
|
2084 |
},{ |
2085 |
.pci.qdev.name = "i82562",
|
2086 |
.pci.qdev.desc = "Intel i82562 Ethernet",
|
2087 |
.device = i82562, |
2088 |
/* TODO: check device id. */
|
2089 |
.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
2090 |
/* TODO: wrong revision id. */
|
2091 |
.revision = 0x0e,
|
2092 |
.stats_size = 80,
|
2093 |
.has_extended_tcb_support = true,
|
2094 |
.power_management = true,
|
2095 |
},{ |
2096 |
/* Toshiba Tecra 8200. */
|
2097 |
.pci.qdev.name = "i82801",
|
2098 |
.pci.qdev.desc = "Intel i82801 Ethernet",
|
2099 |
.device = i82801, |
2100 |
.device_id = 0x2449,
|
2101 |
.revision = 0x03,
|
2102 |
.stats_size = 80,
|
2103 |
.has_extended_tcb_support = true,
|
2104 |
.power_management = true,
|
2105 |
} |
2106 |
}; |
2107 |
|
2108 |
static Property e100_properties[] = {
|
2109 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
2110 |
DEFINE_PROP_END_OF_LIST(), |
2111 |
}; |
2112 |
|
2113 |
static void eepro100_register_devices(void) |
2114 |
{ |
2115 |
size_t i; |
2116 |
for (i = 0; i < ARRAY_SIZE(e100_devices); i++) { |
2117 |
PCIDeviceInfo *pci_dev = &e100_devices[i].pci; |
2118 |
/* We use the same rom file for all device ids.
|
2119 |
QEMU fixes the device id during rom load. */
|
2120 |
pci_dev->romfile = "gpxe-eepro100-80861209.rom";
|
2121 |
pci_dev->init = e100_nic_init; |
2122 |
pci_dev->exit = pci_nic_uninit; |
2123 |
pci_dev->qdev.props = e100_properties; |
2124 |
pci_dev->qdev.size = sizeof(EEPRO100State);
|
2125 |
pci_qdev_register(pci_dev); |
2126 |
} |
2127 |
} |
2128 |
|
2129 |
device_init(eepro100_register_devices) |