Revision e67888a7
| b/target-sh4/translate.c | ||
|---|---|---|
| 647 | 647 |
gen_op_movl_rN_T0(REG(B7_4)); |
| 648 | 648 |
gen_op_xor_T0_rN(REG(B11_8)); |
| 649 | 649 |
return; |
| 650 |
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn */
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|
| 650 |
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
|
|
| 651 | 651 |
if (ctx->fpscr & FPSCR_PR) {
|
| 652 | 652 |
gen_op_fmov_drN_DT0(XREG(B7_4)); |
| 653 | 653 |
gen_op_fmov_DT0_drN(XREG(B11_8)); |
| ... | ... | |
| 661 | 661 |
gen_op_fmov_FT0_frN(FREG(B11_8)); |
| 662 | 662 |
} |
| 663 | 663 |
return; |
| 664 |
case 0xf00a: /* fmov {F,D,X}Rm,@Rn */
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|
| 664 |
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
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|
| 665 | 665 |
if (ctx->fpscr & FPSCR_PR) {
|
| 666 | 666 |
gen_op_fmov_drN_DT0(XREG(B7_4)); |
| 667 | 667 |
gen_op_movl_rN_T1(REG(B11_8)); |
| ... | ... | |
| 678 | 678 |
gen_op_stfl_FT0_T1(ctx); |
| 679 | 679 |
} |
| 680 | 680 |
return; |
| 681 |
case 0xf008: /* fmov @Rm,{F,D,X}Rn */
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|
| 681 |
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
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|
| 682 | 682 |
if (ctx->fpscr & FPSCR_PR) {
|
| 683 | 683 |
gen_op_movl_rN_T0(REG(B7_4)); |
| 684 | 684 |
gen_op_ldfq_T0_DT0(ctx); |
| ... | ... | |
| 695 | 695 |
gen_op_fmov_FT0_frN(FREG(B11_8)); |
| 696 | 696 |
} |
| 697 | 697 |
return; |
| 698 |
case 0xf009: /* fmov @Rm+,{F,D,X}Rn */
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|
| 698 |
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
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|
| 699 | 699 |
if (ctx->fpscr & FPSCR_PR) {
|
| 700 | 700 |
gen_op_movl_rN_T0(REG(B7_4)); |
| 701 | 701 |
gen_op_ldfq_T0_DT0(ctx); |
| ... | ... | |
| 715 | 715 |
gen_op_inc4_rN(REG(B7_4)); |
| 716 | 716 |
} |
| 717 | 717 |
return; |
| 718 |
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn */
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|
| 718 |
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
|
|
| 719 | 719 |
if (ctx->fpscr & FPSCR_PR) {
|
| 720 | 720 |
gen_op_dec8_rN(REG(B11_8)); |
| 721 | 721 |
gen_op_fmov_drN_DT0(XREG(B7_4)); |
| ... | ... | |
| 735 | 735 |
gen_op_stfl_FT0_T1(ctx); |
| 736 | 736 |
} |
| 737 | 737 |
return; |
| 738 |
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm */
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|
| 738 |
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
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|
| 739 | 739 |
if (ctx->fpscr & FPSCR_PR) {
|
| 740 | 740 |
gen_op_movl_rN_T0(REG(B7_4)); |
| 741 | 741 |
gen_op_add_rN_T0(REG(0)); |
| ... | ... | |
| 755 | 755 |
gen_op_fmov_FT0_frN(FREG(B11_8)); |
| 756 | 756 |
} |
| 757 | 757 |
return; |
| 758 |
case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) */
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|
| 758 |
case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
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|
| 759 | 759 |
if (ctx->fpscr & FPSCR_PR) {
|
| 760 | 760 |
gen_op_fmov_drN_DT0(XREG(B7_4)); |
| 761 | 761 |
gen_op_movl_rN_T1(REG(B11_8)); |
| ... | ... | |
| 775 | 775 |
gen_op_stfl_FT0_T1(ctx); |
| 776 | 776 |
} |
| 777 | 777 |
return; |
| 778 |
case 0xf000: /* fadd Rm,Rn */
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|
| 779 |
case 0xf001: /* fsub Rm,Rn */
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|
| 780 |
case 0xf002: /* fmul Rm,Rn */
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|
| 781 |
case 0xf003: /* fdiv Rm,Rn */
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|
| 782 |
case 0xf004: /* fcmp/eq Rm,Rn */
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|
| 783 |
case 0xf005: /* fcmp/gt Rm,Rn */
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|
| 778 |
case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
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|
| 779 |
case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
|
|
| 780 |
case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
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|
| 781 |
case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
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|
| 782 |
case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
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|
| 783 |
case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
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|
| 784 | 784 |
if (ctx->fpscr & FPSCR_PR) {
|
| 785 | 785 |
if (ctx->opcode & 0x0110) |
| 786 | 786 |
break; /* illegal instruction */ |
| ... | ... | |
| 1121 | 1121 |
case 0x401b: /* tas.b @Rn */ |
| 1122 | 1122 |
gen_op_tasb_rN(REG(B11_8)); |
| 1123 | 1123 |
return; |
| 1124 |
case 0xf00d: /* fsts FPUL,FRn */
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|
| 1124 |
case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
|
|
| 1125 | 1125 |
gen_op_movl_fpul_FT0(); |
| 1126 | 1126 |
gen_op_fmov_FT0_frN(FREG(B11_8)); |
| 1127 | 1127 |
return; |
| 1128 |
case 0xf01d: /* flds FRm.FPUL */
|
|
| 1128 |
case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
|
|
| 1129 | 1129 |
gen_op_fmov_frN_FT0(FREG(B11_8)); |
| 1130 | 1130 |
gen_op_movl_FT0_fpul(); |
| 1131 | 1131 |
return; |
| 1132 |
case 0xf02d: /* float FPUL,FRn/DRn */
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|
| 1132 |
case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
|
|
| 1133 | 1133 |
if (ctx->fpscr & FPSCR_PR) {
|
| 1134 | 1134 |
if (ctx->opcode & 0x0100) |
| 1135 | 1135 |
break; /* illegal instruction */ |
| ... | ... | |
| 1141 | 1141 |
gen_op_fmov_FT0_frN(FREG(B11_8)); |
| 1142 | 1142 |
} |
| 1143 | 1143 |
return; |
| 1144 |
case 0xf03d: /* ftrc FRm/DRm,FPUL */
|
|
| 1144 |
case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
|
|
| 1145 | 1145 |
if (ctx->fpscr & FPSCR_PR) {
|
| 1146 | 1146 |
if (ctx->opcode & 0x0100) |
| 1147 | 1147 |
break; /* illegal instruction */ |
| ... | ... | |
| 1153 | 1153 |
gen_op_ftrc_FT(); |
| 1154 | 1154 |
} |
| 1155 | 1155 |
return; |
| 1156 |
case 0xf08d: /* fldi0 FRn */
|
|
| 1156 |
case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
|
|
| 1157 | 1157 |
if (!(ctx->fpscr & FPSCR_PR)) {
|
| 1158 | 1158 |
gen_op_movl_imm_T0(0); |
| 1159 | 1159 |
gen_op_fmov_T0_frN(FREG(B11_8)); |
| 1160 | 1160 |
return; |
| 1161 | 1161 |
} |
| 1162 | 1162 |
break; |
| 1163 |
case 0xf09d: /* fldi1 FRn */
|
|
| 1163 |
case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
|
|
| 1164 | 1164 |
if (!(ctx->fpscr & FPSCR_PR)) {
|
| 1165 | 1165 |
gen_op_movl_imm_T0(0x3f800000); |
| 1166 | 1166 |
gen_op_fmov_T0_frN(FREG(B11_8)); |
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