root / hw / ppc / spapr.c @ e68cb8b4
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/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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* Copyright (c) 2010 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "sysemu/sysemu.h" |
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#include "hw/hw.h" |
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#include "elf.h" |
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#include "net/net.h" |
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#include "sysemu/blockdev.h" |
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#include "sysemu/cpus.h" |
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#include "sysemu/kvm.h" |
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#include "kvm_ppc.h" |
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#include "mmu-hash64.h" |
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#include "hw/boards.h" |
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#include "hw/ppc/ppc.h" |
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#include "hw/loader.h" |
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|
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#include "hw/ppc/spapr.h" |
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#include "hw/ppc/spapr_vio.h" |
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#include "hw/pci-host/spapr.h" |
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#include "hw/ppc/xics.h" |
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#include "hw/pci/msi.h" |
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|
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#include "hw/pci/pci.h" |
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#include "exec/address-spaces.h" |
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#include "hw/usb.h" |
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#include "qemu/config-file.h" |
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#include <libfdt.h> |
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|
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/* SLOF memory layout:
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*
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* SLOF raw image loaded at 0, copies its romfs right below the flat
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* device-tree, then position SLOF itself 31M below that
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*
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* So we set FW_OVERHEAD to 40MB which should account for all of that
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* and more
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*
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* We load our kernel at 4M, leaving space for SLOF initial image
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*/
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#define FDT_MAX_SIZE 0x10000 |
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#define RTAS_MAX_SIZE 0x10000 |
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#define FW_MAX_SIZE 0x400000 |
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#define FW_FILE_NAME "slof.bin" |
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#define FW_OVERHEAD 0x2800000 |
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#define KERNEL_LOAD_ADDR FW_MAX_SIZE
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#define MIN_RMA_SLOF 128UL |
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#define TIMEBASE_FREQ 512000000ULL |
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#define MAX_CPUS 256 |
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#define XICS_IRQS 1024 |
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#define PHANDLE_XICP 0x00001111 |
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|
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#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
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|
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sPAPREnvironment *spapr; |
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|
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int spapr_allocate_irq(int hint, bool lsi) |
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{
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int irq;
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if (hint) {
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irq = hint; |
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/* FIXME: we should probably check for collisions somehow */
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} else {
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irq = spapr->next_irq++; |
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} |
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/* Configure irq type */
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if (!xics_get_qirq(spapr->icp, irq)) {
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return 0; |
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} |
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xics_set_irq_type(spapr->icp, irq, lsi); |
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return irq;
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} |
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|
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/* Allocate block of consequtive IRQs, returns a number of the first */
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int spapr_allocate_irq_block(int num, bool lsi) |
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{
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int first = -1; |
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int i;
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for (i = 0; i < num; ++i) { |
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int irq;
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irq = spapr_allocate_irq(0, lsi);
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if (!irq) {
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return -1; |
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} |
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if (0 == i) { |
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first = irq; |
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} |
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/* If the above doesn't create a consecutive block then that's
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* an internal bug */
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assert(irq == (first + i)); |
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} |
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return first;
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} |
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static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) |
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{
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int ret = 0, offset; |
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CPUState *cpu; |
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char cpu_model[32]; |
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int smt = kvmppc_smt_threads();
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uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
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assert(spapr->cpu_model); |
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for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) { |
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uint32_t associativity[] = {cpu_to_be32(0x5),
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cpu_to_be32(0x0),
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cpu_to_be32(0x0),
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cpu_to_be32(0x0),
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cpu_to_be32(cpu->numa_node), |
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cpu_to_be32(cpu->cpu_index)}; |
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if ((cpu->cpu_index % smt) != 0) { |
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continue;
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} |
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snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model, |
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cpu->cpu_index); |
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offset = fdt_path_offset(fdt, cpu_model); |
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if (offset < 0) { |
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return offset;
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} |
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if (nb_numa_nodes > 1) { |
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ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
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sizeof(associativity));
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if (ret < 0) { |
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return ret;
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} |
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} |
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ret = fdt_setprop(fdt, offset, "ibm,pft-size",
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pft_size_prop, sizeof(pft_size_prop));
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if (ret < 0) { |
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return ret;
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} |
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} |
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return ret;
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} |
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static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
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size_t maxsize) |
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{
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size_t maxcells = maxsize / sizeof(uint32_t);
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int i, j, count;
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uint32_t *p = prop; |
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for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
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struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
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if (!sps->page_shift) {
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break;
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} |
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for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { |
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if (sps->enc[count].page_shift == 0) { |
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break;
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} |
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} |
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if ((p - prop) >= (maxcells - 3 - count * 2)) { |
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break;
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} |
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*(p++) = cpu_to_be32(sps->page_shift); |
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*(p++) = cpu_to_be32(sps->slb_enc); |
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*(p++) = cpu_to_be32(count); |
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for (j = 0; j < count; j++) { |
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*(p++) = cpu_to_be32(sps->enc[j].page_shift); |
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*(p++) = cpu_to_be32(sps->enc[j].pte_enc); |
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} |
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} |
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return (p - prop) * sizeof(uint32_t); |
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} |
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#define _FDT(exp) \
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do { \
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int ret = (exp); \
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if (ret < 0) { \ |
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fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
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#exp, fdt_strerror(ret)); \
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exit(1); \
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} \ |
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} while (0) |
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|
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static void *spapr_create_fdt_skel(const char *cpu_model, |
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hwaddr initrd_base, |
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hwaddr initrd_size, |
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hwaddr kernel_size, |
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const char *boot_device, |
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const char *kernel_cmdline, |
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uint32_t epow_irq) |
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{
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void *fdt;
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CPUState *cs; |
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uint32_t start_prop = cpu_to_be32(initrd_base); |
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uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); |
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char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" |
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"\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk";
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char qemu_hypertas_prop[] = "hcall-memop1"; |
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uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
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uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
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char *modelname;
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int i, smt = kvmppc_smt_threads();
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unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; |
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fdt = g_malloc0(FDT_MAX_SIZE); |
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_FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
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|
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if (kernel_size) {
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_FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); |
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} |
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if (initrd_size) {
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_FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); |
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} |
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_FDT((fdt_finish_reservemap(fdt))); |
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|
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/* Root node */
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_FDT((fdt_begin_node(fdt, "")));
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_FDT((fdt_property_string(fdt, "device_type", "chrp"))); |
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_FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); |
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_FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); |
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|
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_FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); |
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_FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); |
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|
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/* /chosen */
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_FDT((fdt_begin_node(fdt, "chosen")));
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/* Set Form1_affinity */
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_FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); |
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_FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
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_FDT((fdt_property(fdt, "linux,initrd-start",
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&start_prop, sizeof(start_prop))));
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_FDT((fdt_property(fdt, "linux,initrd-end",
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&end_prop, sizeof(end_prop))));
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if (kernel_size) {
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uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
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cpu_to_be64(kernel_size) }; |
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_FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); |
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} |
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if (boot_device) {
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_FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
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} |
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_FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
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_FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
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_FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
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|
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_FDT((fdt_end_node(fdt))); |
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|
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/* cpus */
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_FDT((fdt_begin_node(fdt, "cpus")));
|
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|
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_FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
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_FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
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|
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modelname = g_strdup(cpu_model); |
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|
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for (i = 0; i < strlen(modelname); i++) { |
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modelname[i] = toupper(modelname[i]); |
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} |
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|
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/* This is needed during FDT finalization */
|
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spapr->cpu_model = g_strdup(modelname); |
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|
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for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { |
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PowerPCCPU *cpu = POWERPC_CPU(cs); |
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CPUPPCState *env = &cpu->env; |
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); |
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int index = cs->cpu_index;
|
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uint32_t servers_prop[smp_threads]; |
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uint32_t gservers_prop[smp_threads * 2];
|
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char *nodename;
|
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uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
|
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0xffffffff, 0xffffffff}; |
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uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; |
| 317 |
uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
|
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uint32_t page_sizes_prop[64];
|
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size_t page_sizes_prop_size; |
| 320 |
|
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if ((index % smt) != 0) { |
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continue;
|
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} |
| 324 |
|
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nodename = g_strdup_printf("%s@%x", modelname, index);
|
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|
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_FDT((fdt_begin_node(fdt, nodename))); |
| 328 |
|
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g_free(nodename); |
| 330 |
|
| 331 |
_FDT((fdt_property_cell(fdt, "reg", index)));
|
| 332 |
_FDT((fdt_property_string(fdt, "device_type", "cpu"))); |
| 333 |
|
| 334 |
_FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
|
| 335 |
_FDT((fdt_property_cell(fdt, "d-cache-block-size",
|
| 336 |
env->dcache_line_size))); |
| 337 |
_FDT((fdt_property_cell(fdt, "d-cache-line-size",
|
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env->dcache_line_size))); |
| 339 |
_FDT((fdt_property_cell(fdt, "i-cache-block-size",
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| 340 |
env->icache_line_size))); |
| 341 |
_FDT((fdt_property_cell(fdt, "i-cache-line-size",
|
| 342 |
env->icache_line_size))); |
| 343 |
|
| 344 |
if (pcc->l1_dcache_size) {
|
| 345 |
_FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size)));
|
| 346 |
} else {
|
| 347 |
fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
|
| 348 |
} |
| 349 |
if (pcc->l1_icache_size) {
|
| 350 |
_FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size)));
|
| 351 |
} else {
|
| 352 |
fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
|
| 353 |
} |
| 354 |
|
| 355 |
_FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
|
| 356 |
_FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
|
| 357 |
_FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
|
| 358 |
_FDT((fdt_property_string(fdt, "status", "okay"))); |
| 359 |
_FDT((fdt_property(fdt, "64-bit", NULL, 0))); |
| 360 |
|
| 361 |
/* Build interrupt servers and gservers properties */
|
| 362 |
for (i = 0; i < smp_threads; i++) { |
| 363 |
servers_prop[i] = cpu_to_be32(index + i); |
| 364 |
/* Hack, direct the group queues back to cpu 0 */
|
| 365 |
gservers_prop[i*2] = cpu_to_be32(index + i);
|
| 366 |
gservers_prop[i*2 + 1] = 0; |
| 367 |
} |
| 368 |
_FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s",
|
| 369 |
servers_prop, sizeof(servers_prop))));
|
| 370 |
_FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
|
| 371 |
gservers_prop, sizeof(gservers_prop))));
|
| 372 |
|
| 373 |
if (env->mmu_model & POWERPC_MMU_1TSEG) {
|
| 374 |
_FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
|
| 375 |
segs, sizeof(segs))));
|
| 376 |
} |
| 377 |
|
| 378 |
/* Advertise VMX/VSX (vector extensions) if available
|
| 379 |
* 0 / no property == no vector extensions
|
| 380 |
* 1 == VMX / Altivec available
|
| 381 |
* 2 == VSX available */
|
| 382 |
if (env->insns_flags & PPC_ALTIVEC) {
|
| 383 |
uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; |
| 384 |
|
| 385 |
_FDT((fdt_property_cell(fdt, "ibm,vmx", vmx)));
|
| 386 |
} |
| 387 |
|
| 388 |
/* Advertise DFP (Decimal Floating Point) if available
|
| 389 |
* 0 / no property == no DFP
|
| 390 |
* 1 == DFP available */
|
| 391 |
if (env->insns_flags2 & PPC2_DFP) {
|
| 392 |
_FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); |
| 393 |
} |
| 394 |
|
| 395 |
page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, |
| 396 |
sizeof(page_sizes_prop));
|
| 397 |
if (page_sizes_prop_size) {
|
| 398 |
_FDT((fdt_property(fdt, "ibm,segment-page-sizes",
|
| 399 |
page_sizes_prop, page_sizes_prop_size))); |
| 400 |
} |
| 401 |
|
| 402 |
_FDT((fdt_end_node(fdt))); |
| 403 |
} |
| 404 |
|
| 405 |
g_free(modelname); |
| 406 |
|
| 407 |
_FDT((fdt_end_node(fdt))); |
| 408 |
|
| 409 |
/* RTAS */
|
| 410 |
_FDT((fdt_begin_node(fdt, "rtas")));
|
| 411 |
|
| 412 |
_FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
|
| 413 |
sizeof(hypertas_prop))));
|
| 414 |
_FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop,
|
| 415 |
sizeof(qemu_hypertas_prop))));
|
| 416 |
|
| 417 |
_FDT((fdt_property(fdt, "ibm,associativity-reference-points",
|
| 418 |
refpoints, sizeof(refpoints))));
|
| 419 |
|
| 420 |
_FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
|
| 421 |
|
| 422 |
_FDT((fdt_end_node(fdt))); |
| 423 |
|
| 424 |
/* interrupt controller */
|
| 425 |
_FDT((fdt_begin_node(fdt, "interrupt-controller")));
|
| 426 |
|
| 427 |
_FDT((fdt_property_string(fdt, "device_type",
|
| 428 |
"PowerPC-External-Interrupt-Presentation")));
|
| 429 |
_FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); |
| 430 |
_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
| 431 |
_FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
|
| 432 |
interrupt_server_ranges_prop, |
| 433 |
sizeof(interrupt_server_ranges_prop))));
|
| 434 |
_FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); |
| 435 |
_FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
|
| 436 |
_FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
|
| 437 |
|
| 438 |
_FDT((fdt_end_node(fdt))); |
| 439 |
|
| 440 |
/* vdevice */
|
| 441 |
_FDT((fdt_begin_node(fdt, "vdevice")));
|
| 442 |
|
| 443 |
_FDT((fdt_property_string(fdt, "device_type", "vdevice"))); |
| 444 |
_FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); |
| 445 |
_FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
| 446 |
_FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
| 447 |
_FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
| 448 |
_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
| 449 |
|
| 450 |
_FDT((fdt_end_node(fdt))); |
| 451 |
|
| 452 |
/* event-sources */
|
| 453 |
spapr_events_fdt_skel(fdt, epow_irq); |
| 454 |
|
| 455 |
_FDT((fdt_end_node(fdt))); /* close root node */
|
| 456 |
_FDT((fdt_finish(fdt))); |
| 457 |
|
| 458 |
return fdt;
|
| 459 |
} |
| 460 |
|
| 461 |
static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) |
| 462 |
{
|
| 463 |
uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
|
| 464 |
cpu_to_be32(0x0), cpu_to_be32(0x0), |
| 465 |
cpu_to_be32(0x0)};
|
| 466 |
char mem_name[32]; |
| 467 |
hwaddr node0_size, mem_start; |
| 468 |
uint64_t mem_reg_property[2];
|
| 469 |
int i, off;
|
| 470 |
|
| 471 |
/* memory node(s) */
|
| 472 |
node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; |
| 473 |
if (spapr->rma_size > node0_size) {
|
| 474 |
spapr->rma_size = node0_size; |
| 475 |
} |
| 476 |
|
| 477 |
/* RMA */
|
| 478 |
mem_reg_property[0] = 0; |
| 479 |
mem_reg_property[1] = cpu_to_be64(spapr->rma_size);
|
| 480 |
off = fdt_add_subnode(fdt, 0, "memory@0"); |
| 481 |
_FDT(off); |
| 482 |
_FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); |
| 483 |
_FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
|
| 484 |
sizeof(mem_reg_property))));
|
| 485 |
_FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
|
| 486 |
sizeof(associativity))));
|
| 487 |
|
| 488 |
/* RAM: Node 0 */
|
| 489 |
if (node0_size > spapr->rma_size) {
|
| 490 |
mem_reg_property[0] = cpu_to_be64(spapr->rma_size);
|
| 491 |
mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size);
|
| 492 |
|
| 493 |
sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size);
|
| 494 |
off = fdt_add_subnode(fdt, 0, mem_name);
|
| 495 |
_FDT(off); |
| 496 |
_FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); |
| 497 |
_FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
|
| 498 |
sizeof(mem_reg_property))));
|
| 499 |
_FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
|
| 500 |
sizeof(associativity))));
|
| 501 |
} |
| 502 |
|
| 503 |
/* RAM: Node 1 and beyond */
|
| 504 |
mem_start = node0_size; |
| 505 |
for (i = 1; i < nb_numa_nodes; i++) { |
| 506 |
mem_reg_property[0] = cpu_to_be64(mem_start);
|
| 507 |
mem_reg_property[1] = cpu_to_be64(node_mem[i]);
|
| 508 |
associativity[3] = associativity[4] = cpu_to_be32(i); |
| 509 |
sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start);
|
| 510 |
off = fdt_add_subnode(fdt, 0, mem_name);
|
| 511 |
_FDT(off); |
| 512 |
_FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); |
| 513 |
_FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
|
| 514 |
sizeof(mem_reg_property))));
|
| 515 |
_FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
|
| 516 |
sizeof(associativity))));
|
| 517 |
mem_start += node_mem[i]; |
| 518 |
} |
| 519 |
|
| 520 |
return 0; |
| 521 |
} |
| 522 |
|
| 523 |
static void spapr_finalize_fdt(sPAPREnvironment *spapr, |
| 524 |
hwaddr fdt_addr, |
| 525 |
hwaddr rtas_addr, |
| 526 |
hwaddr rtas_size) |
| 527 |
{
|
| 528 |
int ret;
|
| 529 |
void *fdt;
|
| 530 |
sPAPRPHBState *phb; |
| 531 |
|
| 532 |
fdt = g_malloc(FDT_MAX_SIZE); |
| 533 |
|
| 534 |
/* open out the base tree into a temp buffer for the final tweaks */
|
| 535 |
_FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); |
| 536 |
|
| 537 |
ret = spapr_populate_memory(spapr, fdt); |
| 538 |
if (ret < 0) { |
| 539 |
fprintf(stderr, "couldn't setup memory nodes in fdt\n");
|
| 540 |
exit(1);
|
| 541 |
} |
| 542 |
|
| 543 |
ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
| 544 |
if (ret < 0) { |
| 545 |
fprintf(stderr, "couldn't setup vio devices in fdt\n");
|
| 546 |
exit(1);
|
| 547 |
} |
| 548 |
|
| 549 |
QLIST_FOREACH(phb, &spapr->phbs, list) {
|
| 550 |
ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
| 551 |
} |
| 552 |
|
| 553 |
if (ret < 0) { |
| 554 |
fprintf(stderr, "couldn't setup PCI devices in fdt\n");
|
| 555 |
exit(1);
|
| 556 |
} |
| 557 |
|
| 558 |
/* RTAS */
|
| 559 |
ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); |
| 560 |
if (ret < 0) { |
| 561 |
fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
|
| 562 |
} |
| 563 |
|
| 564 |
/* Advertise NUMA via ibm,associativity */
|
| 565 |
ret = spapr_fixup_cpu_dt(fdt, spapr); |
| 566 |
if (ret < 0) { |
| 567 |
fprintf(stderr, "Couldn't finalize CPU device tree properties\n");
|
| 568 |
} |
| 569 |
|
| 570 |
if (!spapr->has_graphics) {
|
| 571 |
spapr_populate_chosen_stdout(fdt, spapr->vio_bus); |
| 572 |
} |
| 573 |
|
| 574 |
_FDT((fdt_pack(fdt))); |
| 575 |
|
| 576 |
if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
|
| 577 |
hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
|
| 578 |
fdt_totalsize(fdt), FDT_MAX_SIZE); |
| 579 |
exit(1);
|
| 580 |
} |
| 581 |
|
| 582 |
cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
| 583 |
|
| 584 |
g_free(fdt); |
| 585 |
} |
| 586 |
|
| 587 |
static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
| 588 |
{
|
| 589 |
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; |
| 590 |
} |
| 591 |
|
| 592 |
static void emulate_spapr_hypercall(PowerPCCPU *cpu) |
| 593 |
{
|
| 594 |
CPUPPCState *env = &cpu->env; |
| 595 |
|
| 596 |
if (msr_pr) {
|
| 597 |
hcall_dprintf("Hypercall made with MSR[PR]=1\n");
|
| 598 |
env->gpr[3] = H_PRIVILEGE;
|
| 599 |
} else {
|
| 600 |
env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
| 601 |
} |
| 602 |
} |
| 603 |
|
| 604 |
static void spapr_reset_htab(sPAPREnvironment *spapr) |
| 605 |
{
|
| 606 |
long shift;
|
| 607 |
|
| 608 |
/* allocate hash page table. For now we always make this 16mb,
|
| 609 |
* later we should probably make it scale to the size of guest
|
| 610 |
* RAM */
|
| 611 |
|
| 612 |
shift = kvmppc_reset_htab(spapr->htab_shift); |
| 613 |
|
| 614 |
if (shift > 0) { |
| 615 |
/* Kernel handles htab, we don't need to allocate one */
|
| 616 |
spapr->htab_shift = shift; |
| 617 |
} else {
|
| 618 |
if (!spapr->htab) {
|
| 619 |
/* Allocate an htab if we don't yet have one */
|
| 620 |
spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); |
| 621 |
} |
| 622 |
|
| 623 |
/* And clear it */
|
| 624 |
memset(spapr->htab, 0, HTAB_SIZE(spapr));
|
| 625 |
} |
| 626 |
|
| 627 |
/* Update the RMA size if necessary */
|
| 628 |
if (spapr->vrma_adjust) {
|
| 629 |
spapr->rma_size = kvmppc_rma_size(ram_size, spapr->htab_shift); |
| 630 |
} |
| 631 |
} |
| 632 |
|
| 633 |
static void ppc_spapr_reset(void) |
| 634 |
{
|
| 635 |
PowerPCCPU *first_ppc_cpu; |
| 636 |
|
| 637 |
/* Reset the hash table & recalc the RMA */
|
| 638 |
spapr_reset_htab(spapr); |
| 639 |
|
| 640 |
qemu_devices_reset(); |
| 641 |
|
| 642 |
/* Load the fdt */
|
| 643 |
spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, |
| 644 |
spapr->rtas_size); |
| 645 |
|
| 646 |
/* Set up the entry state */
|
| 647 |
first_ppc_cpu = POWERPC_CPU(first_cpu); |
| 648 |
first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
|
| 649 |
first_ppc_cpu->env.gpr[5] = 0; |
| 650 |
first_cpu->halted = 0;
|
| 651 |
first_ppc_cpu->env.nip = spapr->entry_point; |
| 652 |
|
| 653 |
} |
| 654 |
|
| 655 |
static void spapr_cpu_reset(void *opaque) |
| 656 |
{
|
| 657 |
PowerPCCPU *cpu = opaque; |
| 658 |
CPUState *cs = CPU(cpu); |
| 659 |
CPUPPCState *env = &cpu->env; |
| 660 |
|
| 661 |
cpu_reset(cs); |
| 662 |
|
| 663 |
/* All CPUs start halted. CPU0 is unhalted from the machine level
|
| 664 |
* reset code and the rest are explicitly started up by the guest
|
| 665 |
* using an RTAS call */
|
| 666 |
cs->halted = 1;
|
| 667 |
|
| 668 |
env->spr[SPR_HIOR] = 0;
|
| 669 |
|
| 670 |
env->external_htab = (uint8_t *)spapr->htab; |
| 671 |
env->htab_base = -1;
|
| 672 |
env->htab_mask = HTAB_SIZE(spapr) - 1;
|
| 673 |
env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | |
| 674 |
(spapr->htab_shift - 18);
|
| 675 |
} |
| 676 |
|
| 677 |
static void spapr_create_nvram(sPAPREnvironment *spapr) |
| 678 |
{
|
| 679 |
DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
|
| 680 |
const char *drivename = qemu_opt_get(qemu_get_machine_opts(), "nvram"); |
| 681 |
|
| 682 |
if (drivename) {
|
| 683 |
BlockDriverState *bs; |
| 684 |
|
| 685 |
bs = bdrv_find(drivename); |
| 686 |
if (!bs) {
|
| 687 |
fprintf(stderr, "No such block device \"%s\" for nvram\n",
|
| 688 |
drivename); |
| 689 |
exit(1);
|
| 690 |
} |
| 691 |
qdev_prop_set_drive_nofail(dev, "drive", bs);
|
| 692 |
} |
| 693 |
|
| 694 |
qdev_init_nofail(dev); |
| 695 |
|
| 696 |
spapr->nvram = (struct sPAPRNVRAM *)dev;
|
| 697 |
} |
| 698 |
|
| 699 |
/* Returns whether we want to use VGA or not */
|
| 700 |
static int spapr_vga_init(PCIBus *pci_bus) |
| 701 |
{
|
| 702 |
switch (vga_interface_type) {
|
| 703 |
case VGA_NONE:
|
| 704 |
case VGA_STD:
|
| 705 |
return pci_vga_init(pci_bus) != NULL; |
| 706 |
default:
|
| 707 |
fprintf(stderr, "This vga model is not supported,"
|
| 708 |
"currently it only supports -vga std\n");
|
| 709 |
exit(0);
|
| 710 |
break;
|
| 711 |
} |
| 712 |
} |
| 713 |
|
| 714 |
static const VMStateDescription vmstate_spapr = { |
| 715 |
.name = "spapr",
|
| 716 |
.version_id = 1,
|
| 717 |
.minimum_version_id = 1,
|
| 718 |
.minimum_version_id_old = 1,
|
| 719 |
.fields = (VMStateField []) {
|
| 720 |
VMSTATE_UINT32(next_irq, sPAPREnvironment), |
| 721 |
|
| 722 |
/* RTC offset */
|
| 723 |
VMSTATE_UINT64(rtc_offset, sPAPREnvironment), |
| 724 |
|
| 725 |
VMSTATE_END_OF_LIST() |
| 726 |
}, |
| 727 |
}; |
| 728 |
|
| 729 |
#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
| 730 |
#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
|
| 731 |
#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
|
| 732 |
#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
|
| 733 |
|
| 734 |
static int htab_save_setup(QEMUFile *f, void *opaque) |
| 735 |
{
|
| 736 |
sPAPREnvironment *spapr = opaque; |
| 737 |
|
| 738 |
/* "Iteration" header */
|
| 739 |
qemu_put_be32(f, spapr->htab_shift); |
| 740 |
|
| 741 |
if (spapr->htab) {
|
| 742 |
spapr->htab_save_index = 0;
|
| 743 |
spapr->htab_first_pass = true;
|
| 744 |
} else {
|
| 745 |
assert(kvm_enabled()); |
| 746 |
|
| 747 |
spapr->htab_fd = kvmppc_get_htab_fd(false);
|
| 748 |
if (spapr->htab_fd < 0) { |
| 749 |
fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n",
|
| 750 |
strerror(errno)); |
| 751 |
return -1; |
| 752 |
} |
| 753 |
} |
| 754 |
|
| 755 |
|
| 756 |
return 0; |
| 757 |
} |
| 758 |
|
| 759 |
static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, |
| 760 |
int64_t max_ns) |
| 761 |
{
|
| 762 |
int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
|
| 763 |
int index = spapr->htab_save_index;
|
| 764 |
int64_t starttime = qemu_get_clock_ns(rt_clock); |
| 765 |
|
| 766 |
assert(spapr->htab_first_pass); |
| 767 |
|
| 768 |
do {
|
| 769 |
int chunkstart;
|
| 770 |
|
| 771 |
/* Consume invalid HPTEs */
|
| 772 |
while ((index < htabslots)
|
| 773 |
&& !HPTE_VALID(HPTE(spapr->htab, index))) {
|
| 774 |
index++; |
| 775 |
CLEAN_HPTE(HPTE(spapr->htab, index)); |
| 776 |
} |
| 777 |
|
| 778 |
/* Consume valid HPTEs */
|
| 779 |
chunkstart = index; |
| 780 |
while ((index < htabslots)
|
| 781 |
&& HPTE_VALID(HPTE(spapr->htab, index))) {
|
| 782 |
index++; |
| 783 |
CLEAN_HPTE(HPTE(spapr->htab, index)); |
| 784 |
} |
| 785 |
|
| 786 |
if (index > chunkstart) {
|
| 787 |
int n_valid = index - chunkstart;
|
| 788 |
|
| 789 |
qemu_put_be32(f, chunkstart); |
| 790 |
qemu_put_be16(f, n_valid); |
| 791 |
qemu_put_be16(f, 0);
|
| 792 |
qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), |
| 793 |
HASH_PTE_SIZE_64 * n_valid); |
| 794 |
|
| 795 |
if ((qemu_get_clock_ns(rt_clock) - starttime) > max_ns) {
|
| 796 |
break;
|
| 797 |
} |
| 798 |
} |
| 799 |
} while ((index < htabslots) && !qemu_file_rate_limit(f));
|
| 800 |
|
| 801 |
if (index >= htabslots) {
|
| 802 |
assert(index == htabslots); |
| 803 |
index = 0;
|
| 804 |
spapr->htab_first_pass = false;
|
| 805 |
} |
| 806 |
spapr->htab_save_index = index; |
| 807 |
} |
| 808 |
|
| 809 |
static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, |
| 810 |
int64_t max_ns) |
| 811 |
{
|
| 812 |
bool final = max_ns < 0; |
| 813 |
int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
|
| 814 |
int examined = 0, sent = 0; |
| 815 |
int index = spapr->htab_save_index;
|
| 816 |
int64_t starttime = qemu_get_clock_ns(rt_clock); |
| 817 |
|
| 818 |
assert(!spapr->htab_first_pass); |
| 819 |
|
| 820 |
do {
|
| 821 |
int chunkstart, invalidstart;
|
| 822 |
|
| 823 |
/* Consume non-dirty HPTEs */
|
| 824 |
while ((index < htabslots)
|
| 825 |
&& !HPTE_DIRTY(HPTE(spapr->htab, index))) {
|
| 826 |
index++; |
| 827 |
examined++; |
| 828 |
} |
| 829 |
|
| 830 |
chunkstart = index; |
| 831 |
/* Consume valid dirty HPTEs */
|
| 832 |
while ((index < htabslots)
|
| 833 |
&& HPTE_DIRTY(HPTE(spapr->htab, index)) |
| 834 |
&& HPTE_VALID(HPTE(spapr->htab, index))) {
|
| 835 |
CLEAN_HPTE(HPTE(spapr->htab, index)); |
| 836 |
index++; |
| 837 |
examined++; |
| 838 |
} |
| 839 |
|
| 840 |
invalidstart = index; |
| 841 |
/* Consume invalid dirty HPTEs */
|
| 842 |
while ((index < htabslots)
|
| 843 |
&& HPTE_DIRTY(HPTE(spapr->htab, index)) |
| 844 |
&& !HPTE_VALID(HPTE(spapr->htab, index))) {
|
| 845 |
CLEAN_HPTE(HPTE(spapr->htab, index)); |
| 846 |
index++; |
| 847 |
examined++; |
| 848 |
} |
| 849 |
|
| 850 |
if (index > chunkstart) {
|
| 851 |
int n_valid = invalidstart - chunkstart;
|
| 852 |
int n_invalid = index - invalidstart;
|
| 853 |
|
| 854 |
qemu_put_be32(f, chunkstart); |
| 855 |
qemu_put_be16(f, n_valid); |
| 856 |
qemu_put_be16(f, n_invalid); |
| 857 |
qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), |
| 858 |
HASH_PTE_SIZE_64 * n_valid); |
| 859 |
sent += index - chunkstart; |
| 860 |
|
| 861 |
if (!final && (qemu_get_clock_ns(rt_clock) - starttime) > max_ns) {
|
| 862 |
break;
|
| 863 |
} |
| 864 |
} |
| 865 |
|
| 866 |
if (examined >= htabslots) {
|
| 867 |
break;
|
| 868 |
} |
| 869 |
|
| 870 |
if (index >= htabslots) {
|
| 871 |
assert(index == htabslots); |
| 872 |
index = 0;
|
| 873 |
} |
| 874 |
} while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
|
| 875 |
|
| 876 |
if (index >= htabslots) {
|
| 877 |
assert(index == htabslots); |
| 878 |
index = 0;
|
| 879 |
} |
| 880 |
|
| 881 |
spapr->htab_save_index = index; |
| 882 |
|
| 883 |
return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
| 884 |
} |
| 885 |
|
| 886 |
#define MAX_ITERATION_NS 5000000 /* 5 ms */ |
| 887 |
#define MAX_KVM_BUF_SIZE 2048 |
| 888 |
|
| 889 |
static int htab_save_iterate(QEMUFile *f, void *opaque) |
| 890 |
{
|
| 891 |
sPAPREnvironment *spapr = opaque; |
| 892 |
int rc = 0; |
| 893 |
|
| 894 |
/* Iteration header */
|
| 895 |
qemu_put_be32(f, 0);
|
| 896 |
|
| 897 |
if (!spapr->htab) {
|
| 898 |
assert(kvm_enabled()); |
| 899 |
|
| 900 |
rc = kvmppc_save_htab(f, spapr->htab_fd, |
| 901 |
MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
| 902 |
if (rc < 0) { |
| 903 |
return rc;
|
| 904 |
} |
| 905 |
} else if (spapr->htab_first_pass) { |
| 906 |
htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
| 907 |
} else {
|
| 908 |
rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
| 909 |
} |
| 910 |
|
| 911 |
/* End marker */
|
| 912 |
qemu_put_be32(f, 0);
|
| 913 |
qemu_put_be16(f, 0);
|
| 914 |
qemu_put_be16(f, 0);
|
| 915 |
|
| 916 |
return rc;
|
| 917 |
} |
| 918 |
|
| 919 |
static int htab_save_complete(QEMUFile *f, void *opaque) |
| 920 |
{
|
| 921 |
sPAPREnvironment *spapr = opaque; |
| 922 |
|
| 923 |
/* Iteration header */
|
| 924 |
qemu_put_be32(f, 0);
|
| 925 |
|
| 926 |
if (!spapr->htab) {
|
| 927 |
int rc;
|
| 928 |
|
| 929 |
assert(kvm_enabled()); |
| 930 |
|
| 931 |
rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1);
|
| 932 |
if (rc < 0) { |
| 933 |
return rc;
|
| 934 |
} |
| 935 |
close(spapr->htab_fd); |
| 936 |
spapr->htab_fd = -1;
|
| 937 |
} else {
|
| 938 |
htab_save_later_pass(f, spapr, -1);
|
| 939 |
} |
| 940 |
|
| 941 |
/* End marker */
|
| 942 |
qemu_put_be32(f, 0);
|
| 943 |
qemu_put_be16(f, 0);
|
| 944 |
qemu_put_be16(f, 0);
|
| 945 |
|
| 946 |
return 0; |
| 947 |
} |
| 948 |
|
| 949 |
static int htab_load(QEMUFile *f, void *opaque, int version_id) |
| 950 |
{
|
| 951 |
sPAPREnvironment *spapr = opaque; |
| 952 |
uint32_t section_hdr; |
| 953 |
int fd = -1; |
| 954 |
|
| 955 |
if (version_id < 1 || version_id > 1) { |
| 956 |
fprintf(stderr, "htab_load() bad version\n");
|
| 957 |
return -EINVAL;
|
| 958 |
} |
| 959 |
|
| 960 |
section_hdr = qemu_get_be32(f); |
| 961 |
|
| 962 |
if (section_hdr) {
|
| 963 |
/* First section, just the hash shift */
|
| 964 |
if (spapr->htab_shift != section_hdr) {
|
| 965 |
return -EINVAL;
|
| 966 |
} |
| 967 |
return 0; |
| 968 |
} |
| 969 |
|
| 970 |
if (!spapr->htab) {
|
| 971 |
assert(kvm_enabled()); |
| 972 |
|
| 973 |
fd = kvmppc_get_htab_fd(true);
|
| 974 |
if (fd < 0) { |
| 975 |
fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n",
|
| 976 |
strerror(errno)); |
| 977 |
} |
| 978 |
} |
| 979 |
|
| 980 |
while (true) { |
| 981 |
uint32_t index; |
| 982 |
uint16_t n_valid, n_invalid; |
| 983 |
|
| 984 |
index = qemu_get_be32(f); |
| 985 |
n_valid = qemu_get_be16(f); |
| 986 |
n_invalid = qemu_get_be16(f); |
| 987 |
|
| 988 |
if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { |
| 989 |
/* End of Stream */
|
| 990 |
break;
|
| 991 |
} |
| 992 |
|
| 993 |
if ((index + n_valid + n_invalid) >
|
| 994 |
(HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
|
| 995 |
/* Bad index in stream */
|
| 996 |
fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) "
|
| 997 |
"in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid,
|
| 998 |
spapr->htab_shift); |
| 999 |
return -EINVAL;
|
| 1000 |
} |
| 1001 |
|
| 1002 |
if (spapr->htab) {
|
| 1003 |
if (n_valid) {
|
| 1004 |
qemu_get_buffer(f, HPTE(spapr->htab, index), |
| 1005 |
HASH_PTE_SIZE_64 * n_valid); |
| 1006 |
} |
| 1007 |
if (n_invalid) {
|
| 1008 |
memset(HPTE(spapr->htab, index + n_valid), 0,
|
| 1009 |
HASH_PTE_SIZE_64 * n_invalid); |
| 1010 |
} |
| 1011 |
} else {
|
| 1012 |
int rc;
|
| 1013 |
|
| 1014 |
assert(fd >= 0);
|
| 1015 |
|
| 1016 |
rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); |
| 1017 |
if (rc < 0) { |
| 1018 |
return rc;
|
| 1019 |
} |
| 1020 |
} |
| 1021 |
} |
| 1022 |
|
| 1023 |
if (!spapr->htab) {
|
| 1024 |
assert(fd >= 0);
|
| 1025 |
close(fd); |
| 1026 |
} |
| 1027 |
|
| 1028 |
return 0; |
| 1029 |
} |
| 1030 |
|
| 1031 |
static SaveVMHandlers savevm_htab_handlers = {
|
| 1032 |
.save_live_setup = htab_save_setup, |
| 1033 |
.save_live_iterate = htab_save_iterate, |
| 1034 |
.save_live_complete = htab_save_complete, |
| 1035 |
.load_state = htab_load, |
| 1036 |
}; |
| 1037 |
|
| 1038 |
/* pSeries LPAR / sPAPR hardware init */
|
| 1039 |
static void ppc_spapr_init(QEMUMachineInitArgs *args) |
| 1040 |
{
|
| 1041 |
ram_addr_t ram_size = args->ram_size; |
| 1042 |
const char *cpu_model = args->cpu_model; |
| 1043 |
const char *kernel_filename = args->kernel_filename; |
| 1044 |
const char *kernel_cmdline = args->kernel_cmdline; |
| 1045 |
const char *initrd_filename = args->initrd_filename; |
| 1046 |
const char *boot_device = args->boot_device; |
| 1047 |
PowerPCCPU *cpu; |
| 1048 |
CPUPPCState *env; |
| 1049 |
PCIHostState *phb; |
| 1050 |
int i;
|
| 1051 |
MemoryRegion *sysmem = get_system_memory(); |
| 1052 |
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
| 1053 |
hwaddr rma_alloc_size; |
| 1054 |
uint32_t initrd_base = 0;
|
| 1055 |
long kernel_size = 0, initrd_size = 0; |
| 1056 |
long load_limit, rtas_limit, fw_size;
|
| 1057 |
char *filename;
|
| 1058 |
|
| 1059 |
msi_supported = true;
|
| 1060 |
|
| 1061 |
spapr = g_malloc0(sizeof(*spapr));
|
| 1062 |
QLIST_INIT(&spapr->phbs); |
| 1063 |
|
| 1064 |
cpu_ppc_hypercall = emulate_spapr_hypercall; |
| 1065 |
|
| 1066 |
/* Allocate RMA if necessary */
|
| 1067 |
rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem);
|
| 1068 |
|
| 1069 |
if (rma_alloc_size == -1) { |
| 1070 |
hw_error("qemu: Unable to create RMA\n");
|
| 1071 |
exit(1);
|
| 1072 |
} |
| 1073 |
|
| 1074 |
if (rma_alloc_size && (rma_alloc_size < ram_size)) {
|
| 1075 |
spapr->rma_size = rma_alloc_size; |
| 1076 |
} else {
|
| 1077 |
spapr->rma_size = ram_size; |
| 1078 |
|
| 1079 |
/* With KVM, we don't actually know whether KVM supports an
|
| 1080 |
* unbounded RMA (PR KVM) or is limited by the hash table size
|
| 1081 |
* (HV KVM using VRMA), so we always assume the latter
|
| 1082 |
*
|
| 1083 |
* In that case, we also limit the initial allocations for RTAS
|
| 1084 |
* etc... to 256M since we have no way to know what the VRMA size
|
| 1085 |
* is going to be as it depends on the size of the hash table
|
| 1086 |
* isn't determined yet.
|
| 1087 |
*/
|
| 1088 |
if (kvm_enabled()) {
|
| 1089 |
spapr->vrma_adjust = 1;
|
| 1090 |
spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
|
| 1091 |
} |
| 1092 |
} |
| 1093 |
|
| 1094 |
/* We place the device tree and RTAS just below either the top of the RMA,
|
| 1095 |
* or just below 2GB, whichever is lowere, so that it can be
|
| 1096 |
* processed with 32-bit real mode code if necessary */
|
| 1097 |
rtas_limit = MIN(spapr->rma_size, 0x80000000);
|
| 1098 |
spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
| 1099 |
spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; |
| 1100 |
load_limit = spapr->fdt_addr - FW_OVERHEAD; |
| 1101 |
|
| 1102 |
/* We aim for a hash table of size 1/128 the size of RAM. The
|
| 1103 |
* normal rule of thumb is 1/64 the size of RAM, but that's much
|
| 1104 |
* more than needed for the Linux guests we support. */
|
| 1105 |
spapr->htab_shift = 18; /* Minimum architected size */ |
| 1106 |
while (spapr->htab_shift <= 46) { |
| 1107 |
if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { |
| 1108 |
break;
|
| 1109 |
} |
| 1110 |
spapr->htab_shift++; |
| 1111 |
} |
| 1112 |
|
| 1113 |
/* Set up Interrupt Controller before we create the VCPUs */
|
| 1114 |
spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, |
| 1115 |
XICS_IRQS); |
| 1116 |
spapr->next_irq = XICS_IRQ_BASE; |
| 1117 |
|
| 1118 |
/* init CPUs */
|
| 1119 |
if (cpu_model == NULL) { |
| 1120 |
cpu_model = kvm_enabled() ? "host" : "POWER7"; |
| 1121 |
} |
| 1122 |
for (i = 0; i < smp_cpus; i++) { |
| 1123 |
cpu = cpu_ppc_init(cpu_model); |
| 1124 |
if (cpu == NULL) { |
| 1125 |
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
| 1126 |
exit(1);
|
| 1127 |
} |
| 1128 |
env = &cpu->env; |
| 1129 |
|
| 1130 |
xics_cpu_setup(spapr->icp, cpu); |
| 1131 |
|
| 1132 |
/* Set time-base frequency to 512 MHz */
|
| 1133 |
cpu_ppc_tb_init(env, TIMEBASE_FREQ); |
| 1134 |
|
| 1135 |
/* PAPR always has exception vectors in RAM not ROM. To ensure this,
|
| 1136 |
* MSR[IP] should never be set.
|
| 1137 |
*/
|
| 1138 |
env->msr_mask &= ~(1 << 6); |
| 1139 |
|
| 1140 |
/* Tell KVM that we're in PAPR mode */
|
| 1141 |
if (kvm_enabled()) {
|
| 1142 |
kvmppc_set_papr(cpu); |
| 1143 |
} |
| 1144 |
|
| 1145 |
qemu_register_reset(spapr_cpu_reset, cpu); |
| 1146 |
} |
| 1147 |
|
| 1148 |
/* allocate RAM */
|
| 1149 |
spapr->ram_limit = ram_size; |
| 1150 |
if (spapr->ram_limit > rma_alloc_size) {
|
| 1151 |
ram_addr_t nonrma_base = rma_alloc_size; |
| 1152 |
ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; |
| 1153 |
|
| 1154 |
memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size); |
| 1155 |
vmstate_register_ram_global(ram); |
| 1156 |
memory_region_add_subregion(sysmem, nonrma_base, ram); |
| 1157 |
} |
| 1158 |
|
| 1159 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
|
| 1160 |
spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, |
| 1161 |
rtas_limit - spapr->rtas_addr); |
| 1162 |
if (spapr->rtas_size < 0) { |
| 1163 |
hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
|
| 1164 |
exit(1);
|
| 1165 |
} |
| 1166 |
if (spapr->rtas_size > RTAS_MAX_SIZE) {
|
| 1167 |
hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
|
| 1168 |
spapr->rtas_size, RTAS_MAX_SIZE); |
| 1169 |
exit(1);
|
| 1170 |
} |
| 1171 |
g_free(filename); |
| 1172 |
|
| 1173 |
/* Set up EPOW events infrastructure */
|
| 1174 |
spapr_events_init(spapr); |
| 1175 |
|
| 1176 |
/* Set up VIO bus */
|
| 1177 |
spapr->vio_bus = spapr_vio_bus_init(); |
| 1178 |
|
| 1179 |
for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
| 1180 |
if (serial_hds[i]) {
|
| 1181 |
spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
| 1182 |
} |
| 1183 |
} |
| 1184 |
|
| 1185 |
/* We always have at least the nvram device on VIO */
|
| 1186 |
spapr_create_nvram(spapr); |
| 1187 |
|
| 1188 |
/* Set up PCI */
|
| 1189 |
spapr_pci_rtas_init(); |
| 1190 |
|
| 1191 |
phb = spapr_create_phb(spapr, 0);
|
| 1192 |
|
| 1193 |
for (i = 0; i < nb_nics; i++) { |
| 1194 |
NICInfo *nd = &nd_table[i]; |
| 1195 |
|
| 1196 |
if (!nd->model) {
|
| 1197 |
nd->model = g_strdup("ibmveth");
|
| 1198 |
} |
| 1199 |
|
| 1200 |
if (strcmp(nd->model, "ibmveth") == 0) { |
| 1201 |
spapr_vlan_create(spapr->vio_bus, nd); |
| 1202 |
} else {
|
| 1203 |
pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
|
| 1204 |
} |
| 1205 |
} |
| 1206 |
|
| 1207 |
for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
| 1208 |
spapr_vscsi_create(spapr->vio_bus); |
| 1209 |
} |
| 1210 |
|
| 1211 |
/* Graphics */
|
| 1212 |
if (spapr_vga_init(phb->bus)) {
|
| 1213 |
spapr->has_graphics = true;
|
| 1214 |
} |
| 1215 |
|
| 1216 |
if (usb_enabled(spapr->has_graphics)) {
|
| 1217 |
pci_create_simple(phb->bus, -1, "pci-ohci"); |
| 1218 |
if (spapr->has_graphics) {
|
| 1219 |
usbdevice_create("keyboard");
|
| 1220 |
usbdevice_create("mouse");
|
| 1221 |
} |
| 1222 |
} |
| 1223 |
|
| 1224 |
if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
| 1225 |
fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
|
| 1226 |
"%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
|
| 1227 |
exit(1);
|
| 1228 |
} |
| 1229 |
|
| 1230 |
if (kernel_filename) {
|
| 1231 |
uint64_t lowaddr = 0;
|
| 1232 |
|
| 1233 |
kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
|
| 1234 |
NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); |
| 1235 |
if (kernel_size < 0) { |
| 1236 |
kernel_size = load_image_targphys(kernel_filename, |
| 1237 |
KERNEL_LOAD_ADDR, |
| 1238 |
load_limit - KERNEL_LOAD_ADDR); |
| 1239 |
} |
| 1240 |
if (kernel_size < 0) { |
| 1241 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
| 1242 |
kernel_filename); |
| 1243 |
exit(1);
|
| 1244 |
} |
| 1245 |
|
| 1246 |
/* load initrd */
|
| 1247 |
if (initrd_filename) {
|
| 1248 |
/* Try to locate the initrd in the gap between the kernel
|
| 1249 |
* and the firmware. Add a bit of space just in case
|
| 1250 |
*/
|
| 1251 |
initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; |
| 1252 |
initrd_size = load_image_targphys(initrd_filename, initrd_base, |
| 1253 |
load_limit - initrd_base); |
| 1254 |
if (initrd_size < 0) { |
| 1255 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
| 1256 |
initrd_filename); |
| 1257 |
exit(1);
|
| 1258 |
} |
| 1259 |
} else {
|
| 1260 |
initrd_base = 0;
|
| 1261 |
initrd_size = 0;
|
| 1262 |
} |
| 1263 |
} |
| 1264 |
|
| 1265 |
if (bios_name == NULL) { |
| 1266 |
bios_name = FW_FILE_NAME; |
| 1267 |
} |
| 1268 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 1269 |
fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
|
| 1270 |
if (fw_size < 0) { |
| 1271 |
hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
|
| 1272 |
exit(1);
|
| 1273 |
} |
| 1274 |
g_free(filename); |
| 1275 |
|
| 1276 |
spapr->entry_point = 0x100;
|
| 1277 |
|
| 1278 |
vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
| 1279 |
register_savevm_live(NULL, "spapr/htab", -1, 1, |
| 1280 |
&savevm_htab_handlers, spapr); |
| 1281 |
|
| 1282 |
/* Prepare the device tree */
|
| 1283 |
spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, |
| 1284 |
initrd_base, initrd_size, |
| 1285 |
kernel_size, |
| 1286 |
boot_device, kernel_cmdline, |
| 1287 |
spapr->epow_irq); |
| 1288 |
assert(spapr->fdt_skel != NULL);
|
| 1289 |
} |
| 1290 |
|
| 1291 |
static QEMUMachine spapr_machine = {
|
| 1292 |
.name = "pseries",
|
| 1293 |
.desc = "pSeries Logical Partition (PAPR compliant)",
|
| 1294 |
.is_default = 1,
|
| 1295 |
.init = ppc_spapr_init, |
| 1296 |
.reset = ppc_spapr_reset, |
| 1297 |
.block_default_type = IF_SCSI, |
| 1298 |
.max_cpus = MAX_CPUS, |
| 1299 |
.no_parallel = 1,
|
| 1300 |
.boot_order = NULL,
|
| 1301 |
}; |
| 1302 |
|
| 1303 |
static void spapr_machine_init(void) |
| 1304 |
{
|
| 1305 |
qemu_register_machine(&spapr_machine); |
| 1306 |
} |
| 1307 |
|
| 1308 |
machine_init(spapr_machine_init); |