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/*
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* PowerPC implementation of KVM hooks
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*
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* Copyright IBM Corp. 2007
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*
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* Authors:
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* Jerone Young <jyoung5@us.ibm.com>
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* Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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* Hollis Blanchard <hollisb@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include <dirent.h> |
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#include <sys/types.h> |
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#include <sys/ioctl.h> |
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#include <sys/mman.h> |
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#include <sys/vfs.h> |
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#include <linux/kvm.h> |
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#include "qemu-common.h" |
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#include "qemu/timer.h" |
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#include "sysemu/sysemu.h" |
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#include "sysemu/kvm.h" |
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#include "kvm_ppc.h" |
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#include "cpu.h" |
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#include "sysemu/cpus.h" |
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#include "sysemu/device_tree.h" |
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#include "mmu-hash64.h" |
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#include "hw/sysbus.h" |
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#include "hw/ppc/spapr.h" |
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#include "hw/ppc/spapr_vio.h" |
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#include "sysemu/watchdog.h" |
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//#define DEBUG_KVM
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#ifdef DEBUG_KVM
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#define dprintf(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
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#else
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#define dprintf(fmt, ...) \
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do { } while (0) |
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#endif
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#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" |
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const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
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KVM_CAP_LAST_INFO |
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}; |
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static int cap_interrupt_unset = false; |
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static int cap_interrupt_level = false; |
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static int cap_segstate; |
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static int cap_booke_sregs; |
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static int cap_ppc_smt; |
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static int cap_ppc_rma; |
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static int cap_spapr_tce; |
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static int cap_hior; |
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static int cap_one_reg; |
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static int cap_epr; |
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static int cap_ppc_watchdog; |
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static int cap_papr; |
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static int cap_htab_fd; |
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/* XXX We have a race condition where we actually have a level triggered
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* interrupt, but the infrastructure can't expose that yet, so the guest
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* takes but ignores it, goes to sleep and never gets notified that there's
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* still an interrupt pending.
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*
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* As a quick workaround, let's just wake up again 20 ms after we injected
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* an interrupt. That way we can assure that we're always reinjecting
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* interrupts in case the guest swallowed them.
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*/
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static QEMUTimer *idle_timer;
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static void kvm_kick_cpu(void *opaque) |
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{ |
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PowerPCCPU *cpu = opaque; |
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qemu_cpu_kick(CPU(cpu)); |
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} |
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static int kvm_ppc_register_host_cpu_type(void); |
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int kvm_arch_init(KVMState *s)
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{ |
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cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); |
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cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL); |
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cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); |
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cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); |
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cap_ppc_smt = kvm_check_extension(s, KVM_CAP_PPC_SMT); |
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cap_ppc_rma = kvm_check_extension(s, KVM_CAP_PPC_RMA); |
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cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); |
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cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); |
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cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); |
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cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); |
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cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); |
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/* Note: we don't set cap_papr here, because this capability is
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* only activated after this by kvmppc_set_papr() */
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cap_htab_fd = kvm_check_extension(s, KVM_CAP_PPC_HTAB_FD); |
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if (!cap_interrupt_level) {
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fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
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"VM to stall at times!\n");
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} |
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kvm_ppc_register_host_cpu_type(); |
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return 0; |
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} |
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static int kvm_arch_sync_sregs(PowerPCCPU *cpu) |
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{ |
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CPUPPCState *cenv = &cpu->env; |
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CPUState *cs = CPU(cpu); |
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struct kvm_sregs sregs;
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int ret;
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if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
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/* What we're really trying to say is "if we're on BookE, we use
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the native PVR for now". This is the only sane way to check
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it though, so we potentially confuse users that they can run
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BookE guests on BookS. Let's hope nobody dares enough :) */
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return 0; |
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} else {
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if (!cap_segstate) {
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fprintf(stderr, "kvm error: missing PVR setting capability\n");
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return -ENOSYS;
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} |
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} |
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ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
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if (ret) {
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return ret;
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} |
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sregs.pvr = cenv->spr[SPR_PVR]; |
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return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
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} |
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/* Set up a shared TLB array with KVM */
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static int kvm_booke206_tlb_init(PowerPCCPU *cpu) |
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{ |
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CPUPPCState *env = &cpu->env; |
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CPUState *cs = CPU(cpu); |
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struct kvm_book3e_206_tlb_params params = {};
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struct kvm_config_tlb cfg = {};
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struct kvm_enable_cap encap = {};
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unsigned int entries = 0; |
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int ret, i;
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if (!kvm_enabled() ||
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!kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { |
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return 0; |
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} |
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assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); |
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for (i = 0; i < BOOKE206_MAX_TLBN; i++) { |
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params.tlb_sizes[i] = booke206_tlb_size(env, i); |
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params.tlb_ways[i] = booke206_tlb_ways(env, i); |
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entries += params.tlb_sizes[i]; |
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} |
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assert(entries == env->nb_tlb); |
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assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); |
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env->tlb_dirty = true;
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cfg.array = (uintptr_t)env->tlb.tlbm; |
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cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
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cfg.params = (uintptr_t)¶ms; |
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cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; |
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encap.cap = KVM_CAP_SW_TLB; |
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encap.args[0] = (uintptr_t)&cfg;
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ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap); |
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if (ret < 0) { |
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fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
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__func__, strerror(-ret)); |
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return ret;
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} |
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env->kvm_sw_tlb = true;
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return 0; |
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} |
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#if defined(TARGET_PPC64)
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static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, |
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struct kvm_ppc_smmu_info *info)
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{ |
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CPUPPCState *env = &cpu->env; |
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CPUState *cs = CPU(cpu); |
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memset(info, 0, sizeof(*info)); |
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/* We don't have the new KVM_PPC_GET_SMMU_INFO ioctl, so
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* need to "guess" what the supported page sizes are.
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*
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* For that to work we make a few assumptions:
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*
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* - If KVM_CAP_PPC_GET_PVINFO is supported we are running "PR"
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* KVM which only supports 4K and 16M pages, but supports them
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* regardless of the backing store characteritics. We also don't
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* support 1T segments.
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*
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* This is safe as if HV KVM ever supports that capability or PR
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* KVM grows supports for more page/segment sizes, those versions
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* will have implemented KVM_CAP_PPC_GET_SMMU_INFO and thus we
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* will not hit this fallback
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*
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* - Else we are running HV KVM. This means we only support page
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* sizes that fit in the backing store. Additionally we only
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* advertize 64K pages if the processor is ARCH 2.06 and we assume
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* P7 encodings for the SLB and hash table. Here too, we assume
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* support for any newer processor will mean a kernel that
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* implements KVM_CAP_PPC_GET_SMMU_INFO and thus doesn't hit
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* this fallback.
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*/
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if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO)) {
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/* No flags */
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info->flags = 0;
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info->slb_size = 64;
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/* Standard 4k base page size segment */
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info->sps[0].page_shift = 12; |
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info->sps[0].slb_enc = 0; |
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info->sps[0].enc[0].page_shift = 12; |
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info->sps[0].enc[0].pte_enc = 0; |
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/* Standard 16M large page size segment */
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info->sps[1].page_shift = 24; |
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info->sps[1].slb_enc = SLB_VSID_L;
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info->sps[1].enc[0].page_shift = 24; |
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info->sps[1].enc[0].pte_enc = 0; |
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} else {
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int i = 0; |
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/* HV KVM has backing store size restrictions */
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info->flags = KVM_PPC_PAGE_SIZES_REAL; |
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if (env->mmu_model & POWERPC_MMU_1TSEG) {
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info->flags |= KVM_PPC_1T_SEGMENTS; |
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} |
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if (env->mmu_model == POWERPC_MMU_2_06) {
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info->slb_size = 32;
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} else {
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info->slb_size = 64;
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} |
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/* Standard 4k base page size segment */
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info->sps[i].page_shift = 12;
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info->sps[i].slb_enc = 0;
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info->sps[i].enc[0].page_shift = 12; |
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info->sps[i].enc[0].pte_enc = 0; |
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i++; |
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/* 64K on MMU 2.06 */
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if (env->mmu_model == POWERPC_MMU_2_06) {
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info->sps[i].page_shift = 16;
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info->sps[i].slb_enc = 0x110;
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info->sps[i].enc[0].page_shift = 16; |
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info->sps[i].enc[0].pte_enc = 1; |
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i++; |
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} |
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/* Standard 16M large page size segment */
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info->sps[i].page_shift = 24;
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info->sps[i].slb_enc = SLB_VSID_L; |
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info->sps[i].enc[0].page_shift = 24; |
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info->sps[i].enc[0].pte_enc = 0; |
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} |
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} |
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static void kvm_get_smmu_info(PowerPCCPU *cpu, struct kvm_ppc_smmu_info *info) |
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{ |
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CPUState *cs = CPU(cpu); |
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int ret;
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if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
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ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_SMMU_INFO, info); |
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if (ret == 0) { |
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return;
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} |
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} |
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kvm_get_fallback_smmu_info(cpu, info); |
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} |
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static long getrampagesize(void) |
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{ |
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struct statfs fs;
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int ret;
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if (!mem_path) {
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/* guest RAM is backed by normal anonymous pages */
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return getpagesize();
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} |
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do {
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ret = statfs(mem_path, &fs); |
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} while (ret != 0 && errno == EINTR); |
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if (ret != 0) { |
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fprintf(stderr, "Couldn't statfs() memory path: %s\n",
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strerror(errno)); |
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exit(1);
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} |
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#define HUGETLBFS_MAGIC 0x958458f6 |
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if (fs.f_type != HUGETLBFS_MAGIC) {
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/* Explicit mempath, but it's ordinary pages */
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return getpagesize();
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} |
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/* It's hugepage, return the huge page size */
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return fs.f_bsize;
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} |
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static bool kvm_valid_page_size(uint32_t flags, long rampgsize, uint32_t shift) |
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{ |
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if (!(flags & KVM_PPC_PAGE_SIZES_REAL)) {
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return true; |
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} |
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return (1ul << shift) <= rampgsize; |
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} |
337 |
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static void kvm_fixup_page_sizes(PowerPCCPU *cpu) |
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{ |
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static struct kvm_ppc_smmu_info smmu_info; |
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static bool has_smmu_info; |
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CPUPPCState *env = &cpu->env; |
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long rampagesize;
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int iq, ik, jq, jk;
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/* We only handle page sizes for 64-bit server guests for now */
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if (!(env->mmu_model & POWERPC_MMU_64)) {
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return;
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} |
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/* Collect MMU info from kernel if not already */
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if (!has_smmu_info) {
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kvm_get_smmu_info(cpu, &smmu_info); |
354 |
has_smmu_info = true;
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} |
356 |
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rampagesize = getrampagesize(); |
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/* Convert to QEMU form */
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memset(&env->sps, 0, sizeof(env->sps)); |
361 |
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for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) { |
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struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq];
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struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik];
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if (!kvm_valid_page_size(smmu_info.flags, rampagesize,
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ksps->page_shift)) { |
368 |
continue;
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} |
370 |
qsps->page_shift = ksps->page_shift; |
371 |
qsps->slb_enc = ksps->slb_enc; |
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for (jk = jq = 0; jk < KVM_PPC_PAGE_SIZES_MAX_SZ; jk++) { |
373 |
if (!kvm_valid_page_size(smmu_info.flags, rampagesize,
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ksps->enc[jk].page_shift)) { |
375 |
continue;
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} |
377 |
qsps->enc[jq].page_shift = ksps->enc[jk].page_shift; |
378 |
qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc; |
379 |
if (++jq >= PPC_PAGE_SIZES_MAX_SZ) {
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break;
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} |
382 |
} |
383 |
if (++iq >= PPC_PAGE_SIZES_MAX_SZ) {
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break;
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} |
386 |
} |
387 |
env->slb_nr = smmu_info.slb_size; |
388 |
if (smmu_info.flags & KVM_PPC_1T_SEGMENTS) {
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env->mmu_model |= POWERPC_MMU_1TSEG; |
390 |
} else {
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env->mmu_model &= ~POWERPC_MMU_1TSEG; |
392 |
} |
393 |
} |
394 |
#else /* defined (TARGET_PPC64) */ |
395 |
|
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static inline void kvm_fixup_page_sizes(PowerPCCPU *cpu) |
397 |
{ |
398 |
} |
399 |
|
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#endif /* !defined (TARGET_PPC64) */ |
401 |
|
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unsigned long kvm_arch_vcpu_id(CPUState *cpu) |
403 |
{ |
404 |
return cpu->cpu_index;
|
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} |
406 |
|
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int kvm_arch_init_vcpu(CPUState *cs)
|
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{ |
409 |
PowerPCCPU *cpu = POWERPC_CPU(cs); |
410 |
CPUPPCState *cenv = &cpu->env; |
411 |
int ret;
|
412 |
|
413 |
/* Gather server mmu info from KVM and update the CPU state */
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kvm_fixup_page_sizes(cpu); |
415 |
|
416 |
/* Synchronize sregs with kvm */
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417 |
ret = kvm_arch_sync_sregs(cpu); |
418 |
if (ret) {
|
419 |
return ret;
|
420 |
} |
421 |
|
422 |
idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_cpu, cpu); |
423 |
|
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/* Some targets support access to KVM's guest TLB. */
|
425 |
switch (cenv->mmu_model) {
|
426 |
case POWERPC_MMU_BOOKE206:
|
427 |
ret = kvm_booke206_tlb_init(cpu); |
428 |
break;
|
429 |
default:
|
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break;
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431 |
} |
432 |
|
433 |
return ret;
|
434 |
} |
435 |
|
436 |
void kvm_arch_reset_vcpu(CPUState *cpu)
|
437 |
{ |
438 |
} |
439 |
|
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static void kvm_sw_tlb_put(PowerPCCPU *cpu) |
441 |
{ |
442 |
CPUPPCState *env = &cpu->env; |
443 |
CPUState *cs = CPU(cpu); |
444 |
struct kvm_dirty_tlb dirty_tlb;
|
445 |
unsigned char *bitmap; |
446 |
int ret;
|
447 |
|
448 |
if (!env->kvm_sw_tlb) {
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return;
|
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} |
451 |
|
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bitmap = g_malloc((env->nb_tlb + 7) / 8); |
453 |
memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); |
454 |
|
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dirty_tlb.bitmap = (uintptr_t)bitmap; |
456 |
dirty_tlb.num_dirty = env->nb_tlb; |
457 |
|
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ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); |
459 |
if (ret) {
|
460 |
fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
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__func__, strerror(-ret)); |
462 |
} |
463 |
|
464 |
g_free(bitmap); |
465 |
} |
466 |
|
467 |
static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) |
468 |
{ |
469 |
PowerPCCPU *cpu = POWERPC_CPU(cs); |
470 |
CPUPPCState *env = &cpu->env; |
471 |
union {
|
472 |
uint32_t u32; |
473 |
uint64_t u64; |
474 |
} val; |
475 |
struct kvm_one_reg reg = {
|
476 |
.id = id, |
477 |
.addr = (uintptr_t) &val, |
478 |
}; |
479 |
int ret;
|
480 |
|
481 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
482 |
if (ret != 0) { |
483 |
fprintf(stderr, "Warning: Unable to retrieve SPR %d from KVM: %s\n",
|
484 |
spr, strerror(errno)); |
485 |
} else {
|
486 |
switch (id & KVM_REG_SIZE_MASK) {
|
487 |
case KVM_REG_SIZE_U32:
|
488 |
env->spr[spr] = val.u32; |
489 |
break;
|
490 |
|
491 |
case KVM_REG_SIZE_U64:
|
492 |
env->spr[spr] = val.u64; |
493 |
break;
|
494 |
|
495 |
default:
|
496 |
/* Don't handle this size yet */
|
497 |
abort(); |
498 |
} |
499 |
} |
500 |
} |
501 |
|
502 |
static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) |
503 |
{ |
504 |
PowerPCCPU *cpu = POWERPC_CPU(cs); |
505 |
CPUPPCState *env = &cpu->env; |
506 |
union {
|
507 |
uint32_t u32; |
508 |
uint64_t u64; |
509 |
} val; |
510 |
struct kvm_one_reg reg = {
|
511 |
.id = id, |
512 |
.addr = (uintptr_t) &val, |
513 |
}; |
514 |
int ret;
|
515 |
|
516 |
switch (id & KVM_REG_SIZE_MASK) {
|
517 |
case KVM_REG_SIZE_U32:
|
518 |
val.u32 = env->spr[spr]; |
519 |
break;
|
520 |
|
521 |
case KVM_REG_SIZE_U64:
|
522 |
val.u64 = env->spr[spr]; |
523 |
break;
|
524 |
|
525 |
default:
|
526 |
/* Don't handle this size yet */
|
527 |
abort(); |
528 |
} |
529 |
|
530 |
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
531 |
if (ret != 0) { |
532 |
fprintf(stderr, "Warning: Unable to set SPR %d to KVM: %s\n",
|
533 |
spr, strerror(errno)); |
534 |
} |
535 |
} |
536 |
|
537 |
static int kvm_put_fp(CPUState *cs) |
538 |
{ |
539 |
PowerPCCPU *cpu = POWERPC_CPU(cs); |
540 |
CPUPPCState *env = &cpu->env; |
541 |
struct kvm_one_reg reg;
|
542 |
int i;
|
543 |
int ret;
|
544 |
|
545 |
if (env->insns_flags & PPC_FLOAT) {
|
546 |
uint64_t fpscr = env->fpscr; |
547 |
bool vsx = !!(env->insns_flags2 & PPC2_VSX);
|
548 |
|
549 |
reg.id = KVM_REG_PPC_FPSCR; |
550 |
reg.addr = (uintptr_t)&fpscr; |
551 |
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
552 |
if (ret < 0) { |
553 |
dprintf("Unable to set FPSCR to KVM: %s\n", strerror(errno));
|
554 |
return ret;
|
555 |
} |
556 |
|
557 |
for (i = 0; i < 32; i++) { |
558 |
uint64_t vsr[2];
|
559 |
|
560 |
vsr[0] = float64_val(env->fpr[i]);
|
561 |
vsr[1] = env->vsr[i];
|
562 |
reg.addr = (uintptr_t) &vsr; |
563 |
reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); |
564 |
|
565 |
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
566 |
if (ret < 0) { |
567 |
dprintf("Unable to set %s%d to KVM: %s\n", vsx ? "VSR" : "FPR", |
568 |
i, strerror(errno)); |
569 |
return ret;
|
570 |
} |
571 |
} |
572 |
} |
573 |
|
574 |
if (env->insns_flags & PPC_ALTIVEC) {
|
575 |
reg.id = KVM_REG_PPC_VSCR; |
576 |
reg.addr = (uintptr_t)&env->vscr; |
577 |
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
578 |
if (ret < 0) { |
579 |
dprintf("Unable to set VSCR to KVM: %s\n", strerror(errno));
|
580 |
return ret;
|
581 |
} |
582 |
|
583 |
for (i = 0; i < 32; i++) { |
584 |
reg.id = KVM_REG_PPC_VR(i); |
585 |
reg.addr = (uintptr_t)&env->avr[i]; |
586 |
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
587 |
if (ret < 0) { |
588 |
dprintf("Unable to set VR%d to KVM: %s\n", i, strerror(errno));
|
589 |
return ret;
|
590 |
} |
591 |
} |
592 |
} |
593 |
|
594 |
return 0; |
595 |
} |
596 |
|
597 |
static int kvm_get_fp(CPUState *cs) |
598 |
{ |
599 |
PowerPCCPU *cpu = POWERPC_CPU(cs); |
600 |
CPUPPCState *env = &cpu->env; |
601 |
struct kvm_one_reg reg;
|
602 |
int i;
|
603 |
int ret;
|
604 |
|
605 |
if (env->insns_flags & PPC_FLOAT) {
|
606 |
uint64_t fpscr; |
607 |
bool vsx = !!(env->insns_flags2 & PPC2_VSX);
|
608 |
|
609 |
reg.id = KVM_REG_PPC_FPSCR; |
610 |
reg.addr = (uintptr_t)&fpscr; |
611 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
612 |
if (ret < 0) { |
613 |
dprintf("Unable to get FPSCR from KVM: %s\n", strerror(errno));
|
614 |
return ret;
|
615 |
} else {
|
616 |
env->fpscr = fpscr; |
617 |
} |
618 |
|
619 |
for (i = 0; i < 32; i++) { |
620 |
uint64_t vsr[2];
|
621 |
|
622 |
reg.addr = (uintptr_t) &vsr; |
623 |
reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); |
624 |
|
625 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
626 |
if (ret < 0) { |
627 |
dprintf("Unable to get %s%d from KVM: %s\n",
|
628 |
vsx ? "VSR" : "FPR", i, strerror(errno)); |
629 |
return ret;
|
630 |
} else {
|
631 |
env->fpr[i] = vsr[0];
|
632 |
if (vsx) {
|
633 |
env->vsr[i] = vsr[1];
|
634 |
} |
635 |
} |
636 |
} |
637 |
} |
638 |
|
639 |
if (env->insns_flags & PPC_ALTIVEC) {
|
640 |
reg.id = KVM_REG_PPC_VSCR; |
641 |
reg.addr = (uintptr_t)&env->vscr; |
642 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
643 |
if (ret < 0) { |
644 |
dprintf("Unable to get VSCR from KVM: %s\n", strerror(errno));
|
645 |
return ret;
|
646 |
} |
647 |
|
648 |
for (i = 0; i < 32; i++) { |
649 |
reg.id = KVM_REG_PPC_VR(i); |
650 |
reg.addr = (uintptr_t)&env->avr[i]; |
651 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
652 |
if (ret < 0) { |
653 |
dprintf("Unable to get VR%d from KVM: %s\n",
|
654 |
i, strerror(errno)); |
655 |
return ret;
|
656 |
} |
657 |
} |
658 |
} |
659 |
|
660 |
return 0; |
661 |
} |
662 |
|
663 |
#if defined(TARGET_PPC64)
|
664 |
static int kvm_get_vpa(CPUState *cs) |
665 |
{ |
666 |
PowerPCCPU *cpu = POWERPC_CPU(cs); |
667 |
CPUPPCState *env = &cpu->env; |
668 |
struct kvm_one_reg reg;
|
669 |
int ret;
|
670 |
|
671 |
reg.id = KVM_REG_PPC_VPA_ADDR; |
672 |
reg.addr = (uintptr_t)&env->vpa_addr; |
673 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
674 |
if (ret < 0) { |
675 |
dprintf("Unable to get VPA address from KVM: %s\n", strerror(errno));
|
676 |
return ret;
|
677 |
} |
678 |
|
679 |
assert((uintptr_t)&env->slb_shadow_size |
680 |
== ((uintptr_t)&env->slb_shadow_addr + 8));
|
681 |
reg.id = KVM_REG_PPC_VPA_SLB; |
682 |
reg.addr = (uintptr_t)&env->slb_shadow_addr; |
683 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
684 |
if (ret < 0) { |
685 |
dprintf("Unable to get SLB shadow state from KVM: %s\n",
|
686 |
strerror(errno)); |
687 |
return ret;
|
688 |
} |
689 |
|
690 |
assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8));
|
691 |
reg.id = KVM_REG_PPC_VPA_DTL; |
692 |
reg.addr = (uintptr_t)&env->dtl_addr; |
693 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
694 |
if (ret < 0) { |
695 |
dprintf("Unable to get dispatch trace log state from KVM: %s\n",
|
696 |
strerror(errno)); |
697 |
return ret;
|
698 |
} |
699 |
|
700 |
return 0; |
701 |
} |
702 |
|
703 |
static int kvm_put_vpa(CPUState *cs) |
704 |
{ |
705 |
PowerPCCPU *cpu = POWERPC_CPU(cs); |
706 |
CPUPPCState *env = &cpu->env; |
707 |
struct kvm_one_reg reg;
|
708 |
int ret;
|
709 |
|
710 |
/* SLB shadow or DTL can't be registered unless a master VPA is
|
711 |
* registered. That means when restoring state, if a VPA *is*
|
712 |
* registered, we need to set that up first. If not, we need to
|
713 |
* deregister the others before deregistering the master VPA */
|
714 |
assert(env->vpa_addr || !(env->slb_shadow_addr || env->dtl_addr)); |
715 |
|
716 |
if (env->vpa_addr) {
|
717 |
reg.id = KVM_REG_PPC_VPA_ADDR; |
718 |
reg.addr = (uintptr_t)&env->vpa_addr; |
719 |
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
720 |
if (ret < 0) { |
721 |
dprintf("Unable to set VPA address to KVM: %s\n", strerror(errno));
|
722 |
return ret;
|
723 |
} |
724 |
} |
725 |
|
726 |
assert((uintptr_t)&env->slb_shadow_size |
727 |
== ((uintptr_t)&env->slb_shadow_addr + 8));
|
728 |
reg.id = KVM_REG_PPC_VPA_SLB; |
729 |
reg.addr = (uintptr_t)&env->slb_shadow_addr; |
730 |
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
731 |
if (ret < 0) { |
732 |
dprintf("Unable to set SLB shadow state to KVM: %s\n", strerror(errno));
|
733 |
return ret;
|
734 |
} |
735 |
|
736 |
assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8));
|
737 |
reg.id = KVM_REG_PPC_VPA_DTL; |
738 |
reg.addr = (uintptr_t)&env->dtl_addr; |
739 |
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
740 |
if (ret < 0) { |
741 |
dprintf("Unable to set dispatch trace log state to KVM: %s\n",
|
742 |
strerror(errno)); |
743 |
return ret;
|
744 |
} |
745 |
|
746 |
if (!env->vpa_addr) {
|
747 |
reg.id = KVM_REG_PPC_VPA_ADDR; |
748 |
reg.addr = (uintptr_t)&env->vpa_addr; |
749 |
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
750 |
if (ret < 0) { |
751 |
dprintf("Unable to set VPA address to KVM: %s\n", strerror(errno));
|
752 |
return ret;
|
753 |
} |
754 |
} |
755 |
|
756 |
return 0; |
757 |
} |
758 |
#endif /* TARGET_PPC64 */ |
759 |
|
760 |
int kvm_arch_put_registers(CPUState *cs, int level) |
761 |
{ |
762 |
PowerPCCPU *cpu = POWERPC_CPU(cs); |
763 |
CPUPPCState *env = &cpu->env; |
764 |
struct kvm_regs regs;
|
765 |
int ret;
|
766 |
int i;
|
767 |
|
768 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); |
769 |
if (ret < 0) { |
770 |
return ret;
|
771 |
} |
772 |
|
773 |
regs.ctr = env->ctr; |
774 |
regs.lr = env->lr; |
775 |
regs.xer = cpu_read_xer(env); |
776 |
regs.msr = env->msr; |
777 |
regs.pc = env->nip; |
778 |
|
779 |
regs.srr0 = env->spr[SPR_SRR0]; |
780 |
regs.srr1 = env->spr[SPR_SRR1]; |
781 |
|
782 |
regs.sprg0 = env->spr[SPR_SPRG0]; |
783 |
regs.sprg1 = env->spr[SPR_SPRG1]; |
784 |
regs.sprg2 = env->spr[SPR_SPRG2]; |
785 |
regs.sprg3 = env->spr[SPR_SPRG3]; |
786 |
regs.sprg4 = env->spr[SPR_SPRG4]; |
787 |
regs.sprg5 = env->spr[SPR_SPRG5]; |
788 |
regs.sprg6 = env->spr[SPR_SPRG6]; |
789 |
regs.sprg7 = env->spr[SPR_SPRG7]; |
790 |
|
791 |
regs.pid = env->spr[SPR_BOOKE_PID]; |
792 |
|
793 |
for (i = 0;i < 32; i++) |
794 |
regs.gpr[i] = env->gpr[i]; |
795 |
|
796 |
regs.cr = 0;
|
797 |
for (i = 0; i < 8; i++) { |
798 |
regs.cr |= (env->crf[i] & 15) << (4 * (7 - i)); |
799 |
} |
800 |
|
801 |
ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); |
802 |
if (ret < 0) |
803 |
return ret;
|
804 |
|
805 |
kvm_put_fp(cs); |
806 |
|
807 |
if (env->tlb_dirty) {
|
808 |
kvm_sw_tlb_put(cpu); |
809 |
env->tlb_dirty = false;
|
810 |
} |
811 |
|
812 |
if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
|
813 |
struct kvm_sregs sregs;
|
814 |
|
815 |
sregs.pvr = env->spr[SPR_PVR]; |
816 |
|
817 |
sregs.u.s.sdr1 = env->spr[SPR_SDR1]; |
818 |
|
819 |
/* Sync SLB */
|
820 |
#ifdef TARGET_PPC64
|
821 |
for (i = 0; i < 64; i++) { |
822 |
sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; |
823 |
sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; |
824 |
} |
825 |
#endif
|
826 |
|
827 |
/* Sync SRs */
|
828 |
for (i = 0; i < 16; i++) { |
829 |
sregs.u.s.ppc32.sr[i] = env->sr[i]; |
830 |
} |
831 |
|
832 |
/* Sync BATs */
|
833 |
for (i = 0; i < 8; i++) { |
834 |
/* Beware. We have to swap upper and lower bits here */
|
835 |
sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) |
836 |
| env->DBAT[1][i];
|
837 |
sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) |
838 |
| env->IBAT[1][i];
|
839 |
} |
840 |
|
841 |
ret = kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); |
842 |
if (ret) {
|
843 |
return ret;
|
844 |
} |
845 |
} |
846 |
|
847 |
if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
|
848 |
kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); |
849 |
} |
850 |
|
851 |
if (cap_one_reg) {
|
852 |
int i;
|
853 |
|
854 |
/* We deliberately ignore errors here, for kernels which have
|
855 |
* the ONE_REG calls, but don't support the specific
|
856 |
* registers, there's a reasonable chance things will still
|
857 |
* work, at least until we try to migrate. */
|
858 |
for (i = 0; i < 1024; i++) { |
859 |
uint64_t id = env->spr_cb[i].one_reg_id; |
860 |
|
861 |
if (id != 0) { |
862 |
kvm_put_one_spr(cs, id, i); |
863 |
} |
864 |
} |
865 |
|
866 |
#ifdef TARGET_PPC64
|
867 |
if (cap_papr) {
|
868 |
if (kvm_put_vpa(cs) < 0) { |
869 |
dprintf("Warning: Unable to set VPA information to KVM\n");
|
870 |
} |
871 |
} |
872 |
#endif /* TARGET_PPC64 */ |
873 |
} |
874 |
|
875 |
return ret;
|
876 |
} |
877 |
|
878 |
int kvm_arch_get_registers(CPUState *cs)
|
879 |
{ |
880 |
PowerPCCPU *cpu = POWERPC_CPU(cs); |
881 |
CPUPPCState *env = &cpu->env; |
882 |
struct kvm_regs regs;
|
883 |
struct kvm_sregs sregs;
|
884 |
uint32_t cr; |
885 |
int i, ret;
|
886 |
|
887 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); |
888 |
if (ret < 0) |
889 |
return ret;
|
890 |
|
891 |
cr = regs.cr; |
892 |
for (i = 7; i >= 0; i--) { |
893 |
env->crf[i] = cr & 15;
|
894 |
cr >>= 4;
|
895 |
} |
896 |
|
897 |
env->ctr = regs.ctr; |
898 |
env->lr = regs.lr; |
899 |
cpu_write_xer(env, regs.xer); |
900 |
env->msr = regs.msr; |
901 |
env->nip = regs.pc; |
902 |
|
903 |
env->spr[SPR_SRR0] = regs.srr0; |
904 |
env->spr[SPR_SRR1] = regs.srr1; |
905 |
|
906 |
env->spr[SPR_SPRG0] = regs.sprg0; |
907 |
env->spr[SPR_SPRG1] = regs.sprg1; |
908 |
env->spr[SPR_SPRG2] = regs.sprg2; |
909 |
env->spr[SPR_SPRG3] = regs.sprg3; |
910 |
env->spr[SPR_SPRG4] = regs.sprg4; |
911 |
env->spr[SPR_SPRG5] = regs.sprg5; |
912 |
env->spr[SPR_SPRG6] = regs.sprg6; |
913 |
env->spr[SPR_SPRG7] = regs.sprg7; |
914 |
|
915 |
env->spr[SPR_BOOKE_PID] = regs.pid; |
916 |
|
917 |
for (i = 0;i < 32; i++) |
918 |
env->gpr[i] = regs.gpr[i]; |
919 |
|
920 |
kvm_get_fp(cs); |
921 |
|
922 |
if (cap_booke_sregs) {
|
923 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
924 |
if (ret < 0) { |
925 |
return ret;
|
926 |
} |
927 |
|
928 |
if (sregs.u.e.features & KVM_SREGS_E_BASE) {
|
929 |
env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; |
930 |
env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; |
931 |
env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; |
932 |
env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; |
933 |
env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; |
934 |
env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; |
935 |
env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; |
936 |
env->spr[SPR_DECR] = sregs.u.e.dec; |
937 |
env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
|
938 |
env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
|
939 |
env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; |
940 |
} |
941 |
|
942 |
if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
|
943 |
env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; |
944 |
env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; |
945 |
env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; |
946 |
env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; |
947 |
env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; |
948 |
} |
949 |
|
950 |
if (sregs.u.e.features & KVM_SREGS_E_64) {
|
951 |
env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; |
952 |
} |
953 |
|
954 |
if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
|
955 |
env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; |
956 |
} |
957 |
|
958 |
if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
|
959 |
env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
|
960 |
env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
|
961 |
env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
|
962 |
env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
|
963 |
env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
|
964 |
env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
|
965 |
env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
|
966 |
env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
|
967 |
env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
|
968 |
env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
|
969 |
env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
|
970 |
env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
|
971 |
env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
|
972 |
env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
|
973 |
env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
|
974 |
env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
|
975 |
|
976 |
if (sregs.u.e.features & KVM_SREGS_E_SPE) {
|
977 |
env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
|
978 |
env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
|
979 |
env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
|
980 |
} |
981 |
|
982 |
if (sregs.u.e.features & KVM_SREGS_E_PM) {
|
983 |
env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
|
984 |
} |
985 |
|
986 |
if (sregs.u.e.features & KVM_SREGS_E_PC) {
|
987 |
env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
|
988 |
env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
|
989 |
} |
990 |
} |
991 |
|
992 |
if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
|
993 |
env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; |
994 |
env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; |
995 |
env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; |
996 |
env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
|
997 |
env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; |
998 |
env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; |
999 |
env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
|
1000 |
env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; |
1001 |
env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
|
1002 |
env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
|
1003 |
} |
1004 |
|
1005 |
if (sregs.u.e.features & KVM_SREGS_EXP) {
|
1006 |
env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; |
1007 |
} |
1008 |
|
1009 |
if (sregs.u.e.features & KVM_SREGS_E_PD) {
|
1010 |
env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; |
1011 |
env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; |
1012 |
} |
1013 |
|
1014 |
if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
|
1015 |
env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; |
1016 |
env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; |
1017 |
env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; |
1018 |
|
1019 |
if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
|
1020 |
env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; |
1021 |
env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; |
1022 |
} |
1023 |
} |
1024 |
} |
1025 |
|
1026 |
if (cap_segstate) {
|
1027 |
ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
1028 |
if (ret < 0) { |
1029 |
return ret;
|
1030 |
} |
1031 |
|
1032 |
ppc_store_sdr1(env, sregs.u.s.sdr1); |
1033 |
|
1034 |
/* Sync SLB */
|
1035 |
#ifdef TARGET_PPC64
|
1036 |
for (i = 0; i < 64; i++) { |
1037 |
ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe, |
1038 |
sregs.u.s.ppc64.slb[i].slbv); |
1039 |
} |
1040 |
#endif
|
1041 |
|
1042 |
/* Sync SRs */
|
1043 |
for (i = 0; i < 16; i++) { |
1044 |
env->sr[i] = sregs.u.s.ppc32.sr[i]; |
1045 |
} |
1046 |
|
1047 |
/* Sync BATs */
|
1048 |
for (i = 0; i < 8; i++) { |
1049 |
env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; |
1050 |
env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; |
1051 |
env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; |
1052 |
env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; |
1053 |
} |
1054 |
} |
1055 |
|
1056 |
if (cap_hior) {
|
1057 |
kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); |
1058 |
} |
1059 |
|
1060 |
if (cap_one_reg) {
|
1061 |
int i;
|
1062 |
|
1063 |
/* We deliberately ignore errors here, for kernels which have
|
1064 |
* the ONE_REG calls, but don't support the specific
|
1065 |
* registers, there's a reasonable chance things will still
|
1066 |
* work, at least until we try to migrate. */
|
1067 |
for (i = 0; i < 1024; i++) { |
1068 |
uint64_t id = env->spr_cb[i].one_reg_id; |
1069 |
|
1070 |
if (id != 0) { |
1071 |
kvm_get_one_spr(cs, id, i); |
1072 |
} |
1073 |
} |
1074 |
|
1075 |
#ifdef TARGET_PPC64
|
1076 |
if (cap_papr) {
|
1077 |
if (kvm_get_vpa(cs) < 0) { |
1078 |
dprintf("Warning: Unable to get VPA information from KVM\n");
|
1079 |
} |
1080 |
} |
1081 |
#endif
|
1082 |
} |
1083 |
|
1084 |
return 0; |
1085 |
} |
1086 |
|
1087 |
int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) |
1088 |
{ |
1089 |
unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
|
1090 |
|
1091 |
if (irq != PPC_INTERRUPT_EXT) {
|
1092 |
return 0; |
1093 |
} |
1094 |
|
1095 |
if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
|
1096 |
return 0; |
1097 |
} |
1098 |
|
1099 |
kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); |
1100 |
|
1101 |
return 0; |
1102 |
} |
1103 |
|
1104 |
#if defined(TARGET_PPCEMB)
|
1105 |
#define PPC_INPUT_INT PPC40x_INPUT_INT
|
1106 |
#elif defined(TARGET_PPC64)
|
1107 |
#define PPC_INPUT_INT PPC970_INPUT_INT
|
1108 |
#else
|
1109 |
#define PPC_INPUT_INT PPC6xx_INPUT_INT
|
1110 |
#endif
|
1111 |
|
1112 |
void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) |
1113 |
{ |
1114 |
PowerPCCPU *cpu = POWERPC_CPU(cs); |
1115 |
CPUPPCState *env = &cpu->env; |
1116 |
int r;
|
1117 |
unsigned irq;
|
1118 |
|
1119 |
/* PowerPC QEMU tracks the various core input pins (interrupt, critical
|
1120 |
* interrupt, reset, etc) in PPC-specific env->irq_input_state. */
|
1121 |
if (!cap_interrupt_level &&
|
1122 |
run->ready_for_interrupt_injection && |
1123 |
(cs->interrupt_request & CPU_INTERRUPT_HARD) && |
1124 |
(env->irq_input_state & (1<<PPC_INPUT_INT)))
|
1125 |
{ |
1126 |
/* For now KVM disregards the 'irq' argument. However, in the
|
1127 |
* future KVM could cache it in-kernel to avoid a heavyweight exit
|
1128 |
* when reading the UIC.
|
1129 |
*/
|
1130 |
irq = KVM_INTERRUPT_SET; |
1131 |
|
1132 |
dprintf("injected interrupt %d\n", irq);
|
1133 |
r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq); |
1134 |
if (r < 0) { |
1135 |
printf("cpu %d fail inject %x\n", cs->cpu_index, irq);
|
1136 |
} |
1137 |
|
1138 |
/* Always wake up soon in case the interrupt was level based */
|
1139 |
qemu_mod_timer(idle_timer, qemu_get_clock_ns(vm_clock) + |
1140 |
(get_ticks_per_sec() / 50));
|
1141 |
} |
1142 |
|
1143 |
/* We don't know if there are more interrupts pending after this. However,
|
1144 |
* the guest will return to userspace in the course of handling this one
|
1145 |
* anyways, so we will get a chance to deliver the rest. */
|
1146 |
} |
1147 |
|
1148 |
void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) |
1149 |
{ |
1150 |
} |
1151 |
|
1152 |
int kvm_arch_process_async_events(CPUState *cs)
|
1153 |
{ |
1154 |
return cs->halted;
|
1155 |
} |
1156 |
|
1157 |
static int kvmppc_handle_halt(PowerPCCPU *cpu) |
1158 |
{ |
1159 |
CPUState *cs = CPU(cpu); |
1160 |
CPUPPCState *env = &cpu->env; |
1161 |
|
1162 |
if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
|
1163 |
cs->halted = 1;
|
1164 |
env->exception_index = EXCP_HLT; |
1165 |
} |
1166 |
|
1167 |
return 0; |
1168 |
} |
1169 |
|
1170 |
/* map dcr access to existing qemu dcr emulation */
|
1171 |
static int kvmppc_handle_dcr_read(CPUPPCState *env, uint32_t dcrn, uint32_t *data) |
1172 |
{ |
1173 |
if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) |
1174 |
fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
|
1175 |
|
1176 |
return 0; |
1177 |
} |
1178 |
|
1179 |
static int kvmppc_handle_dcr_write(CPUPPCState *env, uint32_t dcrn, uint32_t data) |
1180 |
{ |
1181 |
if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) |
1182 |
fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
|
1183 |
|
1184 |
return 0; |
1185 |
} |
1186 |
|
1187 |
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
1188 |
{ |
1189 |
PowerPCCPU *cpu = POWERPC_CPU(cs); |
1190 |
CPUPPCState *env = &cpu->env; |
1191 |
int ret;
|
1192 |
|
1193 |
switch (run->exit_reason) {
|
1194 |
case KVM_EXIT_DCR:
|
1195 |
if (run->dcr.is_write) {
|
1196 |
dprintf("handle dcr write\n");
|
1197 |
ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); |
1198 |
} else {
|
1199 |
dprintf("handle dcr read\n");
|
1200 |
ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); |
1201 |
} |
1202 |
break;
|
1203 |
case KVM_EXIT_HLT:
|
1204 |
dprintf("handle halt\n");
|
1205 |
ret = kvmppc_handle_halt(cpu); |
1206 |
break;
|
1207 |
#if defined(TARGET_PPC64)
|
1208 |
case KVM_EXIT_PAPR_HCALL:
|
1209 |
dprintf("handle PAPR hypercall\n");
|
1210 |
run->papr_hcall.ret = spapr_hypercall(cpu, |
1211 |
run->papr_hcall.nr, |
1212 |
run->papr_hcall.args); |
1213 |
ret = 0;
|
1214 |
break;
|
1215 |
#endif
|
1216 |
case KVM_EXIT_EPR:
|
1217 |
dprintf("handle epr\n");
|
1218 |
run->epr.epr = ldl_phys(env->mpic_iack); |
1219 |
ret = 0;
|
1220 |
break;
|
1221 |
case KVM_EXIT_WATCHDOG:
|
1222 |
dprintf("handle watchdog expiry\n");
|
1223 |
watchdog_perform_action(); |
1224 |
ret = 0;
|
1225 |
break;
|
1226 |
|
1227 |
default:
|
1228 |
fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
|
1229 |
ret = -1;
|
1230 |
break;
|
1231 |
} |
1232 |
|
1233 |
return ret;
|
1234 |
} |
1235 |
|
1236 |
int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
|
1237 |
{ |
1238 |
CPUState *cs = CPU(cpu); |
1239 |
uint32_t bits = tsr_bits; |
1240 |
struct kvm_one_reg reg = {
|
1241 |
.id = KVM_REG_PPC_OR_TSR, |
1242 |
.addr = (uintptr_t) &bits, |
1243 |
}; |
1244 |
|
1245 |
return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
1246 |
} |
1247 |
|
1248 |
int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
|
1249 |
{ |
1250 |
|
1251 |
CPUState *cs = CPU(cpu); |
1252 |
uint32_t bits = tsr_bits; |
1253 |
struct kvm_one_reg reg = {
|
1254 |
.id = KVM_REG_PPC_CLEAR_TSR, |
1255 |
.addr = (uintptr_t) &bits, |
1256 |
}; |
1257 |
|
1258 |
return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
1259 |
} |
1260 |
|
1261 |
int kvmppc_set_tcr(PowerPCCPU *cpu)
|
1262 |
{ |
1263 |
CPUState *cs = CPU(cpu); |
1264 |
CPUPPCState *env = &cpu->env; |
1265 |
uint32_t tcr = env->spr[SPR_BOOKE_TCR]; |
1266 |
|
1267 |
struct kvm_one_reg reg = {
|
1268 |
.id = KVM_REG_PPC_TCR, |
1269 |
.addr = (uintptr_t) &tcr, |
1270 |
}; |
1271 |
|
1272 |
return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
1273 |
} |
1274 |
|
1275 |
int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
|
1276 |
{ |
1277 |
CPUState *cs = CPU(cpu); |
1278 |
struct kvm_enable_cap encap = {};
|
1279 |
int ret;
|
1280 |
|
1281 |
if (!kvm_enabled()) {
|
1282 |
return -1; |
1283 |
} |
1284 |
|
1285 |
if (!cap_ppc_watchdog) {
|
1286 |
printf("warning: KVM does not support watchdog");
|
1287 |
return -1; |
1288 |
} |
1289 |
|
1290 |
encap.cap = KVM_CAP_PPC_BOOKE_WATCHDOG; |
1291 |
ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap); |
1292 |
if (ret < 0) { |
1293 |
fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
|
1294 |
__func__, strerror(-ret)); |
1295 |
return ret;
|
1296 |
} |
1297 |
|
1298 |
return ret;
|
1299 |
} |
1300 |
|
1301 |
static int read_cpuinfo(const char *field, char *value, int len) |
1302 |
{ |
1303 |
FILE *f; |
1304 |
int ret = -1; |
1305 |
int field_len = strlen(field);
|
1306 |
char line[512]; |
1307 |
|
1308 |
f = fopen("/proc/cpuinfo", "r"); |
1309 |
if (!f) {
|
1310 |
return -1; |
1311 |
} |
1312 |
|
1313 |
do {
|
1314 |
if(!fgets(line, sizeof(line), f)) { |
1315 |
break;
|
1316 |
} |
1317 |
if (!strncmp(line, field, field_len)) {
|
1318 |
pstrcpy(value, len, line); |
1319 |
ret = 0;
|
1320 |
break;
|
1321 |
} |
1322 |
} while(*line);
|
1323 |
|
1324 |
fclose(f); |
1325 |
|
1326 |
return ret;
|
1327 |
} |
1328 |
|
1329 |
uint32_t kvmppc_get_tbfreq(void)
|
1330 |
{ |
1331 |
char line[512]; |
1332 |
char *ns;
|
1333 |
uint32_t retval = get_ticks_per_sec(); |
1334 |
|
1335 |
if (read_cpuinfo("timebase", line, sizeof(line))) { |
1336 |
return retval;
|
1337 |
} |
1338 |
|
1339 |
if (!(ns = strchr(line, ':'))) { |
1340 |
return retval;
|
1341 |
} |
1342 |
|
1343 |
ns++; |
1344 |
|
1345 |
retval = atoi(ns); |
1346 |
return retval;
|
1347 |
} |
1348 |
|
1349 |
/* Try to find a device tree node for a CPU with clock-frequency property */
|
1350 |
static int kvmppc_find_cpu_dt(char *buf, int buf_len) |
1351 |
{ |
1352 |
struct dirent *dirp;
|
1353 |
DIR *dp; |
1354 |
|
1355 |
if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) { |
1356 |
printf("Can't open directory " PROC_DEVTREE_CPU "\n"); |
1357 |
return -1; |
1358 |
} |
1359 |
|
1360 |
buf[0] = '\0'; |
1361 |
while ((dirp = readdir(dp)) != NULL) { |
1362 |
FILE *f; |
1363 |
snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
|
1364 |
dirp->d_name); |
1365 |
f = fopen(buf, "r");
|
1366 |
if (f) {
|
1367 |
snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
|
1368 |
fclose(f); |
1369 |
break;
|
1370 |
} |
1371 |
buf[0] = '\0'; |
1372 |
} |
1373 |
closedir(dp); |
1374 |
if (buf[0] == '\0') { |
1375 |
printf("Unknown host!\n");
|
1376 |
return -1; |
1377 |
} |
1378 |
|
1379 |
return 0; |
1380 |
} |
1381 |
|
1382 |
/* Read a CPU node property from the host device tree that's a single
|
1383 |
* integer (32-bit or 64-bit). Returns 0 if anything goes wrong
|
1384 |
* (can't find or open the property, or doesn't understand the
|
1385 |
* format) */
|
1386 |
static uint64_t kvmppc_read_int_cpu_dt(const char *propname) |
1387 |
{ |
1388 |
char buf[PATH_MAX];
|
1389 |
union {
|
1390 |
uint32_t v32; |
1391 |
uint64_t v64; |
1392 |
} u; |
1393 |
FILE *f; |
1394 |
int len;
|
1395 |
|
1396 |
if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { |
1397 |
return -1; |
1398 |
} |
1399 |
|
1400 |
strncat(buf, "/", sizeof(buf) - strlen(buf)); |
1401 |
strncat(buf, propname, sizeof(buf) - strlen(buf));
|
1402 |
|
1403 |
f = fopen(buf, "rb");
|
1404 |
if (!f) {
|
1405 |
return -1; |
1406 |
} |
1407 |
|
1408 |
len = fread(&u, 1, sizeof(u), f); |
1409 |
fclose(f); |
1410 |
switch (len) {
|
1411 |
case 4: |
1412 |
/* property is a 32-bit quantity */
|
1413 |
return be32_to_cpu(u.v32);
|
1414 |
case 8: |
1415 |
return be64_to_cpu(u.v64);
|
1416 |
} |
1417 |
|
1418 |
return 0; |
1419 |
} |
1420 |
|
1421 |
uint64_t kvmppc_get_clockfreq(void)
|
1422 |
{ |
1423 |
return kvmppc_read_int_cpu_dt("clock-frequency"); |
1424 |
} |
1425 |
|
1426 |
uint32_t kvmppc_get_vmx(void)
|
1427 |
{ |
1428 |
return kvmppc_read_int_cpu_dt("ibm,vmx"); |
1429 |
} |
1430 |
|
1431 |
uint32_t kvmppc_get_dfp(void)
|
1432 |
{ |
1433 |
return kvmppc_read_int_cpu_dt("ibm,dfp"); |
1434 |
} |
1435 |
|
1436 |
static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) |
1437 |
{ |
1438 |
PowerPCCPU *cpu = ppc_env_get_cpu(env); |
1439 |
CPUState *cs = CPU(cpu); |
1440 |
|
1441 |
if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
|
1442 |
!kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { |
1443 |
return 0; |
1444 |
} |
1445 |
|
1446 |
return 1; |
1447 |
} |
1448 |
|
1449 |
int kvmppc_get_hasidle(CPUPPCState *env)
|
1450 |
{ |
1451 |
struct kvm_ppc_pvinfo pvinfo;
|
1452 |
|
1453 |
if (!kvmppc_get_pvinfo(env, &pvinfo) &&
|
1454 |
(pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { |
1455 |
return 1; |
1456 |
} |
1457 |
|
1458 |
return 0; |
1459 |
} |
1460 |
|
1461 |
int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) |
1462 |
{ |
1463 |
uint32_t *hc = (uint32_t*)buf; |
1464 |
struct kvm_ppc_pvinfo pvinfo;
|
1465 |
|
1466 |
if (!kvmppc_get_pvinfo(env, &pvinfo)) {
|
1467 |
memcpy(buf, pvinfo.hcall, buf_len); |
1468 |
return 0; |
1469 |
} |
1470 |
|
1471 |
/*
|
1472 |
* Fallback to always fail hypercalls:
|
1473 |
*
|
1474 |
* li r3, -1
|
1475 |
* nop
|
1476 |
* nop
|
1477 |
* nop
|
1478 |
*/
|
1479 |
|
1480 |
hc[0] = 0x3860ffff; |
1481 |
hc[1] = 0x60000000; |
1482 |
hc[2] = 0x60000000; |
1483 |
hc[3] = 0x60000000; |
1484 |
|
1485 |
return 0; |
1486 |
} |
1487 |
|
1488 |
void kvmppc_set_papr(PowerPCCPU *cpu)
|
1489 |
{ |
1490 |
CPUPPCState *env = &cpu->env; |
1491 |
CPUState *cs = CPU(cpu); |
1492 |
struct kvm_enable_cap cap = {};
|
1493 |
int ret;
|
1494 |
|
1495 |
cap.cap = KVM_CAP_PPC_PAPR; |
1496 |
ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &cap); |
1497 |
|
1498 |
if (ret) {
|
1499 |
cpu_abort(env, "This KVM version does not support PAPR\n");
|
1500 |
} |
1501 |
|
1502 |
/* Update the capability flag so we sync the right information
|
1503 |
* with kvm */
|
1504 |
cap_papr = 1;
|
1505 |
} |
1506 |
|
1507 |
void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) |
1508 |
{ |
1509 |
CPUPPCState *env = &cpu->env; |
1510 |
CPUState *cs = CPU(cpu); |
1511 |
struct kvm_enable_cap cap = {};
|
1512 |
int ret;
|
1513 |
|
1514 |
cap.cap = KVM_CAP_PPC_EPR; |
1515 |
cap.args[0] = mpic_proxy;
|
1516 |
ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &cap); |
1517 |
|
1518 |
if (ret && mpic_proxy) {
|
1519 |
cpu_abort(env, "This KVM version does not support EPR\n");
|
1520 |
} |
1521 |
} |
1522 |
|
1523 |
int kvmppc_smt_threads(void) |
1524 |
{ |
1525 |
return cap_ppc_smt ? cap_ppc_smt : 1; |
1526 |
} |
1527 |
|
1528 |
#ifdef TARGET_PPC64
|
1529 |
off_t kvmppc_alloc_rma(const char *name, MemoryRegion *sysmem) |
1530 |
{ |
1531 |
void *rma;
|
1532 |
off_t size; |
1533 |
int fd;
|
1534 |
struct kvm_allocate_rma ret;
|
1535 |
MemoryRegion *rma_region; |
1536 |
|
1537 |
/* If cap_ppc_rma == 0, contiguous RMA allocation is not supported
|
1538 |
* if cap_ppc_rma == 1, contiguous RMA allocation is supported, but
|
1539 |
* not necessary on this hardware
|
1540 |
* if cap_ppc_rma == 2, contiguous RMA allocation is needed on this hardware
|
1541 |
*
|
1542 |
* FIXME: We should allow the user to force contiguous RMA
|
1543 |
* allocation in the cap_ppc_rma==1 case.
|
1544 |
*/
|
1545 |
if (cap_ppc_rma < 2) { |
1546 |
return 0; |
1547 |
} |
1548 |
|
1549 |
fd = kvm_vm_ioctl(kvm_state, KVM_ALLOCATE_RMA, &ret); |
1550 |
if (fd < 0) { |
1551 |
fprintf(stderr, "KVM: Error on KVM_ALLOCATE_RMA: %s\n",
|
1552 |
strerror(errno)); |
1553 |
return -1; |
1554 |
} |
1555 |
|
1556 |
size = MIN(ret.rma_size, 256ul << 20); |
1557 |
|
1558 |
rma = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); |
1559 |
if (rma == MAP_FAILED) {
|
1560 |
fprintf(stderr, "KVM: Error mapping RMA: %s\n", strerror(errno));
|
1561 |
return -1; |
1562 |
}; |
1563 |
|
1564 |
rma_region = g_new(MemoryRegion, 1);
|
1565 |
memory_region_init_ram_ptr(rma_region, NULL, name, size, rma);
|
1566 |
vmstate_register_ram_global(rma_region); |
1567 |
memory_region_add_subregion(sysmem, 0, rma_region);
|
1568 |
|
1569 |
return size;
|
1570 |
} |
1571 |
|
1572 |
uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift) |
1573 |
{ |
1574 |
struct kvm_ppc_smmu_info info;
|
1575 |
long rampagesize, best_page_shift;
|
1576 |
int i;
|
1577 |
|
1578 |
if (cap_ppc_rma >= 2) { |
1579 |
return current_size;
|
1580 |
} |
1581 |
|
1582 |
/* Find the largest hardware supported page size that's less than
|
1583 |
* or equal to the (logical) backing page size of guest RAM */
|
1584 |
kvm_get_smmu_info(POWERPC_CPU(first_cpu), &info); |
1585 |
rampagesize = getrampagesize(); |
1586 |
best_page_shift = 0;
|
1587 |
|
1588 |
for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { |
1589 |
struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
|
1590 |
|
1591 |
if (!sps->page_shift) {
|
1592 |
continue;
|
1593 |
} |
1594 |
|
1595 |
if ((sps->page_shift > best_page_shift)
|
1596 |
&& ((1UL << sps->page_shift) <= rampagesize)) {
|
1597 |
best_page_shift = sps->page_shift; |
1598 |
} |
1599 |
} |
1600 |
|
1601 |
return MIN(current_size,
|
1602 |
1ULL << (best_page_shift + hash_shift - 7)); |
1603 |
} |
1604 |
#endif
|
1605 |
|
1606 |
void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd) |
1607 |
{ |
1608 |
struct kvm_create_spapr_tce args = {
|
1609 |
.liobn = liobn, |
1610 |
.window_size = window_size, |
1611 |
}; |
1612 |
long len;
|
1613 |
int fd;
|
1614 |
void *table;
|
1615 |
|
1616 |
/* Must set fd to -1 so we don't try to munmap when called for
|
1617 |
* destroying the table, which the upper layers -will- do
|
1618 |
*/
|
1619 |
*pfd = -1;
|
1620 |
if (!cap_spapr_tce) {
|
1621 |
return NULL; |
1622 |
} |
1623 |
|
1624 |
fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); |
1625 |
if (fd < 0) { |
1626 |
fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
|
1627 |
liobn); |
1628 |
return NULL; |
1629 |
} |
1630 |
|
1631 |
len = (window_size / SPAPR_TCE_PAGE_SIZE) * sizeof(uint64_t);
|
1632 |
/* FIXME: round this up to page size */
|
1633 |
|
1634 |
table = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); |
1635 |
if (table == MAP_FAILED) {
|
1636 |
fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
|
1637 |
liobn); |
1638 |
close(fd); |
1639 |
return NULL; |
1640 |
} |
1641 |
|
1642 |
*pfd = fd; |
1643 |
return table;
|
1644 |
} |
1645 |
|
1646 |
int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t window_size) |
1647 |
{ |
1648 |
long len;
|
1649 |
|
1650 |
if (fd < 0) { |
1651 |
return -1; |
1652 |
} |
1653 |
|
1654 |
len = (window_size / SPAPR_TCE_PAGE_SIZE)*sizeof(uint64_t);
|
1655 |
if ((munmap(table, len) < 0) || |
1656 |
(close(fd) < 0)) {
|
1657 |
fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
|
1658 |
strerror(errno)); |
1659 |
/* Leak the table */
|
1660 |
} |
1661 |
|
1662 |
return 0; |
1663 |
} |
1664 |
|
1665 |
int kvmppc_reset_htab(int shift_hint) |
1666 |
{ |
1667 |
uint32_t shift = shift_hint; |
1668 |
|
1669 |
if (!kvm_enabled()) {
|
1670 |
/* Full emulation, tell caller to allocate htab itself */
|
1671 |
return 0; |
1672 |
} |
1673 |
if (kvm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
|
1674 |
int ret;
|
1675 |
ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); |
1676 |
if (ret == -ENOTTY) {
|
1677 |
/* At least some versions of PR KVM advertise the
|
1678 |
* capability, but don't implement the ioctl(). Oops.
|
1679 |
* Return 0 so that we allocate the htab in qemu, as is
|
1680 |
* correct for PR. */
|
1681 |
return 0; |
1682 |
} else if (ret < 0) { |
1683 |
return ret;
|
1684 |
} |
1685 |
return shift;
|
1686 |
} |
1687 |
|
1688 |
/* We have a kernel that predates the htab reset calls. For PR
|
1689 |
* KVM, we need to allocate the htab ourselves, for an HV KVM of
|
1690 |
* this era, it has allocated a 16MB fixed size hash table
|
1691 |
* already. Kernels of this era have the GET_PVINFO capability
|
1692 |
* only on PR, so we use this hack to determine the right
|
1693 |
* answer */
|
1694 |
if (kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_PVINFO)) {
|
1695 |
/* PR - tell caller to allocate htab */
|
1696 |
return 0; |
1697 |
} else {
|
1698 |
/* HV - assume 16MB kernel allocated htab */
|
1699 |
return 24; |
1700 |
} |
1701 |
} |
1702 |
|
1703 |
static inline uint32_t mfpvr(void) |
1704 |
{ |
1705 |
uint32_t pvr; |
1706 |
|
1707 |
asm ("mfpvr %0" |
1708 |
: "=r"(pvr));
|
1709 |
return pvr;
|
1710 |
} |
1711 |
|
1712 |
static void alter_insns(uint64_t *word, uint64_t flags, bool on) |
1713 |
{ |
1714 |
if (on) {
|
1715 |
*word |= flags; |
1716 |
} else {
|
1717 |
*word &= ~flags; |
1718 |
} |
1719 |
} |
1720 |
|
1721 |
static void kvmppc_host_cpu_initfn(Object *obj) |
1722 |
{ |
1723 |
assert(kvm_enabled()); |
1724 |
} |
1725 |
|
1726 |
static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) |
1727 |
{ |
1728 |
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
1729 |
uint32_t vmx = kvmppc_get_vmx(); |
1730 |
uint32_t dfp = kvmppc_get_dfp(); |
1731 |
uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
|
1732 |
uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
|
1733 |
|
1734 |
/* Now fix up the class with information we can query from the host */
|
1735 |
|
1736 |
if (vmx != -1) { |
1737 |
/* Only override when we know what the host supports */
|
1738 |
alter_insns(&pcc->insns_flags, PPC_ALTIVEC, vmx > 0);
|
1739 |
alter_insns(&pcc->insns_flags2, PPC2_VSX, vmx > 1);
|
1740 |
} |
1741 |
if (dfp != -1) { |
1742 |
/* Only override when we know what the host supports */
|
1743 |
alter_insns(&pcc->insns_flags2, PPC2_DFP, dfp); |
1744 |
} |
1745 |
|
1746 |
if (dcache_size != -1) { |
1747 |
pcc->l1_dcache_size = dcache_size; |
1748 |
} |
1749 |
|
1750 |
if (icache_size != -1) { |
1751 |
pcc->l1_icache_size = icache_size; |
1752 |
} |
1753 |
} |
1754 |
|
1755 |
int kvmppc_fixup_cpu(PowerPCCPU *cpu)
|
1756 |
{ |
1757 |
CPUState *cs = CPU(cpu); |
1758 |
int smt;
|
1759 |
|
1760 |
/* Adjust cpu index for SMT */
|
1761 |
smt = kvmppc_smt_threads(); |
1762 |
cs->cpu_index = (cs->cpu_index / smp_threads) * smt |
1763 |
+ (cs->cpu_index % smp_threads); |
1764 |
|
1765 |
return 0; |
1766 |
} |
1767 |
|
1768 |
bool kvmppc_has_cap_epr(void) |
1769 |
{ |
1770 |
return cap_epr;
|
1771 |
} |
1772 |
|
1773 |
static int kvm_ppc_register_host_cpu_type(void) |
1774 |
{ |
1775 |
TypeInfo type_info = { |
1776 |
.name = TYPE_HOST_POWERPC_CPU, |
1777 |
.instance_init = kvmppc_host_cpu_initfn, |
1778 |
.class_init = kvmppc_host_cpu_class_init, |
1779 |
}; |
1780 |
uint32_t host_pvr = mfpvr(); |
1781 |
PowerPCCPUClass *pvr_pcc; |
1782 |
|
1783 |
pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); |
1784 |
if (pvr_pcc == NULL) { |
1785 |
return -1; |
1786 |
} |
1787 |
type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); |
1788 |
type_register(&type_info); |
1789 |
return 0; |
1790 |
} |
1791 |
|
1792 |
|
1793 |
int kvmppc_get_htab_fd(bool write) |
1794 |
{ |
1795 |
struct kvm_get_htab_fd s = {
|
1796 |
.flags = write ? KVM_GET_HTAB_WRITE : 0,
|
1797 |
.start_index = 0,
|
1798 |
}; |
1799 |
|
1800 |
if (!cap_htab_fd) {
|
1801 |
fprintf(stderr, "KVM version doesn't support saving the hash table\n");
|
1802 |
return -1; |
1803 |
} |
1804 |
|
1805 |
return kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
|
1806 |
} |
1807 |
|
1808 |
int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) |
1809 |
{ |
1810 |
int64_t starttime = qemu_get_clock_ns(rt_clock); |
1811 |
uint8_t buf[bufsize]; |
1812 |
ssize_t rc; |
1813 |
|
1814 |
do {
|
1815 |
rc = read(fd, buf, bufsize); |
1816 |
if (rc < 0) { |
1817 |
fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
|
1818 |
strerror(errno)); |
1819 |
return rc;
|
1820 |
} else if (rc) { |
1821 |
/* Kernel already retuns data in BE format for the file */
|
1822 |
qemu_put_buffer(f, buf, rc); |
1823 |
} |
1824 |
} while ((rc != 0) |
1825 |
&& ((max_ns < 0)
|
1826 |
|| ((qemu_get_clock_ns(rt_clock) - starttime) < max_ns))); |
1827 |
|
1828 |
return (rc == 0) ? 1 : 0; |
1829 |
} |
1830 |
|
1831 |
int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, |
1832 |
uint16_t n_valid, uint16_t n_invalid) |
1833 |
{ |
1834 |
struct kvm_get_htab_header *buf;
|
1835 |
size_t chunksize = sizeof(*buf) + n_valid*HASH_PTE_SIZE_64;
|
1836 |
ssize_t rc; |
1837 |
|
1838 |
buf = alloca(chunksize); |
1839 |
/* This is KVM on ppc, so this is all big-endian */
|
1840 |
buf->index = index; |
1841 |
buf->n_valid = n_valid; |
1842 |
buf->n_invalid = n_invalid; |
1843 |
|
1844 |
qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64*n_valid); |
1845 |
|
1846 |
rc = write(fd, buf, chunksize); |
1847 |
if (rc < 0) { |
1848 |
fprintf(stderr, "Error writing KVM hash table: %s\n",
|
1849 |
strerror(errno)); |
1850 |
return rc;
|
1851 |
} |
1852 |
if (rc != chunksize) {
|
1853 |
/* We should never get a short write on a single chunk */
|
1854 |
fprintf(stderr, "Short write, restoring KVM hash table\n");
|
1855 |
return -1; |
1856 |
} |
1857 |
return 0; |
1858 |
} |
1859 |
|
1860 |
bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
|
1861 |
{ |
1862 |
return true; |
1863 |
} |
1864 |
|
1865 |
int kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr) |
1866 |
{ |
1867 |
return 1; |
1868 |
} |
1869 |
|
1870 |
int kvm_arch_on_sigbus(int code, void *addr) |
1871 |
{ |
1872 |
return 1; |
1873 |
} |
1874 |
|
1875 |
void kvm_arch_init_irq_routing(KVMState *s)
|
1876 |
{ |
1877 |
} |