Revision e6a71ae3 hw/piix_pci.c
b/hw/piix_pci.c | ||
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246 | 246 |
pci_conf[0x80] = 0x00; |
247 | 247 |
pci_conf[0x82] = 0x00; |
248 | 248 |
pci_conf[0xa0] = 0x08; |
249 |
pci_conf[0xa0] = 0x08; |
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250 | 249 |
pci_conf[0xa2] = 0x00; |
251 | 250 |
pci_conf[0xa3] = 0x00; |
252 | 251 |
pci_conf[0xa4] = 0x00; |
... | ... | |
284 | 283 |
pci_conf[0x80] = 0x00; |
285 | 284 |
pci_conf[0x82] = 0x00; |
286 | 285 |
pci_conf[0xa0] = 0x08; |
287 |
pci_conf[0xa0] = 0x08; |
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288 | 286 |
pci_conf[0xa2] = 0x00; |
289 | 287 |
pci_conf[0xa3] = 0x00; |
290 | 288 |
pci_conf[0xa4] = 0x00; |
... | ... | |
312 | 310 |
return pci_device_load(d, f); |
313 | 311 |
} |
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int piix_init(PCIBus *bus, int devfn) |
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{ |
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PCIDevice *d; |
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uint8_t *pci_conf; |
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|
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d = pci_register_device(bus, "PIIX", sizeof(PCIDevice), |
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devfn, NULL, NULL); |
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register_savevm("PIIX", 0, 2, piix_save, piix_load, d); |
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piix3_dev = d; |
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pci_conf = d->config; |
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pci_conf[0x00] = 0x86; // Intel |
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pci_conf[0x01] = 0x80; |
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pci_conf[0x02] = 0x2E; // 82371FB PIIX PCI-to-ISA bridge |
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pci_conf[0x03] = 0x12; |
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pci_conf[0x08] = 0x02; // Step A1 |
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pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
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pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
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pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
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piix3_reset(d); |
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return d->devfn; |
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} |
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315 | 338 |
int piix3_init(PCIBus *bus, int devfn) |
316 | 339 |
{ |
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PCIDevice *d; |
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