Revision e6dbd3b3 target-m68k/translate.c
| b/target-m68k/translate.c | ||
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| 42 | 42 |
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/* internal defines */ |
| 44 | 44 |
typedef struct DisasContext {
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CPUM68KState *env; |
|
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target_ulong pc; |
| 46 | 47 |
int is_jmp; |
| 47 | 48 |
int cc_op; |
| ... | ... | |
| 198 | 199 |
} |
| 199 | 200 |
} |
| 200 | 201 |
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/* Read a 32-bit immediate constant. */ |
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static inline uint32_t read_im32(DisasContext *s) |
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{
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uint32_t im; |
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im = ((uint32_t)lduw_code(s->pc)) << 16; |
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s->pc += 2; |
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im |= lduw_code(s->pc); |
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s->pc += 2; |
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return im; |
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} |
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|
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/* Calculate and address index. */ |
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static int gen_addr_index(uint16_t ext, int tmp) |
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{
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int add; |
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int scale; |
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add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12); |
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if ((ext & 0x800) == 0) {
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gen_op_ext16s32(tmp, add); |
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add = tmp; |
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} |
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scale = (ext >> 9) & 3; |
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if (scale != 0) {
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gen_op_shl32(tmp, add, gen_im32(scale)); |
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add = tmp; |
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} |
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return add; |
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} |
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|
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/* Handle a base + index + displacement effective addresss. A base of |
| 202 | 233 |
-1 means pc-relative. */ |
| 203 | 234 |
static int gen_lea_indexed(DisasContext *s, int opsize, int base) |
| 204 | 235 |
{
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int scale; |
|
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uint32_t offset; |
| 207 | 237 |
uint16_t ext; |
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int add; |
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int tmp; |
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uint32_t bd, od; |
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offset = s->pc; |
| 212 | 243 |
ext = lduw_code(s->pc); |
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s->pc += 2; |
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tmp = ((ext >> 12) & 7) + ((ext & 0x8000) ? QREG_A0 : QREG_D0); |
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/* ??? Check W/L bit. */ |
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scale = (ext >> 9) & 3; |
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if (scale == 0) {
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add = tmp; |
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} else {
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add = gen_new_qreg(QMODE_I32); |
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gen_op_shl32(add, tmp, gen_im32(scale)); |
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} |
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tmp = gen_new_qreg(QMODE_I32); |
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if (base != -1) {
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gen_op_add32(tmp, base, gen_im32((int8_t)ext)); |
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gen_op_add32(tmp, tmp, add); |
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|
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if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) |
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return -1; |
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|
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if (ext & 0x100) {
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/* full extension word format */ |
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if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) |
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return -1; |
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if ((ext & 0x30) > 0x10) {
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/* base displacement */ |
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if ((ext & 0x30) == 0x20) {
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bd = (int16_t)lduw_code(s->pc); |
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s->pc += 2; |
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} else {
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bd = read_im32(s); |
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} |
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} else {
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bd = 0; |
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} |
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tmp = gen_new_qreg(QMODE_I32); |
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if ((ext & 0x44) == 0) {
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/* pre-index */ |
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add = gen_addr_index(ext, tmp); |
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} else {
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add = QREG_NULL; |
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} |
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if ((ext & 0x80) == 0) {
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/* base not suppressed */ |
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if (base == -1) {
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base = gen_im32(offset + bd); |
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bd = 0; |
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} |
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if (add) {
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gen_op_add32(tmp, add, base); |
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add = tmp; |
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} else {
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add = base; |
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} |
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} |
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if (add) {
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if (bd != 0) {
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gen_op_add32(tmp, add, gen_im32(bd)); |
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add = tmp; |
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} |
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} else {
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add = gen_im32(bd); |
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} |
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if ((ext & 3) != 0) {
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/* memory indirect */ |
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base = gen_load(s, OS_LONG, add, 0); |
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if ((ext & 0x44) == 4) {
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add = gen_addr_index(ext, tmp); |
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gen_op_add32(tmp, add, base); |
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add = tmp; |
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} else {
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add = base; |
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} |
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if ((ext & 3) > 1) {
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/* outer displacement */ |
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if ((ext & 3) == 2) {
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od = (int16_t)lduw_code(s->pc); |
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s->pc += 2; |
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} else {
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od = read_im32(s); |
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} |
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} else {
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od = 0; |
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} |
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if (od != 0) {
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gen_op_add32(add, tmp, gen_im32(od)); |
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add = tmp; |
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} |
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} |
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} else {
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gen_op_add32(tmp, add, gen_im32(offset + (int8_t)ext)); |
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/* brief extension word format */ |
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tmp = gen_new_qreg(QMODE_I32); |
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add = gen_addr_index(ext, tmp); |
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if (base != -1) {
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gen_op_add32(tmp, add, base); |
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if ((int8_t)ext) |
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gen_op_add32(tmp, tmp, gen_im32((int8_t)ext)); |
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} else {
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gen_op_add32(tmp, add, gen_im32(offset + (int8_t)ext)); |
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} |
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add = tmp; |
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} |
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return tmp; |
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} |
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|
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/* Read a 32-bit immediate constant. */ |
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static inline uint32_t read_im32(DisasContext *s) |
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{
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uint32_t im; |
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im = ((uint32_t)lduw_code(s->pc)) << 16; |
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s->pc += 2; |
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im |= lduw_code(s->pc); |
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s->pc += 2; |
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return im; |
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return add; |
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} |
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|
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/* Update the CPU env CC_OP state. */ |
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static inline void gen_flush_cc_op(DisasContext *s) |
| 247 | 337 |
{
|
| ... | ... | |
| 2721 | 2811 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
| 2722 | 2812 |
gen_opparam_ptr = gen_opparam_buf; |
| 2723 | 2813 |
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dc->env = env; |
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dc->is_jmp = DISAS_NEXT; |
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dc->pc = pc_start; |
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dc->cc_op = CC_OP_DYNAMIC; |
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