root / hw / rtl8139.c @ e6e055c9
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1 | a41b2ff2 | pbrook | /**
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2 | a41b2ff2 | pbrook | * QEMU RTL8139 emulation
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3 | 5fafdf24 | ths | *
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4 | a41b2ff2 | pbrook | * Copyright (c) 2006 Igor Kovalenko
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5 | 5fafdf24 | ths | *
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6 | a41b2ff2 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a41b2ff2 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | a41b2ff2 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | a41b2ff2 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a41b2ff2 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | a41b2ff2 | pbrook | * furnished to do so, subject to the following conditions:
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12 | a41b2ff2 | pbrook | *
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13 | a41b2ff2 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | a41b2ff2 | pbrook | * all copies or substantial portions of the Software.
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15 | a41b2ff2 | pbrook | *
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16 | a41b2ff2 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a41b2ff2 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a41b2ff2 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a41b2ff2 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a41b2ff2 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a41b2ff2 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a41b2ff2 | pbrook | * THE SOFTWARE.
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23 | 5fafdf24 | ths | |
24 | a41b2ff2 | pbrook | * Modifications:
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25 | a41b2ff2 | pbrook | * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
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26 | 5fafdf24 | ths | *
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27 | 6cadb320 | bellard | * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
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28 | 6cadb320 | bellard | * HW revision ID changes for FreeBSD driver
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29 | 5fafdf24 | ths | *
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30 | 6cadb320 | bellard | * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
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31 | 6cadb320 | bellard | * Corrected packet transfer reassembly routine for 8139C+ mode
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32 | 6cadb320 | bellard | * Rearranged debugging print statements
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33 | 6cadb320 | bellard | * Implemented PCI timer interrupt (disabled by default)
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34 | 6cadb320 | bellard | * Implemented Tally Counters, increased VM load/save version
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35 | 6cadb320 | bellard | * Implemented IP/TCP/UDP checksum task offloading
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36 | 718da2b9 | bellard | *
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37 | 718da2b9 | bellard | * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
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38 | 718da2b9 | bellard | * Fixed MTU=1500 for produced ethernet frames
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39 | 718da2b9 | bellard | *
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40 | 718da2b9 | bellard | * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
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41 | 718da2b9 | bellard | * segmentation offloading
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42 | 718da2b9 | bellard | * Removed slirp.h dependency
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43 | 718da2b9 | bellard | * Added rx/tx buffer reset when enabling rx/tx operation
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44 | 05447803 | Frediano Ziglio | *
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45 | 05447803 | Frediano Ziglio | * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
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46 | 05447803 | Frediano Ziglio | * when strictly needed (required for for
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47 | 05447803 | Frediano Ziglio | * Darwin)
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48 | a41b2ff2 | pbrook | */
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49 | a41b2ff2 | pbrook | |
50 | 87ecb68b | pbrook | #include "hw.h" |
51 | 87ecb68b | pbrook | #include "pci.h" |
52 | 87ecb68b | pbrook | #include "qemu-timer.h" |
53 | 87ecb68b | pbrook | #include "net.h" |
54 | 254111ec | Gerd Hoffmann | #include "loader.h" |
55 | a41b2ff2 | pbrook | |
56 | a41b2ff2 | pbrook | /* debug RTL8139 card */
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57 | a41b2ff2 | pbrook | //#define DEBUG_RTL8139 1
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58 | a41b2ff2 | pbrook | |
59 | 6cadb320 | bellard | #define PCI_FREQUENCY 33000000L |
60 | 6cadb320 | bellard | |
61 | a41b2ff2 | pbrook | /* debug RTL8139 card C+ mode only */
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62 | a41b2ff2 | pbrook | //#define DEBUG_RTL8139CP 1
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63 | a41b2ff2 | pbrook | |
64 | ccf1d14a | ths | /* Calculate CRCs properly on Rx packets */
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65 | ccf1d14a | ths | #define RTL8139_CALCULATE_RXCRC 1 |
66 | a41b2ff2 | pbrook | |
67 | a41b2ff2 | pbrook | #if defined(RTL8139_CALCULATE_RXCRC)
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68 | a41b2ff2 | pbrook | /* For crc32 */
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69 | a41b2ff2 | pbrook | #include <zlib.h> |
70 | a41b2ff2 | pbrook | #endif
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71 | a41b2ff2 | pbrook | |
72 | a41b2ff2 | pbrook | #define SET_MASKED(input, mask, curr) \
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73 | a41b2ff2 | pbrook | ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) |
74 | a41b2ff2 | pbrook | |
75 | a41b2ff2 | pbrook | /* arg % size for size which is a power of 2 */
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76 | a41b2ff2 | pbrook | #define MOD2(input, size) \
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77 | a41b2ff2 | pbrook | ( ( input ) & ( size - 1 ) )
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78 | a41b2ff2 | pbrook | |
79 | 6cadb320 | bellard | #if defined (DEBUG_RTL8139)
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80 | 6cadb320 | bellard | # define DEBUG_PRINT(x) do { printf x ; } while (0) |
81 | 6cadb320 | bellard | #else
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82 | 6cadb320 | bellard | # define DEBUG_PRINT(x)
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83 | 6cadb320 | bellard | #endif
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84 | 6cadb320 | bellard | |
85 | a41b2ff2 | pbrook | /* Symbolic offsets to registers. */
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86 | a41b2ff2 | pbrook | enum RTL8139_registers {
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87 | a41b2ff2 | pbrook | MAC0 = 0, /* Ethernet hardware address. */ |
88 | a41b2ff2 | pbrook | MAR0 = 8, /* Multicast filter. */ |
89 | 6cadb320 | bellard | TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ |
90 | 6cadb320 | bellard | /* Dump Tally Conter control register(64bit). C+ mode only */
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91 | 6cadb320 | bellard | TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ |
92 | a41b2ff2 | pbrook | RxBuf = 0x30,
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93 | a41b2ff2 | pbrook | ChipCmd = 0x37,
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94 | a41b2ff2 | pbrook | RxBufPtr = 0x38,
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95 | a41b2ff2 | pbrook | RxBufAddr = 0x3A,
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96 | a41b2ff2 | pbrook | IntrMask = 0x3C,
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97 | a41b2ff2 | pbrook | IntrStatus = 0x3E,
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98 | a41b2ff2 | pbrook | TxConfig = 0x40,
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99 | a41b2ff2 | pbrook | RxConfig = 0x44,
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100 | a41b2ff2 | pbrook | Timer = 0x48, /* A general-purpose counter. */ |
101 | a41b2ff2 | pbrook | RxMissed = 0x4C, /* 24 bits valid, write clears. */ |
102 | a41b2ff2 | pbrook | Cfg9346 = 0x50,
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103 | a41b2ff2 | pbrook | Config0 = 0x51,
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104 | a41b2ff2 | pbrook | Config1 = 0x52,
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105 | a41b2ff2 | pbrook | FlashReg = 0x54,
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106 | a41b2ff2 | pbrook | MediaStatus = 0x58,
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107 | a41b2ff2 | pbrook | Config3 = 0x59,
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108 | a41b2ff2 | pbrook | Config4 = 0x5A, /* absent on RTL-8139A */ |
109 | a41b2ff2 | pbrook | HltClk = 0x5B,
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110 | a41b2ff2 | pbrook | MultiIntr = 0x5C,
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111 | a41b2ff2 | pbrook | PCIRevisionID = 0x5E,
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112 | a41b2ff2 | pbrook | TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ |
113 | a41b2ff2 | pbrook | BasicModeCtrl = 0x62,
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114 | a41b2ff2 | pbrook | BasicModeStatus = 0x64,
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115 | a41b2ff2 | pbrook | NWayAdvert = 0x66,
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116 | a41b2ff2 | pbrook | NWayLPAR = 0x68,
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117 | a41b2ff2 | pbrook | NWayExpansion = 0x6A,
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118 | a41b2ff2 | pbrook | /* Undocumented registers, but required for proper operation. */
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119 | a41b2ff2 | pbrook | FIFOTMS = 0x70, /* FIFO Control and test. */ |
120 | a41b2ff2 | pbrook | CSCR = 0x74, /* Chip Status and Configuration Register. */ |
121 | a41b2ff2 | pbrook | PARA78 = 0x78,
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122 | a41b2ff2 | pbrook | PARA7c = 0x7c, /* Magic transceiver parameter register. */ |
123 | a41b2ff2 | pbrook | Config5 = 0xD8, /* absent on RTL-8139A */ |
124 | a41b2ff2 | pbrook | /* C+ mode */
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125 | a41b2ff2 | pbrook | TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ |
126 | a41b2ff2 | pbrook | RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ |
127 | a41b2ff2 | pbrook | CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ |
128 | a41b2ff2 | pbrook | IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ |
129 | a41b2ff2 | pbrook | RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ |
130 | a41b2ff2 | pbrook | RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ |
131 | a41b2ff2 | pbrook | TxThresh = 0xEC, /* Early Tx threshold */ |
132 | a41b2ff2 | pbrook | }; |
133 | a41b2ff2 | pbrook | |
134 | a41b2ff2 | pbrook | enum ClearBitMasks {
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135 | a41b2ff2 | pbrook | MultiIntrClear = 0xF000,
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136 | a41b2ff2 | pbrook | ChipCmdClear = 0xE2,
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137 | a41b2ff2 | pbrook | Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), |
138 | a41b2ff2 | pbrook | }; |
139 | a41b2ff2 | pbrook | |
140 | a41b2ff2 | pbrook | enum ChipCmdBits {
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141 | a41b2ff2 | pbrook | CmdReset = 0x10,
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142 | a41b2ff2 | pbrook | CmdRxEnb = 0x08,
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143 | a41b2ff2 | pbrook | CmdTxEnb = 0x04,
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144 | a41b2ff2 | pbrook | RxBufEmpty = 0x01,
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145 | a41b2ff2 | pbrook | }; |
146 | a41b2ff2 | pbrook | |
147 | a41b2ff2 | pbrook | /* C+ mode */
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148 | a41b2ff2 | pbrook | enum CplusCmdBits {
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149 | 6cadb320 | bellard | CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ |
150 | 6cadb320 | bellard | CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ |
151 | 6cadb320 | bellard | CPlusRxEnb = 0x0002,
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152 | 6cadb320 | bellard | CPlusTxEnb = 0x0001,
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153 | a41b2ff2 | pbrook | }; |
154 | a41b2ff2 | pbrook | |
155 | a41b2ff2 | pbrook | /* Interrupt register bits, using my own meaningful names. */
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156 | a41b2ff2 | pbrook | enum IntrStatusBits {
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157 | a41b2ff2 | pbrook | PCIErr = 0x8000,
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158 | a41b2ff2 | pbrook | PCSTimeout = 0x4000,
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159 | a41b2ff2 | pbrook | RxFIFOOver = 0x40,
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160 | a41b2ff2 | pbrook | RxUnderrun = 0x20,
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161 | a41b2ff2 | pbrook | RxOverflow = 0x10,
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162 | a41b2ff2 | pbrook | TxErr = 0x08,
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163 | a41b2ff2 | pbrook | TxOK = 0x04,
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164 | a41b2ff2 | pbrook | RxErr = 0x02,
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165 | a41b2ff2 | pbrook | RxOK = 0x01,
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166 | a41b2ff2 | pbrook | |
167 | a41b2ff2 | pbrook | RxAckBits = RxFIFOOver | RxOverflow | RxOK, |
168 | a41b2ff2 | pbrook | }; |
169 | a41b2ff2 | pbrook | |
170 | a41b2ff2 | pbrook | enum TxStatusBits {
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171 | a41b2ff2 | pbrook | TxHostOwns = 0x2000,
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172 | a41b2ff2 | pbrook | TxUnderrun = 0x4000,
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173 | a41b2ff2 | pbrook | TxStatOK = 0x8000,
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174 | a41b2ff2 | pbrook | TxOutOfWindow = 0x20000000,
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175 | a41b2ff2 | pbrook | TxAborted = 0x40000000,
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176 | a41b2ff2 | pbrook | TxCarrierLost = 0x80000000,
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177 | a41b2ff2 | pbrook | }; |
178 | a41b2ff2 | pbrook | enum RxStatusBits {
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179 | a41b2ff2 | pbrook | RxMulticast = 0x8000,
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180 | a41b2ff2 | pbrook | RxPhysical = 0x4000,
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181 | a41b2ff2 | pbrook | RxBroadcast = 0x2000,
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182 | a41b2ff2 | pbrook | RxBadSymbol = 0x0020,
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183 | a41b2ff2 | pbrook | RxRunt = 0x0010,
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184 | a41b2ff2 | pbrook | RxTooLong = 0x0008,
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185 | a41b2ff2 | pbrook | RxCRCErr = 0x0004,
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186 | a41b2ff2 | pbrook | RxBadAlign = 0x0002,
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187 | a41b2ff2 | pbrook | RxStatusOK = 0x0001,
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188 | a41b2ff2 | pbrook | }; |
189 | a41b2ff2 | pbrook | |
190 | a41b2ff2 | pbrook | /* Bits in RxConfig. */
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191 | a41b2ff2 | pbrook | enum rx_mode_bits {
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192 | a41b2ff2 | pbrook | AcceptErr = 0x20,
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193 | a41b2ff2 | pbrook | AcceptRunt = 0x10,
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194 | a41b2ff2 | pbrook | AcceptBroadcast = 0x08,
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195 | a41b2ff2 | pbrook | AcceptMulticast = 0x04,
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196 | a41b2ff2 | pbrook | AcceptMyPhys = 0x02,
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197 | a41b2ff2 | pbrook | AcceptAllPhys = 0x01,
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198 | a41b2ff2 | pbrook | }; |
199 | a41b2ff2 | pbrook | |
200 | a41b2ff2 | pbrook | /* Bits in TxConfig. */
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201 | a41b2ff2 | pbrook | enum tx_config_bits {
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202 | a41b2ff2 | pbrook | |
203 | a41b2ff2 | pbrook | /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
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204 | a41b2ff2 | pbrook | TxIFGShift = 24,
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205 | a41b2ff2 | pbrook | TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ |
206 | a41b2ff2 | pbrook | TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ |
207 | a41b2ff2 | pbrook | TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ |
208 | a41b2ff2 | pbrook | TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ |
209 | a41b2ff2 | pbrook | |
210 | a41b2ff2 | pbrook | TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ |
211 | a41b2ff2 | pbrook | TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ |
212 | a41b2ff2 | pbrook | TxClearAbt = (1 << 0), /* Clear abort (WO) */ |
213 | a41b2ff2 | pbrook | TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ |
214 | a41b2ff2 | pbrook | TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ |
215 | a41b2ff2 | pbrook | |
216 | a41b2ff2 | pbrook | TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ |
217 | a41b2ff2 | pbrook | }; |
218 | a41b2ff2 | pbrook | |
219 | a41b2ff2 | pbrook | |
220 | a41b2ff2 | pbrook | /* Transmit Status of All Descriptors (TSAD) Register */
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221 | a41b2ff2 | pbrook | enum TSAD_bits {
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222 | a41b2ff2 | pbrook | TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 |
223 | a41b2ff2 | pbrook | TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 |
224 | a41b2ff2 | pbrook | TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 |
225 | a41b2ff2 | pbrook | TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 |
226 | a41b2ff2 | pbrook | TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 |
227 | a41b2ff2 | pbrook | TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 |
228 | a41b2ff2 | pbrook | TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 |
229 | a41b2ff2 | pbrook | TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 |
230 | a41b2ff2 | pbrook | TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 |
231 | a41b2ff2 | pbrook | TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 |
232 | a41b2ff2 | pbrook | TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 |
233 | a41b2ff2 | pbrook | TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 |
234 | a41b2ff2 | pbrook | TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 |
235 | a41b2ff2 | pbrook | TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 |
236 | a41b2ff2 | pbrook | TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 |
237 | a41b2ff2 | pbrook | TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 |
238 | a41b2ff2 | pbrook | }; |
239 | a41b2ff2 | pbrook | |
240 | a41b2ff2 | pbrook | |
241 | a41b2ff2 | pbrook | /* Bits in Config1 */
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242 | a41b2ff2 | pbrook | enum Config1Bits {
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243 | a41b2ff2 | pbrook | Cfg1_PM_Enable = 0x01,
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244 | a41b2ff2 | pbrook | Cfg1_VPD_Enable = 0x02,
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245 | a41b2ff2 | pbrook | Cfg1_PIO = 0x04,
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246 | a41b2ff2 | pbrook | Cfg1_MMIO = 0x08,
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247 | a41b2ff2 | pbrook | LWAKE = 0x10, /* not on 8139, 8139A */ |
248 | a41b2ff2 | pbrook | Cfg1_Driver_Load = 0x20,
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249 | a41b2ff2 | pbrook | Cfg1_LED0 = 0x40,
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250 | a41b2ff2 | pbrook | Cfg1_LED1 = 0x80,
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251 | a41b2ff2 | pbrook | SLEEP = (1 << 1), /* only on 8139, 8139A */ |
252 | a41b2ff2 | pbrook | PWRDN = (1 << 0), /* only on 8139, 8139A */ |
253 | a41b2ff2 | pbrook | }; |
254 | a41b2ff2 | pbrook | |
255 | a41b2ff2 | pbrook | /* Bits in Config3 */
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256 | a41b2ff2 | pbrook | enum Config3Bits {
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257 | a41b2ff2 | pbrook | Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ |
258 | a41b2ff2 | pbrook | Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ |
259 | a41b2ff2 | pbrook | Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ |
260 | a41b2ff2 | pbrook | Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ |
261 | a41b2ff2 | pbrook | Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ |
262 | a41b2ff2 | pbrook | Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ |
263 | a41b2ff2 | pbrook | Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ |
264 | a41b2ff2 | pbrook | Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ |
265 | a41b2ff2 | pbrook | }; |
266 | a41b2ff2 | pbrook | |
267 | a41b2ff2 | pbrook | /* Bits in Config4 */
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268 | a41b2ff2 | pbrook | enum Config4Bits {
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269 | a41b2ff2 | pbrook | LWPTN = (1 << 2), /* not on 8139, 8139A */ |
270 | a41b2ff2 | pbrook | }; |
271 | a41b2ff2 | pbrook | |
272 | a41b2ff2 | pbrook | /* Bits in Config5 */
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273 | a41b2ff2 | pbrook | enum Config5Bits {
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274 | a41b2ff2 | pbrook | Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ |
275 | a41b2ff2 | pbrook | Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ |
276 | a41b2ff2 | pbrook | Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ |
277 | a41b2ff2 | pbrook | Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ |
278 | a41b2ff2 | pbrook | Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ |
279 | a41b2ff2 | pbrook | Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ |
280 | a41b2ff2 | pbrook | Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ |
281 | a41b2ff2 | pbrook | }; |
282 | a41b2ff2 | pbrook | |
283 | a41b2ff2 | pbrook | enum RxConfigBits {
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284 | a41b2ff2 | pbrook | /* rx fifo threshold */
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285 | a41b2ff2 | pbrook | RxCfgFIFOShift = 13,
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286 | a41b2ff2 | pbrook | RxCfgFIFONone = (7 << RxCfgFIFOShift),
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287 | a41b2ff2 | pbrook | |
288 | a41b2ff2 | pbrook | /* Max DMA burst */
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289 | a41b2ff2 | pbrook | RxCfgDMAShift = 8,
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290 | a41b2ff2 | pbrook | RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
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291 | a41b2ff2 | pbrook | |
292 | a41b2ff2 | pbrook | /* rx ring buffer length */
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293 | a41b2ff2 | pbrook | RxCfgRcv8K = 0,
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294 | a41b2ff2 | pbrook | RxCfgRcv16K = (1 << 11), |
295 | a41b2ff2 | pbrook | RxCfgRcv32K = (1 << 12), |
296 | a41b2ff2 | pbrook | RxCfgRcv64K = (1 << 11) | (1 << 12), |
297 | a41b2ff2 | pbrook | |
298 | a41b2ff2 | pbrook | /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
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299 | a41b2ff2 | pbrook | RxNoWrap = (1 << 7), |
300 | a41b2ff2 | pbrook | }; |
301 | a41b2ff2 | pbrook | |
302 | a41b2ff2 | pbrook | /* Twister tuning parameters from RealTek.
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303 | a41b2ff2 | pbrook | Completely undocumented, but required to tune bad links on some boards. */
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304 | a41b2ff2 | pbrook | /*
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305 | a41b2ff2 | pbrook | enum CSCRBits {
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306 | a41b2ff2 | pbrook | CSCR_LinkOKBit = 0x0400,
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307 | a41b2ff2 | pbrook | CSCR_LinkChangeBit = 0x0800,
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308 | a41b2ff2 | pbrook | CSCR_LinkStatusBits = 0x0f000,
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309 | a41b2ff2 | pbrook | CSCR_LinkDownOffCmd = 0x003c0,
|
310 | a41b2ff2 | pbrook | CSCR_LinkDownCmd = 0x0f3c0,
|
311 | a41b2ff2 | pbrook | */
|
312 | a41b2ff2 | pbrook | enum CSCRBits {
|
313 | 5fafdf24 | ths | CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ |
314 | a41b2ff2 | pbrook | CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ |
315 | a41b2ff2 | pbrook | CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ |
316 | a41b2ff2 | pbrook | CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ |
317 | 5fafdf24 | ths | CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ |
318 | a41b2ff2 | pbrook | CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ |
319 | a41b2ff2 | pbrook | CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ |
320 | a41b2ff2 | pbrook | CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ |
321 | a41b2ff2 | pbrook | CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ |
322 | a41b2ff2 | pbrook | }; |
323 | a41b2ff2 | pbrook | |
324 | a41b2ff2 | pbrook | enum Cfg9346Bits {
|
325 | a41b2ff2 | pbrook | Cfg9346_Lock = 0x00,
|
326 | a41b2ff2 | pbrook | Cfg9346_Unlock = 0xC0,
|
327 | a41b2ff2 | pbrook | }; |
328 | a41b2ff2 | pbrook | |
329 | a41b2ff2 | pbrook | typedef enum { |
330 | a41b2ff2 | pbrook | CH_8139 = 0,
|
331 | a41b2ff2 | pbrook | CH_8139_K, |
332 | a41b2ff2 | pbrook | CH_8139A, |
333 | a41b2ff2 | pbrook | CH_8139A_G, |
334 | a41b2ff2 | pbrook | CH_8139B, |
335 | a41b2ff2 | pbrook | CH_8130, |
336 | a41b2ff2 | pbrook | CH_8139C, |
337 | a41b2ff2 | pbrook | CH_8100, |
338 | a41b2ff2 | pbrook | CH_8100B_8139D, |
339 | a41b2ff2 | pbrook | CH_8101, |
340 | c227f099 | Anthony Liguori | } chip_t; |
341 | a41b2ff2 | pbrook | |
342 | a41b2ff2 | pbrook | enum chip_flags {
|
343 | a41b2ff2 | pbrook | HasHltClk = (1 << 0), |
344 | a41b2ff2 | pbrook | HasLWake = (1 << 1), |
345 | a41b2ff2 | pbrook | }; |
346 | a41b2ff2 | pbrook | |
347 | a41b2ff2 | pbrook | #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
|
348 | a41b2ff2 | pbrook | (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) |
349 | a41b2ff2 | pbrook | #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) |
350 | a41b2ff2 | pbrook | |
351 | 6cadb320 | bellard | #define RTL8139_PCI_REVID_8139 0x10 |
352 | 6cadb320 | bellard | #define RTL8139_PCI_REVID_8139CPLUS 0x20 |
353 | 6cadb320 | bellard | |
354 | 6cadb320 | bellard | #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
|
355 | 6cadb320 | bellard | |
356 | a41b2ff2 | pbrook | /* Size is 64 * 16bit words */
|
357 | a41b2ff2 | pbrook | #define EEPROM_9346_ADDR_BITS 6 |
358 | a41b2ff2 | pbrook | #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) |
359 | a41b2ff2 | pbrook | #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) |
360 | a41b2ff2 | pbrook | |
361 | a41b2ff2 | pbrook | enum Chip9346Operation
|
362 | a41b2ff2 | pbrook | { |
363 | a41b2ff2 | pbrook | Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ |
364 | a41b2ff2 | pbrook | Chip9346_op_read = 0x80, /* 10 AAAAAA */ |
365 | a41b2ff2 | pbrook | Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ |
366 | a41b2ff2 | pbrook | Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ |
367 | a41b2ff2 | pbrook | Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ |
368 | a41b2ff2 | pbrook | Chip9346_op_write_all = 0x10, /* 00 01zzzz */ |
369 | a41b2ff2 | pbrook | Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ |
370 | a41b2ff2 | pbrook | }; |
371 | a41b2ff2 | pbrook | |
372 | a41b2ff2 | pbrook | enum Chip9346Mode
|
373 | a41b2ff2 | pbrook | { |
374 | a41b2ff2 | pbrook | Chip9346_none = 0,
|
375 | a41b2ff2 | pbrook | Chip9346_enter_command_mode, |
376 | a41b2ff2 | pbrook | Chip9346_read_command, |
377 | a41b2ff2 | pbrook | Chip9346_data_read, /* from output register */
|
378 | a41b2ff2 | pbrook | Chip9346_data_write, /* to input register, then to contents at specified address */
|
379 | a41b2ff2 | pbrook | Chip9346_data_write_all, /* to input register, then filling contents */
|
380 | a41b2ff2 | pbrook | }; |
381 | a41b2ff2 | pbrook | |
382 | a41b2ff2 | pbrook | typedef struct EEprom9346 |
383 | a41b2ff2 | pbrook | { |
384 | a41b2ff2 | pbrook | uint16_t contents[EEPROM_9346_SIZE]; |
385 | a41b2ff2 | pbrook | int mode;
|
386 | a41b2ff2 | pbrook | uint32_t tick; |
387 | a41b2ff2 | pbrook | uint8_t address; |
388 | a41b2ff2 | pbrook | uint16_t input; |
389 | a41b2ff2 | pbrook | uint16_t output; |
390 | a41b2ff2 | pbrook | |
391 | a41b2ff2 | pbrook | uint8_t eecs; |
392 | a41b2ff2 | pbrook | uint8_t eesk; |
393 | a41b2ff2 | pbrook | uint8_t eedi; |
394 | a41b2ff2 | pbrook | uint8_t eedo; |
395 | a41b2ff2 | pbrook | } EEprom9346; |
396 | a41b2ff2 | pbrook | |
397 | 6cadb320 | bellard | typedef struct RTL8139TallyCounters |
398 | 6cadb320 | bellard | { |
399 | 6cadb320 | bellard | /* Tally counters */
|
400 | 6cadb320 | bellard | uint64_t TxOk; |
401 | 6cadb320 | bellard | uint64_t RxOk; |
402 | 6cadb320 | bellard | uint64_t TxERR; |
403 | 6cadb320 | bellard | uint32_t RxERR; |
404 | 6cadb320 | bellard | uint16_t MissPkt; |
405 | 6cadb320 | bellard | uint16_t FAE; |
406 | 6cadb320 | bellard | uint32_t Tx1Col; |
407 | 6cadb320 | bellard | uint32_t TxMCol; |
408 | 6cadb320 | bellard | uint64_t RxOkPhy; |
409 | 6cadb320 | bellard | uint64_t RxOkBrd; |
410 | 6cadb320 | bellard | uint32_t RxOkMul; |
411 | 6cadb320 | bellard | uint16_t TxAbt; |
412 | 6cadb320 | bellard | uint16_t TxUndrn; |
413 | 6cadb320 | bellard | } RTL8139TallyCounters; |
414 | 6cadb320 | bellard | |
415 | 6cadb320 | bellard | /* Clears all tally counters */
|
416 | 6cadb320 | bellard | static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); |
417 | 6cadb320 | bellard | |
418 | 6cadb320 | bellard | /* Writes tally counters to specified physical memory address */
|
419 | c227f099 | Anthony Liguori | static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters); |
420 | 6cadb320 | bellard | |
421 | a41b2ff2 | pbrook | typedef struct RTL8139State { |
422 | efd6dd45 | Juan Quintela | PCIDevice dev; |
423 | a41b2ff2 | pbrook | uint8_t phys[8]; /* mac address */ |
424 | a41b2ff2 | pbrook | uint8_t mult[8]; /* multicast mask array */ |
425 | a41b2ff2 | pbrook | |
426 | 6cadb320 | bellard | uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ |
427 | a41b2ff2 | pbrook | uint32_t TxAddr[4]; /* TxAddr0 */ |
428 | a41b2ff2 | pbrook | uint32_t RxBuf; /* Receive buffer */
|
429 | a41b2ff2 | pbrook | uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
|
430 | a41b2ff2 | pbrook | uint32_t RxBufPtr; |
431 | a41b2ff2 | pbrook | uint32_t RxBufAddr; |
432 | a41b2ff2 | pbrook | |
433 | a41b2ff2 | pbrook | uint16_t IntrStatus; |
434 | a41b2ff2 | pbrook | uint16_t IntrMask; |
435 | a41b2ff2 | pbrook | |
436 | a41b2ff2 | pbrook | uint32_t TxConfig; |
437 | a41b2ff2 | pbrook | uint32_t RxConfig; |
438 | a41b2ff2 | pbrook | uint32_t RxMissed; |
439 | a41b2ff2 | pbrook | |
440 | a41b2ff2 | pbrook | uint16_t CSCR; |
441 | a41b2ff2 | pbrook | |
442 | a41b2ff2 | pbrook | uint8_t Cfg9346; |
443 | a41b2ff2 | pbrook | uint8_t Config0; |
444 | a41b2ff2 | pbrook | uint8_t Config1; |
445 | a41b2ff2 | pbrook | uint8_t Config3; |
446 | a41b2ff2 | pbrook | uint8_t Config4; |
447 | a41b2ff2 | pbrook | uint8_t Config5; |
448 | a41b2ff2 | pbrook | |
449 | a41b2ff2 | pbrook | uint8_t clock_enabled; |
450 | a41b2ff2 | pbrook | uint8_t bChipCmdState; |
451 | a41b2ff2 | pbrook | |
452 | a41b2ff2 | pbrook | uint16_t MultiIntr; |
453 | a41b2ff2 | pbrook | |
454 | a41b2ff2 | pbrook | uint16_t BasicModeCtrl; |
455 | a41b2ff2 | pbrook | uint16_t BasicModeStatus; |
456 | a41b2ff2 | pbrook | uint16_t NWayAdvert; |
457 | a41b2ff2 | pbrook | uint16_t NWayLPAR; |
458 | a41b2ff2 | pbrook | uint16_t NWayExpansion; |
459 | a41b2ff2 | pbrook | |
460 | a41b2ff2 | pbrook | uint16_t CpCmd; |
461 | a41b2ff2 | pbrook | uint8_t TxThresh; |
462 | a41b2ff2 | pbrook | |
463 | 1673ad51 | Mark McLoughlin | NICState *nic; |
464 | 254111ec | Gerd Hoffmann | NICConf conf; |
465 | a41b2ff2 | pbrook | int rtl8139_mmio_io_addr;
|
466 | a41b2ff2 | pbrook | |
467 | a41b2ff2 | pbrook | /* C ring mode */
|
468 | a41b2ff2 | pbrook | uint32_t currTxDesc; |
469 | a41b2ff2 | pbrook | |
470 | a41b2ff2 | pbrook | /* C+ mode */
|
471 | 2c3891ab | aliguori | uint32_t cplus_enabled; |
472 | 2c3891ab | aliguori | |
473 | a41b2ff2 | pbrook | uint32_t currCPlusRxDesc; |
474 | a41b2ff2 | pbrook | uint32_t currCPlusTxDesc; |
475 | a41b2ff2 | pbrook | |
476 | a41b2ff2 | pbrook | uint32_t RxRingAddrLO; |
477 | a41b2ff2 | pbrook | uint32_t RxRingAddrHI; |
478 | a41b2ff2 | pbrook | |
479 | a41b2ff2 | pbrook | EEprom9346 eeprom; |
480 | 6cadb320 | bellard | |
481 | 6cadb320 | bellard | uint32_t TCTR; |
482 | 6cadb320 | bellard | uint32_t TimerInt; |
483 | 6cadb320 | bellard | int64_t TCTR_base; |
484 | 6cadb320 | bellard | |
485 | 6cadb320 | bellard | /* Tally counters */
|
486 | 6cadb320 | bellard | RTL8139TallyCounters tally_counters; |
487 | 6cadb320 | bellard | |
488 | 6cadb320 | bellard | /* Non-persistent data */
|
489 | 6cadb320 | bellard | uint8_t *cplus_txbuffer; |
490 | 6cadb320 | bellard | int cplus_txbuffer_len;
|
491 | 6cadb320 | bellard | int cplus_txbuffer_offset;
|
492 | 6cadb320 | bellard | |
493 | 6cadb320 | bellard | /* PCI interrupt timer */
|
494 | 6cadb320 | bellard | QEMUTimer *timer; |
495 | 05447803 | Frediano Ziglio | int64_t TimerExpire; |
496 | 6cadb320 | bellard | |
497 | a41b2ff2 | pbrook | } RTL8139State; |
498 | a41b2ff2 | pbrook | |
499 | 05447803 | Frediano Ziglio | static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time); |
500 | 05447803 | Frediano Ziglio | |
501 | 9596ebb7 | pbrook | static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) |
502 | a41b2ff2 | pbrook | { |
503 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
|
504 | a41b2ff2 | pbrook | |
505 | a41b2ff2 | pbrook | switch (command & Chip9346_op_mask)
|
506 | a41b2ff2 | pbrook | { |
507 | a41b2ff2 | pbrook | case Chip9346_op_read:
|
508 | a41b2ff2 | pbrook | { |
509 | a41b2ff2 | pbrook | eeprom->address = command & EEPROM_9346_ADDR_MASK; |
510 | a41b2ff2 | pbrook | eeprom->output = eeprom->contents[eeprom->address]; |
511 | a41b2ff2 | pbrook | eeprom->eedo = 0;
|
512 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
513 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_data_read; |
514 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
|
515 | 6cadb320 | bellard | eeprom->address, eeprom->output)); |
516 | a41b2ff2 | pbrook | } |
517 | a41b2ff2 | pbrook | break;
|
518 | a41b2ff2 | pbrook | |
519 | a41b2ff2 | pbrook | case Chip9346_op_write:
|
520 | a41b2ff2 | pbrook | { |
521 | a41b2ff2 | pbrook | eeprom->address = command & EEPROM_9346_ADDR_MASK; |
522 | a41b2ff2 | pbrook | eeprom->input = 0;
|
523 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
524 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; /* Chip9346_data_write */
|
525 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
|
526 | 6cadb320 | bellard | eeprom->address)); |
527 | a41b2ff2 | pbrook | } |
528 | a41b2ff2 | pbrook | break;
|
529 | a41b2ff2 | pbrook | default:
|
530 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; |
531 | a41b2ff2 | pbrook | switch (command & Chip9346_op_ext_mask)
|
532 | a41b2ff2 | pbrook | { |
533 | a41b2ff2 | pbrook | case Chip9346_op_write_enable:
|
534 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
|
535 | a41b2ff2 | pbrook | break;
|
536 | a41b2ff2 | pbrook | case Chip9346_op_write_all:
|
537 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
|
538 | a41b2ff2 | pbrook | break;
|
539 | a41b2ff2 | pbrook | case Chip9346_op_write_disable:
|
540 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
|
541 | a41b2ff2 | pbrook | break;
|
542 | a41b2ff2 | pbrook | } |
543 | a41b2ff2 | pbrook | break;
|
544 | a41b2ff2 | pbrook | } |
545 | a41b2ff2 | pbrook | } |
546 | a41b2ff2 | pbrook | |
547 | 9596ebb7 | pbrook | static void prom9346_shift_clock(EEprom9346 *eeprom) |
548 | a41b2ff2 | pbrook | { |
549 | a41b2ff2 | pbrook | int bit = eeprom->eedi?1:0; |
550 | a41b2ff2 | pbrook | |
551 | a41b2ff2 | pbrook | ++ eeprom->tick; |
552 | a41b2ff2 | pbrook | |
553 | 6cadb320 | bellard | DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
|
554 | a41b2ff2 | pbrook | |
555 | a41b2ff2 | pbrook | switch (eeprom->mode)
|
556 | a41b2ff2 | pbrook | { |
557 | a41b2ff2 | pbrook | case Chip9346_enter_command_mode:
|
558 | a41b2ff2 | pbrook | if (bit)
|
559 | a41b2ff2 | pbrook | { |
560 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_read_command; |
561 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
562 | a41b2ff2 | pbrook | eeprom->input = 0;
|
563 | 6cadb320 | bellard | DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
|
564 | a41b2ff2 | pbrook | } |
565 | a41b2ff2 | pbrook | break;
|
566 | a41b2ff2 | pbrook | |
567 | a41b2ff2 | pbrook | case Chip9346_read_command:
|
568 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
569 | a41b2ff2 | pbrook | if (eeprom->tick == 8) |
570 | a41b2ff2 | pbrook | { |
571 | a41b2ff2 | pbrook | prom9346_decode_command(eeprom, eeprom->input & 0xff);
|
572 | a41b2ff2 | pbrook | } |
573 | a41b2ff2 | pbrook | break;
|
574 | a41b2ff2 | pbrook | |
575 | a41b2ff2 | pbrook | case Chip9346_data_read:
|
576 | a41b2ff2 | pbrook | eeprom->eedo = (eeprom->output & 0x8000)?1:0; |
577 | a41b2ff2 | pbrook | eeprom->output <<= 1;
|
578 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
579 | a41b2ff2 | pbrook | { |
580 | 6cadb320 | bellard | #if 1 |
581 | 6cadb320 | bellard | // the FreeBSD drivers (rl and re) don't explicitly toggle
|
582 | 6cadb320 | bellard | // CS between reads (or does setting Cfg9346 to 0 count too?),
|
583 | 6cadb320 | bellard | // so we need to enter wait-for-command state here
|
584 | 6cadb320 | bellard | eeprom->mode = Chip9346_enter_command_mode; |
585 | 6cadb320 | bellard | eeprom->input = 0;
|
586 | 6cadb320 | bellard | eeprom->tick = 0;
|
587 | 6cadb320 | bellard | |
588 | 6cadb320 | bellard | DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
|
589 | 6cadb320 | bellard | #else
|
590 | 6cadb320 | bellard | // original behaviour
|
591 | a41b2ff2 | pbrook | ++eeprom->address; |
592 | a41b2ff2 | pbrook | eeprom->address &= EEPROM_9346_ADDR_MASK; |
593 | a41b2ff2 | pbrook | eeprom->output = eeprom->contents[eeprom->address]; |
594 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
595 | a41b2ff2 | pbrook | |
596 | 6cadb320 | bellard | DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
|
597 | 6cadb320 | bellard | eeprom->address, eeprom->output)); |
598 | a41b2ff2 | pbrook | #endif
|
599 | a41b2ff2 | pbrook | } |
600 | a41b2ff2 | pbrook | break;
|
601 | a41b2ff2 | pbrook | |
602 | a41b2ff2 | pbrook | case Chip9346_data_write:
|
603 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
604 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
605 | a41b2ff2 | pbrook | { |
606 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
|
607 | 6cadb320 | bellard | eeprom->address, eeprom->input)); |
608 | 6cadb320 | bellard | |
609 | a41b2ff2 | pbrook | eeprom->contents[eeprom->address] = eeprom->input; |
610 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
|
611 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
612 | a41b2ff2 | pbrook | eeprom->input = 0;
|
613 | a41b2ff2 | pbrook | } |
614 | a41b2ff2 | pbrook | break;
|
615 | a41b2ff2 | pbrook | |
616 | a41b2ff2 | pbrook | case Chip9346_data_write_all:
|
617 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
618 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
619 | a41b2ff2 | pbrook | { |
620 | a41b2ff2 | pbrook | int i;
|
621 | a41b2ff2 | pbrook | for (i = 0; i < EEPROM_9346_SIZE; i++) |
622 | a41b2ff2 | pbrook | { |
623 | a41b2ff2 | pbrook | eeprom->contents[i] = eeprom->input; |
624 | a41b2ff2 | pbrook | } |
625 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
|
626 | 6cadb320 | bellard | eeprom->input)); |
627 | 6cadb320 | bellard | |
628 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_enter_command_mode; |
629 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
630 | a41b2ff2 | pbrook | eeprom->input = 0;
|
631 | a41b2ff2 | pbrook | } |
632 | a41b2ff2 | pbrook | break;
|
633 | a41b2ff2 | pbrook | |
634 | a41b2ff2 | pbrook | default:
|
635 | a41b2ff2 | pbrook | break;
|
636 | a41b2ff2 | pbrook | } |
637 | a41b2ff2 | pbrook | } |
638 | a41b2ff2 | pbrook | |
639 | 9596ebb7 | pbrook | static int prom9346_get_wire(RTL8139State *s) |
640 | a41b2ff2 | pbrook | { |
641 | a41b2ff2 | pbrook | EEprom9346 *eeprom = &s->eeprom; |
642 | a41b2ff2 | pbrook | if (!eeprom->eecs)
|
643 | a41b2ff2 | pbrook | return 0; |
644 | a41b2ff2 | pbrook | |
645 | a41b2ff2 | pbrook | return eeprom->eedo;
|
646 | a41b2ff2 | pbrook | } |
647 | a41b2ff2 | pbrook | |
648 | 9596ebb7 | pbrook | /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
|
649 | 9596ebb7 | pbrook | static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) |
650 | a41b2ff2 | pbrook | { |
651 | a41b2ff2 | pbrook | EEprom9346 *eeprom = &s->eeprom; |
652 | a41b2ff2 | pbrook | uint8_t old_eecs = eeprom->eecs; |
653 | a41b2ff2 | pbrook | uint8_t old_eesk = eeprom->eesk; |
654 | a41b2ff2 | pbrook | |
655 | a41b2ff2 | pbrook | eeprom->eecs = eecs; |
656 | a41b2ff2 | pbrook | eeprom->eesk = eesk; |
657 | a41b2ff2 | pbrook | eeprom->eedi = eedi; |
658 | a41b2ff2 | pbrook | |
659 | 6cadb320 | bellard | DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
|
660 | 6cadb320 | bellard | eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo)); |
661 | a41b2ff2 | pbrook | |
662 | a41b2ff2 | pbrook | if (!old_eecs && eecs)
|
663 | a41b2ff2 | pbrook | { |
664 | a41b2ff2 | pbrook | /* Synchronize start */
|
665 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
666 | a41b2ff2 | pbrook | eeprom->input = 0;
|
667 | a41b2ff2 | pbrook | eeprom->output = 0;
|
668 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_enter_command_mode; |
669 | a41b2ff2 | pbrook | |
670 | 6cadb320 | bellard | DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
|
671 | a41b2ff2 | pbrook | } |
672 | a41b2ff2 | pbrook | |
673 | a41b2ff2 | pbrook | if (!eecs)
|
674 | a41b2ff2 | pbrook | { |
675 | 6cadb320 | bellard | DEBUG_PRINT(("=== eeprom: end access\n"));
|
676 | a41b2ff2 | pbrook | return;
|
677 | a41b2ff2 | pbrook | } |
678 | a41b2ff2 | pbrook | |
679 | a41b2ff2 | pbrook | if (!old_eesk && eesk)
|
680 | a41b2ff2 | pbrook | { |
681 | a41b2ff2 | pbrook | /* SK front rules */
|
682 | a41b2ff2 | pbrook | prom9346_shift_clock(eeprom); |
683 | a41b2ff2 | pbrook | } |
684 | a41b2ff2 | pbrook | } |
685 | a41b2ff2 | pbrook | |
686 | a41b2ff2 | pbrook | static void rtl8139_update_irq(RTL8139State *s) |
687 | a41b2ff2 | pbrook | { |
688 | a41b2ff2 | pbrook | int isr;
|
689 | a41b2ff2 | pbrook | isr = (s->IntrStatus & s->IntrMask) & 0xffff;
|
690 | 6cadb320 | bellard | |
691 | 80a34d67 | pbrook | DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
|
692 | 80a34d67 | pbrook | isr ? 1 : 0, s->IntrStatus, s->IntrMask)); |
693 | 6cadb320 | bellard | |
694 | efd6dd45 | Juan Quintela | qemu_set_irq(s->dev.irq[0], (isr != 0)); |
695 | a41b2ff2 | pbrook | } |
696 | a41b2ff2 | pbrook | |
697 | a41b2ff2 | pbrook | #define POLYNOMIAL 0x04c11db6 |
698 | a41b2ff2 | pbrook | |
699 | a41b2ff2 | pbrook | /* From FreeBSD */
|
700 | a41b2ff2 | pbrook | /* XXX: optimize */
|
701 | a41b2ff2 | pbrook | static int compute_mcast_idx(const uint8_t *ep) |
702 | a41b2ff2 | pbrook | { |
703 | a41b2ff2 | pbrook | uint32_t crc; |
704 | a41b2ff2 | pbrook | int carry, i, j;
|
705 | a41b2ff2 | pbrook | uint8_t b; |
706 | a41b2ff2 | pbrook | |
707 | a41b2ff2 | pbrook | crc = 0xffffffff;
|
708 | a41b2ff2 | pbrook | for (i = 0; i < 6; i++) { |
709 | a41b2ff2 | pbrook | b = *ep++; |
710 | a41b2ff2 | pbrook | for (j = 0; j < 8; j++) { |
711 | a41b2ff2 | pbrook | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
712 | a41b2ff2 | pbrook | crc <<= 1;
|
713 | a41b2ff2 | pbrook | b >>= 1;
|
714 | a41b2ff2 | pbrook | if (carry)
|
715 | a41b2ff2 | pbrook | crc = ((crc ^ POLYNOMIAL) | carry); |
716 | a41b2ff2 | pbrook | } |
717 | a41b2ff2 | pbrook | } |
718 | a41b2ff2 | pbrook | return (crc >> 26); |
719 | a41b2ff2 | pbrook | } |
720 | a41b2ff2 | pbrook | |
721 | a41b2ff2 | pbrook | static int rtl8139_RxWrap(RTL8139State *s) |
722 | a41b2ff2 | pbrook | { |
723 | a41b2ff2 | pbrook | /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
|
724 | a41b2ff2 | pbrook | return (s->RxConfig & (1 << 7)); |
725 | a41b2ff2 | pbrook | } |
726 | a41b2ff2 | pbrook | |
727 | a41b2ff2 | pbrook | static int rtl8139_receiver_enabled(RTL8139State *s) |
728 | a41b2ff2 | pbrook | { |
729 | a41b2ff2 | pbrook | return s->bChipCmdState & CmdRxEnb;
|
730 | a41b2ff2 | pbrook | } |
731 | a41b2ff2 | pbrook | |
732 | a41b2ff2 | pbrook | static int rtl8139_transmitter_enabled(RTL8139State *s) |
733 | a41b2ff2 | pbrook | { |
734 | a41b2ff2 | pbrook | return s->bChipCmdState & CmdTxEnb;
|
735 | a41b2ff2 | pbrook | } |
736 | a41b2ff2 | pbrook | |
737 | a41b2ff2 | pbrook | static int rtl8139_cp_receiver_enabled(RTL8139State *s) |
738 | a41b2ff2 | pbrook | { |
739 | a41b2ff2 | pbrook | return s->CpCmd & CPlusRxEnb;
|
740 | a41b2ff2 | pbrook | } |
741 | a41b2ff2 | pbrook | |
742 | a41b2ff2 | pbrook | static int rtl8139_cp_transmitter_enabled(RTL8139State *s) |
743 | a41b2ff2 | pbrook | { |
744 | a41b2ff2 | pbrook | return s->CpCmd & CPlusTxEnb;
|
745 | a41b2ff2 | pbrook | } |
746 | a41b2ff2 | pbrook | |
747 | a41b2ff2 | pbrook | static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) |
748 | a41b2ff2 | pbrook | { |
749 | a41b2ff2 | pbrook | if (s->RxBufAddr + size > s->RxBufferSize)
|
750 | a41b2ff2 | pbrook | { |
751 | a41b2ff2 | pbrook | int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
|
752 | a41b2ff2 | pbrook | |
753 | a41b2ff2 | pbrook | /* write packet data */
|
754 | ccf1d14a | ths | if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) |
755 | a41b2ff2 | pbrook | { |
756 | 6cadb320 | bellard | DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
|
757 | a41b2ff2 | pbrook | |
758 | a41b2ff2 | pbrook | if (size > wrapped)
|
759 | a41b2ff2 | pbrook | { |
760 | a41b2ff2 | pbrook | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, |
761 | a41b2ff2 | pbrook | buf, size-wrapped ); |
762 | a41b2ff2 | pbrook | } |
763 | a41b2ff2 | pbrook | |
764 | a41b2ff2 | pbrook | /* reset buffer pointer */
|
765 | a41b2ff2 | pbrook | s->RxBufAddr = 0;
|
766 | a41b2ff2 | pbrook | |
767 | a41b2ff2 | pbrook | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, |
768 | a41b2ff2 | pbrook | buf + (size-wrapped), wrapped ); |
769 | a41b2ff2 | pbrook | |
770 | a41b2ff2 | pbrook | s->RxBufAddr = wrapped; |
771 | a41b2ff2 | pbrook | |
772 | a41b2ff2 | pbrook | return;
|
773 | a41b2ff2 | pbrook | } |
774 | a41b2ff2 | pbrook | } |
775 | a41b2ff2 | pbrook | |
776 | a41b2ff2 | pbrook | /* non-wrapping path or overwrapping enabled */
|
777 | a41b2ff2 | pbrook | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size ); |
778 | a41b2ff2 | pbrook | |
779 | a41b2ff2 | pbrook | s->RxBufAddr += size; |
780 | a41b2ff2 | pbrook | } |
781 | a41b2ff2 | pbrook | |
782 | a41b2ff2 | pbrook | #define MIN_BUF_SIZE 60 |
783 | c227f099 | Anthony Liguori | static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high) |
784 | a41b2ff2 | pbrook | { |
785 | a41b2ff2 | pbrook | #if TARGET_PHYS_ADDR_BITS > 32 |
786 | c227f099 | Anthony Liguori | return low | ((target_phys_addr_t)high << 32); |
787 | a41b2ff2 | pbrook | #else
|
788 | a41b2ff2 | pbrook | return low;
|
789 | a41b2ff2 | pbrook | #endif
|
790 | a41b2ff2 | pbrook | } |
791 | a41b2ff2 | pbrook | |
792 | 1673ad51 | Mark McLoughlin | static int rtl8139_can_receive(VLANClientState *nc) |
793 | a41b2ff2 | pbrook | { |
794 | 1673ad51 | Mark McLoughlin | RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
795 | a41b2ff2 | pbrook | int avail;
|
796 | a41b2ff2 | pbrook | |
797 | aa1f17c1 | ths | /* Receive (drop) packets if card is disabled. */
|
798 | a41b2ff2 | pbrook | if (!s->clock_enabled)
|
799 | a41b2ff2 | pbrook | return 1; |
800 | a41b2ff2 | pbrook | if (!rtl8139_receiver_enabled(s))
|
801 | a41b2ff2 | pbrook | return 1; |
802 | a41b2ff2 | pbrook | |
803 | a41b2ff2 | pbrook | if (rtl8139_cp_receiver_enabled(s)) {
|
804 | a41b2ff2 | pbrook | /* ??? Flow control not implemented in c+ mode.
|
805 | a41b2ff2 | pbrook | This is a hack to work around slirp deficiencies anyway. */
|
806 | a41b2ff2 | pbrook | return 1; |
807 | a41b2ff2 | pbrook | } else {
|
808 | a41b2ff2 | pbrook | avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, |
809 | a41b2ff2 | pbrook | s->RxBufferSize); |
810 | a41b2ff2 | pbrook | return (avail == 0 || avail >= 1514); |
811 | a41b2ff2 | pbrook | } |
812 | a41b2ff2 | pbrook | } |
813 | a41b2ff2 | pbrook | |
814 | 1673ad51 | Mark McLoughlin | static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) |
815 | a41b2ff2 | pbrook | { |
816 | 1673ad51 | Mark McLoughlin | RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
817 | 4f1c942b | Mark McLoughlin | int size = size_;
|
818 | a41b2ff2 | pbrook | |
819 | a41b2ff2 | pbrook | uint32_t packet_header = 0;
|
820 | a41b2ff2 | pbrook | |
821 | a41b2ff2 | pbrook | uint8_t buf1[60];
|
822 | 5fafdf24 | ths | static const uint8_t broadcast_macaddr[6] = |
823 | a41b2ff2 | pbrook | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
824 | a41b2ff2 | pbrook | |
825 | 6cadb320 | bellard | DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
|
826 | a41b2ff2 | pbrook | |
827 | a41b2ff2 | pbrook | /* test if board clock is stopped */
|
828 | a41b2ff2 | pbrook | if (!s->clock_enabled)
|
829 | a41b2ff2 | pbrook | { |
830 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
|
831 | 4f1c942b | Mark McLoughlin | return -1; |
832 | a41b2ff2 | pbrook | } |
833 | a41b2ff2 | pbrook | |
834 | a41b2ff2 | pbrook | /* first check if receiver is enabled */
|
835 | a41b2ff2 | pbrook | |
836 | a41b2ff2 | pbrook | if (!rtl8139_receiver_enabled(s))
|
837 | a41b2ff2 | pbrook | { |
838 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
|
839 | 4f1c942b | Mark McLoughlin | return -1; |
840 | a41b2ff2 | pbrook | } |
841 | a41b2ff2 | pbrook | |
842 | a41b2ff2 | pbrook | /* XXX: check this */
|
843 | a41b2ff2 | pbrook | if (s->RxConfig & AcceptAllPhys) {
|
844 | a41b2ff2 | pbrook | /* promiscuous: receive all */
|
845 | 6cadb320 | bellard | DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
|
846 | a41b2ff2 | pbrook | |
847 | a41b2ff2 | pbrook | } else {
|
848 | a41b2ff2 | pbrook | if (!memcmp(buf, broadcast_macaddr, 6)) { |
849 | a41b2ff2 | pbrook | /* broadcast address */
|
850 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptBroadcast))
|
851 | a41b2ff2 | pbrook | { |
852 | 6cadb320 | bellard | DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
|
853 | 6cadb320 | bellard | |
854 | 6cadb320 | bellard | /* update tally counter */
|
855 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
856 | 6cadb320 | bellard | |
857 | 4f1c942b | Mark McLoughlin | return size;
|
858 | a41b2ff2 | pbrook | } |
859 | a41b2ff2 | pbrook | |
860 | a41b2ff2 | pbrook | packet_header |= RxBroadcast; |
861 | a41b2ff2 | pbrook | |
862 | 6cadb320 | bellard | DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
|
863 | 6cadb320 | bellard | |
864 | 6cadb320 | bellard | /* update tally counter */
|
865 | 6cadb320 | bellard | ++s->tally_counters.RxOkBrd; |
866 | 6cadb320 | bellard | |
867 | a41b2ff2 | pbrook | } else if (buf[0] & 0x01) { |
868 | a41b2ff2 | pbrook | /* multicast */
|
869 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptMulticast))
|
870 | a41b2ff2 | pbrook | { |
871 | 6cadb320 | bellard | DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
|
872 | 6cadb320 | bellard | |
873 | 6cadb320 | bellard | /* update tally counter */
|
874 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
875 | 6cadb320 | bellard | |
876 | 4f1c942b | Mark McLoughlin | return size;
|
877 | a41b2ff2 | pbrook | } |
878 | a41b2ff2 | pbrook | |
879 | a41b2ff2 | pbrook | int mcast_idx = compute_mcast_idx(buf);
|
880 | a41b2ff2 | pbrook | |
881 | a41b2ff2 | pbrook | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
882 | a41b2ff2 | pbrook | { |
883 | 6cadb320 | bellard | DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
|
884 | 6cadb320 | bellard | |
885 | 6cadb320 | bellard | /* update tally counter */
|
886 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
887 | 6cadb320 | bellard | |
888 | 4f1c942b | Mark McLoughlin | return size;
|
889 | a41b2ff2 | pbrook | } |
890 | a41b2ff2 | pbrook | |
891 | a41b2ff2 | pbrook | packet_header |= RxMulticast; |
892 | a41b2ff2 | pbrook | |
893 | 6cadb320 | bellard | DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
|
894 | 6cadb320 | bellard | |
895 | 6cadb320 | bellard | /* update tally counter */
|
896 | 6cadb320 | bellard | ++s->tally_counters.RxOkMul; |
897 | 6cadb320 | bellard | |
898 | a41b2ff2 | pbrook | } else if (s->phys[0] == buf[0] && |
899 | 3b46e624 | ths | s->phys[1] == buf[1] && |
900 | 3b46e624 | ths | s->phys[2] == buf[2] && |
901 | 3b46e624 | ths | s->phys[3] == buf[3] && |
902 | 3b46e624 | ths | s->phys[4] == buf[4] && |
903 | a41b2ff2 | pbrook | s->phys[5] == buf[5]) { |
904 | a41b2ff2 | pbrook | /* match */
|
905 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptMyPhys))
|
906 | a41b2ff2 | pbrook | { |
907 | 6cadb320 | bellard | DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
|
908 | 6cadb320 | bellard | |
909 | 6cadb320 | bellard | /* update tally counter */
|
910 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
911 | 6cadb320 | bellard | |
912 | 4f1c942b | Mark McLoughlin | return size;
|
913 | a41b2ff2 | pbrook | } |
914 | a41b2ff2 | pbrook | |
915 | a41b2ff2 | pbrook | packet_header |= RxPhysical; |
916 | a41b2ff2 | pbrook | |
917 | 6cadb320 | bellard | DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
|
918 | 6cadb320 | bellard | |
919 | 6cadb320 | bellard | /* update tally counter */
|
920 | 6cadb320 | bellard | ++s->tally_counters.RxOkPhy; |
921 | a41b2ff2 | pbrook | |
922 | a41b2ff2 | pbrook | } else {
|
923 | a41b2ff2 | pbrook | |
924 | 6cadb320 | bellard | DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
|
925 | 6cadb320 | bellard | |
926 | 6cadb320 | bellard | /* update tally counter */
|
927 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
928 | 6cadb320 | bellard | |
929 | 4f1c942b | Mark McLoughlin | return size;
|
930 | a41b2ff2 | pbrook | } |
931 | a41b2ff2 | pbrook | } |
932 | a41b2ff2 | pbrook | |
933 | a41b2ff2 | pbrook | /* if too small buffer, then expand it */
|
934 | a41b2ff2 | pbrook | if (size < MIN_BUF_SIZE) {
|
935 | a41b2ff2 | pbrook | memcpy(buf1, buf, size); |
936 | a41b2ff2 | pbrook | memset(buf1 + size, 0, MIN_BUF_SIZE - size);
|
937 | a41b2ff2 | pbrook | buf = buf1; |
938 | a41b2ff2 | pbrook | size = MIN_BUF_SIZE; |
939 | a41b2ff2 | pbrook | } |
940 | a41b2ff2 | pbrook | |
941 | a41b2ff2 | pbrook | if (rtl8139_cp_receiver_enabled(s))
|
942 | a41b2ff2 | pbrook | { |
943 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
|
944 | a41b2ff2 | pbrook | |
945 | a41b2ff2 | pbrook | /* begin C+ receiver mode */
|
946 | a41b2ff2 | pbrook | |
947 | a41b2ff2 | pbrook | /* w0 ownership flag */
|
948 | a41b2ff2 | pbrook | #define CP_RX_OWN (1<<31) |
949 | a41b2ff2 | pbrook | /* w0 end of ring flag */
|
950 | a41b2ff2 | pbrook | #define CP_RX_EOR (1<<30) |
951 | a41b2ff2 | pbrook | /* w0 bits 0...12 : buffer size */
|
952 | a41b2ff2 | pbrook | #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) |
953 | a41b2ff2 | pbrook | /* w1 tag available flag */
|
954 | a41b2ff2 | pbrook | #define CP_RX_TAVA (1<<16) |
955 | a41b2ff2 | pbrook | /* w1 bits 0...15 : VLAN tag */
|
956 | a41b2ff2 | pbrook | #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) |
957 | a41b2ff2 | pbrook | /* w2 low 32bit of Rx buffer ptr */
|
958 | a41b2ff2 | pbrook | /* w3 high 32bit of Rx buffer ptr */
|
959 | a41b2ff2 | pbrook | |
960 | a41b2ff2 | pbrook | int descriptor = s->currCPlusRxDesc;
|
961 | c227f099 | Anthony Liguori | target_phys_addr_t cplus_rx_ring_desc; |
962 | a41b2ff2 | pbrook | |
963 | a41b2ff2 | pbrook | cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); |
964 | a41b2ff2 | pbrook | cplus_rx_ring_desc += 16 * descriptor;
|
965 | a41b2ff2 | pbrook | |
966 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n", |
967 | 6cadb320 | bellard | descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc)); |
968 | a41b2ff2 | pbrook | |
969 | a41b2ff2 | pbrook | uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; |
970 | a41b2ff2 | pbrook | |
971 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
|
972 | a41b2ff2 | pbrook | rxdw0 = le32_to_cpu(val); |
973 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
974 | a41b2ff2 | pbrook | rxdw1 = le32_to_cpu(val); |
975 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4); |
976 | a41b2ff2 | pbrook | rxbufLO = le32_to_cpu(val); |
977 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4); |
978 | a41b2ff2 | pbrook | rxbufHI = le32_to_cpu(val); |
979 | a41b2ff2 | pbrook | |
980 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
|
981 | a41b2ff2 | pbrook | descriptor, |
982 | 6cadb320 | bellard | rxdw0, rxdw1, rxbufLO, rxbufHI)); |
983 | a41b2ff2 | pbrook | |
984 | a41b2ff2 | pbrook | if (!(rxdw0 & CP_RX_OWN))
|
985 | a41b2ff2 | pbrook | { |
986 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
|
987 | 6cadb320 | bellard | |
988 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
989 | a41b2ff2 | pbrook | ++s->RxMissed; |
990 | 6cadb320 | bellard | |
991 | 6cadb320 | bellard | /* update tally counter */
|
992 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
993 | 6cadb320 | bellard | ++s->tally_counters.MissPkt; |
994 | 6cadb320 | bellard | |
995 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
996 | 4f1c942b | Mark McLoughlin | return size_;
|
997 | a41b2ff2 | pbrook | } |
998 | a41b2ff2 | pbrook | |
999 | a41b2ff2 | pbrook | uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; |
1000 | a41b2ff2 | pbrook | |
1001 | 6cadb320 | bellard | /* TODO: scatter the packet over available receive ring descriptors space */
|
1002 | 6cadb320 | bellard | |
1003 | a41b2ff2 | pbrook | if (size+4 > rx_space) |
1004 | a41b2ff2 | pbrook | { |
1005 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
|
1006 | 6cadb320 | bellard | descriptor, rx_space, size)); |
1007 | 6cadb320 | bellard | |
1008 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
1009 | a41b2ff2 | pbrook | ++s->RxMissed; |
1010 | 6cadb320 | bellard | |
1011 | 6cadb320 | bellard | /* update tally counter */
|
1012 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
1013 | 6cadb320 | bellard | ++s->tally_counters.MissPkt; |
1014 | 6cadb320 | bellard | |
1015 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1016 | 4f1c942b | Mark McLoughlin | return size_;
|
1017 | a41b2ff2 | pbrook | } |
1018 | a41b2ff2 | pbrook | |
1019 | c227f099 | Anthony Liguori | target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); |
1020 | a41b2ff2 | pbrook | |
1021 | a41b2ff2 | pbrook | /* receive/copy to target memory */
|
1022 | a41b2ff2 | pbrook | cpu_physical_memory_write( rx_addr, buf, size ); |
1023 | a41b2ff2 | pbrook | |
1024 | 6cadb320 | bellard | if (s->CpCmd & CPlusRxChkSum)
|
1025 | 6cadb320 | bellard | { |
1026 | 6cadb320 | bellard | /* do some packet checksumming */
|
1027 | 6cadb320 | bellard | } |
1028 | 6cadb320 | bellard | |
1029 | a41b2ff2 | pbrook | /* write checksum */
|
1030 | a41b2ff2 | pbrook | #if defined (RTL8139_CALCULATE_RXCRC)
|
1031 | ccf1d14a | ths | val = cpu_to_le32(crc32(0, buf, size));
|
1032 | a41b2ff2 | pbrook | #else
|
1033 | a41b2ff2 | pbrook | val = 0;
|
1034 | a41b2ff2 | pbrook | #endif
|
1035 | a41b2ff2 | pbrook | cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
|
1036 | a41b2ff2 | pbrook | |
1037 | a41b2ff2 | pbrook | /* first segment of received packet flag */
|
1038 | a41b2ff2 | pbrook | #define CP_RX_STATUS_FS (1<<29) |
1039 | a41b2ff2 | pbrook | /* last segment of received packet flag */
|
1040 | a41b2ff2 | pbrook | #define CP_RX_STATUS_LS (1<<28) |
1041 | a41b2ff2 | pbrook | /* multicast packet flag */
|
1042 | a41b2ff2 | pbrook | #define CP_RX_STATUS_MAR (1<<26) |
1043 | a41b2ff2 | pbrook | /* physical-matching packet flag */
|
1044 | a41b2ff2 | pbrook | #define CP_RX_STATUS_PAM (1<<25) |
1045 | a41b2ff2 | pbrook | /* broadcast packet flag */
|
1046 | a41b2ff2 | pbrook | #define CP_RX_STATUS_BAR (1<<24) |
1047 | a41b2ff2 | pbrook | /* runt packet flag */
|
1048 | a41b2ff2 | pbrook | #define CP_RX_STATUS_RUNT (1<<19) |
1049 | a41b2ff2 | pbrook | /* crc error flag */
|
1050 | a41b2ff2 | pbrook | #define CP_RX_STATUS_CRC (1<<18) |
1051 | a41b2ff2 | pbrook | /* IP checksum error flag */
|
1052 | a41b2ff2 | pbrook | #define CP_RX_STATUS_IPF (1<<15) |
1053 | a41b2ff2 | pbrook | /* UDP checksum error flag */
|
1054 | a41b2ff2 | pbrook | #define CP_RX_STATUS_UDPF (1<<14) |
1055 | a41b2ff2 | pbrook | /* TCP checksum error flag */
|
1056 | a41b2ff2 | pbrook | #define CP_RX_STATUS_TCPF (1<<13) |
1057 | a41b2ff2 | pbrook | |
1058 | a41b2ff2 | pbrook | /* transfer ownership to target */
|
1059 | a41b2ff2 | pbrook | rxdw0 &= ~CP_RX_OWN; |
1060 | a41b2ff2 | pbrook | |
1061 | a41b2ff2 | pbrook | /* set first segment bit */
|
1062 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_FS; |
1063 | a41b2ff2 | pbrook | |
1064 | a41b2ff2 | pbrook | /* set last segment bit */
|
1065 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_LS; |
1066 | a41b2ff2 | pbrook | |
1067 | a41b2ff2 | pbrook | /* set received packet type flags */
|
1068 | a41b2ff2 | pbrook | if (packet_header & RxBroadcast)
|
1069 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_BAR; |
1070 | a41b2ff2 | pbrook | if (packet_header & RxMulticast)
|
1071 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_MAR; |
1072 | a41b2ff2 | pbrook | if (packet_header & RxPhysical)
|
1073 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_PAM; |
1074 | a41b2ff2 | pbrook | |
1075 | a41b2ff2 | pbrook | /* set received size */
|
1076 | a41b2ff2 | pbrook | rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; |
1077 | a41b2ff2 | pbrook | rxdw0 |= (size+4);
|
1078 | a41b2ff2 | pbrook | |
1079 | a41b2ff2 | pbrook | /* reset VLAN tag flag */
|
1080 | a41b2ff2 | pbrook | rxdw1 &= ~CP_RX_TAVA; |
1081 | a41b2ff2 | pbrook | |
1082 | a41b2ff2 | pbrook | /* update ring data */
|
1083 | a41b2ff2 | pbrook | val = cpu_to_le32(rxdw0); |
1084 | a41b2ff2 | pbrook | cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
|
1085 | a41b2ff2 | pbrook | val = cpu_to_le32(rxdw1); |
1086 | a41b2ff2 | pbrook | cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
1087 | a41b2ff2 | pbrook | |
1088 | 6cadb320 | bellard | /* update tally counter */
|
1089 | 6cadb320 | bellard | ++s->tally_counters.RxOk; |
1090 | 6cadb320 | bellard | |
1091 | a41b2ff2 | pbrook | /* seek to next Rx descriptor */
|
1092 | a41b2ff2 | pbrook | if (rxdw0 & CP_RX_EOR)
|
1093 | a41b2ff2 | pbrook | { |
1094 | a41b2ff2 | pbrook | s->currCPlusRxDesc = 0;
|
1095 | a41b2ff2 | pbrook | } |
1096 | a41b2ff2 | pbrook | else
|
1097 | a41b2ff2 | pbrook | { |
1098 | a41b2ff2 | pbrook | ++s->currCPlusRxDesc; |
1099 | a41b2ff2 | pbrook | } |
1100 | a41b2ff2 | pbrook | |
1101 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
|
1102 | a41b2ff2 | pbrook | |
1103 | a41b2ff2 | pbrook | } |
1104 | a41b2ff2 | pbrook | else
|
1105 | a41b2ff2 | pbrook | { |
1106 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
|
1107 | 6cadb320 | bellard | |
1108 | a41b2ff2 | pbrook | /* begin ring receiver mode */
|
1109 | a41b2ff2 | pbrook | int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
|
1110 | a41b2ff2 | pbrook | |
1111 | a41b2ff2 | pbrook | /* if receiver buffer is empty then avail == 0 */
|
1112 | a41b2ff2 | pbrook | |
1113 | a41b2ff2 | pbrook | if (avail != 0 && size + 8 >= avail) |
1114 | a41b2ff2 | pbrook | { |
1115 | 6cadb320 | bellard | DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
|
1116 | 6cadb320 | bellard | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
|
1117 | 6cadb320 | bellard | |
1118 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
1119 | a41b2ff2 | pbrook | ++s->RxMissed; |
1120 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1121 | 4f1c942b | Mark McLoughlin | return size_;
|
1122 | a41b2ff2 | pbrook | } |
1123 | a41b2ff2 | pbrook | |
1124 | a41b2ff2 | pbrook | packet_header |= RxStatusOK; |
1125 | a41b2ff2 | pbrook | |
1126 | a41b2ff2 | pbrook | packet_header |= (((size+4) << 16) & 0xffff0000); |
1127 | a41b2ff2 | pbrook | |
1128 | a41b2ff2 | pbrook | /* write header */
|
1129 | a41b2ff2 | pbrook | uint32_t val = cpu_to_le32(packet_header); |
1130 | a41b2ff2 | pbrook | |
1131 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
1132 | a41b2ff2 | pbrook | |
1133 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, buf, size); |
1134 | a41b2ff2 | pbrook | |
1135 | a41b2ff2 | pbrook | /* write checksum */
|
1136 | a41b2ff2 | pbrook | #if defined (RTL8139_CALCULATE_RXCRC)
|
1137 | ccf1d14a | ths | val = cpu_to_le32(crc32(0, buf, size));
|
1138 | a41b2ff2 | pbrook | #else
|
1139 | a41b2ff2 | pbrook | val = 0;
|
1140 | a41b2ff2 | pbrook | #endif
|
1141 | a41b2ff2 | pbrook | |
1142 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
1143 | a41b2ff2 | pbrook | |
1144 | a41b2ff2 | pbrook | /* correct buffer write pointer */
|
1145 | a41b2ff2 | pbrook | s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize); |
1146 | a41b2ff2 | pbrook | |
1147 | a41b2ff2 | pbrook | /* now we can signal we have received something */
|
1148 | a41b2ff2 | pbrook | |
1149 | 6cadb320 | bellard | DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
|
1150 | 6cadb320 | bellard | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr)); |
1151 | a41b2ff2 | pbrook | } |
1152 | a41b2ff2 | pbrook | |
1153 | a41b2ff2 | pbrook | s->IntrStatus |= RxOK; |
1154 | 6cadb320 | bellard | |
1155 | 6cadb320 | bellard | if (do_interrupt)
|
1156 | 6cadb320 | bellard | { |
1157 | 6cadb320 | bellard | rtl8139_update_irq(s); |
1158 | 6cadb320 | bellard | } |
1159 | 4f1c942b | Mark McLoughlin | |
1160 | 4f1c942b | Mark McLoughlin | return size_;
|
1161 | 6cadb320 | bellard | } |
1162 | 6cadb320 | bellard | |
1163 | 1673ad51 | Mark McLoughlin | static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size) |
1164 | 6cadb320 | bellard | { |
1165 | 1673ad51 | Mark McLoughlin | return rtl8139_do_receive(nc, buf, size, 1); |
1166 | a41b2ff2 | pbrook | } |
1167 | a41b2ff2 | pbrook | |
1168 | a41b2ff2 | pbrook | static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) |
1169 | a41b2ff2 | pbrook | { |
1170 | a41b2ff2 | pbrook | s->RxBufferSize = bufferSize; |
1171 | a41b2ff2 | pbrook | s->RxBufPtr = 0;
|
1172 | a41b2ff2 | pbrook | s->RxBufAddr = 0;
|
1173 | a41b2ff2 | pbrook | } |
1174 | a41b2ff2 | pbrook | |
1175 | 7f23f812 | Michael S. Tsirkin | static void rtl8139_reset(DeviceState *d) |
1176 | a41b2ff2 | pbrook | { |
1177 | 7f23f812 | Michael S. Tsirkin | RTL8139State *s = container_of(d, RTL8139State, dev.qdev); |
1178 | a41b2ff2 | pbrook | int i;
|
1179 | a41b2ff2 | pbrook | |
1180 | a41b2ff2 | pbrook | /* restore MAC address */
|
1181 | 254111ec | Gerd Hoffmann | memcpy(s->phys, s->conf.macaddr.a, 6);
|
1182 | a41b2ff2 | pbrook | |
1183 | a41b2ff2 | pbrook | /* reset interrupt mask */
|
1184 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
1185 | a41b2ff2 | pbrook | s->IntrMask = 0;
|
1186 | a41b2ff2 | pbrook | |
1187 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1188 | a41b2ff2 | pbrook | |
1189 | a41b2ff2 | pbrook | /* prepare eeprom */
|
1190 | a41b2ff2 | pbrook | s->eeprom.contents[0] = 0x8129; |
1191 | 6cadb320 | bellard | #if 1 |
1192 | 6cadb320 | bellard | // PCI vendor and device ID should be mirrored here
|
1193 | deb54399 | aliguori | s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
|
1194 | deb54399 | aliguori | s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
|
1195 | 6cadb320 | bellard | #endif
|
1196 | 290a0933 | ths | |
1197 | 254111ec | Gerd Hoffmann | s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; |
1198 | 254111ec | Gerd Hoffmann | s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; |
1199 | 254111ec | Gerd Hoffmann | s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; |
1200 | a41b2ff2 | pbrook | |
1201 | a41b2ff2 | pbrook | /* mark all status registers as owned by host */
|
1202 | a41b2ff2 | pbrook | for (i = 0; i < 4; ++i) |
1203 | a41b2ff2 | pbrook | { |
1204 | a41b2ff2 | pbrook | s->TxStatus[i] = TxHostOwns; |
1205 | a41b2ff2 | pbrook | } |
1206 | a41b2ff2 | pbrook | |
1207 | a41b2ff2 | pbrook | s->currTxDesc = 0;
|
1208 | a41b2ff2 | pbrook | s->currCPlusRxDesc = 0;
|
1209 | a41b2ff2 | pbrook | s->currCPlusTxDesc = 0;
|
1210 | a41b2ff2 | pbrook | |
1211 | a41b2ff2 | pbrook | s->RxRingAddrLO = 0;
|
1212 | a41b2ff2 | pbrook | s->RxRingAddrHI = 0;
|
1213 | a41b2ff2 | pbrook | |
1214 | a41b2ff2 | pbrook | s->RxBuf = 0;
|
1215 | a41b2ff2 | pbrook | |
1216 | a41b2ff2 | pbrook | rtl8139_reset_rxring(s, 8192);
|
1217 | a41b2ff2 | pbrook | |
1218 | a41b2ff2 | pbrook | /* ACK the reset */
|
1219 | a41b2ff2 | pbrook | s->TxConfig = 0;
|
1220 | a41b2ff2 | pbrook | |
1221 | a41b2ff2 | pbrook | #if 0
|
1222 | a41b2ff2 | pbrook | // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
|
1223 | a41b2ff2 | pbrook | s->clock_enabled = 0;
|
1224 | a41b2ff2 | pbrook | #else
|
1225 | 6cadb320 | bellard | s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake |
1226 | a41b2ff2 | pbrook | s->clock_enabled = 1;
|
1227 | a41b2ff2 | pbrook | #endif
|
1228 | a41b2ff2 | pbrook | |
1229 | a41b2ff2 | pbrook | s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
|
1230 | a41b2ff2 | pbrook | |
1231 | a41b2ff2 | pbrook | /* set initial state data */
|
1232 | a41b2ff2 | pbrook | s->Config0 = 0x0; /* No boot ROM */ |
1233 | a41b2ff2 | pbrook | s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ |
1234 | a41b2ff2 | pbrook | s->Config3 = 0x1; /* fast back-to-back compatible */ |
1235 | a41b2ff2 | pbrook | s->Config5 = 0x0;
|
1236 | a41b2ff2 | pbrook | |
1237 | 5fafdf24 | ths | s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; |
1238 | a41b2ff2 | pbrook | |
1239 | a41b2ff2 | pbrook | s->CpCmd = 0x0; /* reset C+ mode */ |
1240 | 2c3891ab | aliguori | s->cplus_enabled = 0;
|
1241 | 2c3891ab | aliguori | |
1242 | a41b2ff2 | pbrook | |
1243 | a41b2ff2 | pbrook | // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
|
1244 | a41b2ff2 | pbrook | // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
|
1245 | a41b2ff2 | pbrook | s->BasicModeCtrl = 0x1000; // autonegotiation |
1246 | a41b2ff2 | pbrook | |
1247 | a41b2ff2 | pbrook | s->BasicModeStatus = 0x7809;
|
1248 | a41b2ff2 | pbrook | //s->BasicModeStatus |= 0x0040; /* UTP medium */
|
1249 | a41b2ff2 | pbrook | s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ |
1250 | a41b2ff2 | pbrook | s->BasicModeStatus |= 0x0004; /* link is up */ |
1251 | a41b2ff2 | pbrook | |
1252 | a41b2ff2 | pbrook | s->NWayAdvert = 0x05e1; /* all modes, full duplex */ |
1253 | a41b2ff2 | pbrook | s->NWayLPAR = 0x05e1; /* all modes, full duplex */ |
1254 | a41b2ff2 | pbrook | s->NWayExpansion = 0x0001; /* autonegotiation supported */ |
1255 | 6cadb320 | bellard | |
1256 | 6cadb320 | bellard | /* also reset timer and disable timer interrupt */
|
1257 | 6cadb320 | bellard | s->TCTR = 0;
|
1258 | 6cadb320 | bellard | s->TimerInt = 0;
|
1259 | 6cadb320 | bellard | s->TCTR_base = 0;
|
1260 | 6cadb320 | bellard | |
1261 | 6cadb320 | bellard | /* reset tally counters */
|
1262 | 6cadb320 | bellard | RTL8139TallyCounters_clear(&s->tally_counters); |
1263 | 6cadb320 | bellard | } |
1264 | 6cadb320 | bellard | |
1265 | b1d8e52e | blueswir1 | static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) |
1266 | 6cadb320 | bellard | { |
1267 | 6cadb320 | bellard | counters->TxOk = 0;
|
1268 | 6cadb320 | bellard | counters->RxOk = 0;
|
1269 | 6cadb320 | bellard | counters->TxERR = 0;
|
1270 | 6cadb320 | bellard | counters->RxERR = 0;
|
1271 | 6cadb320 | bellard | counters->MissPkt = 0;
|
1272 | 6cadb320 | bellard | counters->FAE = 0;
|
1273 | 6cadb320 | bellard | counters->Tx1Col = 0;
|
1274 | 6cadb320 | bellard | counters->TxMCol = 0;
|
1275 | 6cadb320 | bellard | counters->RxOkPhy = 0;
|
1276 | 6cadb320 | bellard | counters->RxOkBrd = 0;
|
1277 | 6cadb320 | bellard | counters->RxOkMul = 0;
|
1278 | 6cadb320 | bellard | counters->TxAbt = 0;
|
1279 | 6cadb320 | bellard | counters->TxUndrn = 0;
|
1280 | 6cadb320 | bellard | } |
1281 | 6cadb320 | bellard | |
1282 | c227f099 | Anthony Liguori | static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters) |
1283 | 6cadb320 | bellard | { |
1284 | 6cadb320 | bellard | uint16_t val16; |
1285 | 6cadb320 | bellard | uint32_t val32; |
1286 | 6cadb320 | bellard | uint64_t val64; |
1287 | 6cadb320 | bellard | |
1288 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->TxOk); |
1289 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8); |
1290 | 6cadb320 | bellard | |
1291 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->RxOk); |
1292 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8); |
1293 | 6cadb320 | bellard | |
1294 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->TxERR); |
1295 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8); |
1296 | 6cadb320 | bellard | |
1297 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->RxERR); |
1298 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4); |
1299 | 6cadb320 | bellard | |
1300 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->MissPkt); |
1301 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2); |
1302 | 6cadb320 | bellard | |
1303 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->FAE); |
1304 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2); |
1305 | 6cadb320 | bellard | |
1306 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->Tx1Col); |
1307 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4); |
1308 | 6cadb320 | bellard | |
1309 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->TxMCol); |
1310 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4); |
1311 | 6cadb320 | bellard | |
1312 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->RxOkPhy); |
1313 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8); |
1314 | 6cadb320 | bellard | |
1315 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->RxOkBrd); |
1316 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8); |
1317 | 6cadb320 | bellard | |
1318 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->RxOkMul); |
1319 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4); |
1320 | 6cadb320 | bellard | |
1321 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->TxAbt); |
1322 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2); |
1323 | 6cadb320 | bellard | |
1324 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->TxUndrn); |
1325 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2); |
1326 | 6cadb320 | bellard | } |
1327 | 6cadb320 | bellard | |
1328 | 6cadb320 | bellard | /* Loads values of tally counters from VM state file */
|
1329 | 9d29cdea | Juan Quintela | |
1330 | 9d29cdea | Juan Quintela | static const VMStateDescription vmstate_tally_counters = { |
1331 | 9d29cdea | Juan Quintela | .name = "tally_counters",
|
1332 | 9d29cdea | Juan Quintela | .version_id = 1,
|
1333 | 9d29cdea | Juan Quintela | .minimum_version_id = 1,
|
1334 | 9d29cdea | Juan Quintela | .minimum_version_id_old = 1,
|
1335 | 9d29cdea | Juan Quintela | .fields = (VMStateField []) { |
1336 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(TxOk, RTL8139TallyCounters), |
1337 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(RxOk, RTL8139TallyCounters), |
1338 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(TxERR, RTL8139TallyCounters), |
1339 | 9d29cdea | Juan Quintela | VMSTATE_UINT32(RxERR, RTL8139TallyCounters), |
1340 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(MissPkt, RTL8139TallyCounters), |
1341 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(FAE, RTL8139TallyCounters), |
1342 | 9d29cdea | Juan Quintela | VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters), |
1343 | 9d29cdea | Juan Quintela | VMSTATE_UINT32(TxMCol, RTL8139TallyCounters), |
1344 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters), |
1345 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters), |
1346 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(TxAbt, RTL8139TallyCounters), |
1347 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters), |
1348 | 9d29cdea | Juan Quintela | VMSTATE_END_OF_LIST() |
1349 | 9d29cdea | Juan Quintela | } |
1350 | 9d29cdea | Juan Quintela | }; |
1351 | a41b2ff2 | pbrook | |
1352 | a41b2ff2 | pbrook | static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) |
1353 | a41b2ff2 | pbrook | { |
1354 | a41b2ff2 | pbrook | val &= 0xff;
|
1355 | a41b2ff2 | pbrook | |
1356 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
|
1357 | a41b2ff2 | pbrook | |
1358 | a41b2ff2 | pbrook | if (val & CmdReset)
|
1359 | a41b2ff2 | pbrook | { |
1360 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
|
1361 | 7f23f812 | Michael S. Tsirkin | rtl8139_reset(&s->dev.qdev); |
1362 | a41b2ff2 | pbrook | } |
1363 | a41b2ff2 | pbrook | if (val & CmdRxEnb)
|
1364 | a41b2ff2 | pbrook | { |
1365 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
|
1366 | 718da2b9 | bellard | |
1367 | 718da2b9 | bellard | s->currCPlusRxDesc = 0;
|
1368 | a41b2ff2 | pbrook | } |
1369 | a41b2ff2 | pbrook | if (val & CmdTxEnb)
|
1370 | a41b2ff2 | pbrook | { |
1371 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
|
1372 | 718da2b9 | bellard | |
1373 | 718da2b9 | bellard | s->currCPlusTxDesc = 0;
|
1374 | a41b2ff2 | pbrook | } |
1375 | a41b2ff2 | pbrook | |
1376 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1377 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xe3, s->bChipCmdState);
|
1378 | a41b2ff2 | pbrook | |
1379 | a41b2ff2 | pbrook | /* Deassert reset pin before next read */
|
1380 | a41b2ff2 | pbrook | val &= ~CmdReset; |
1381 | a41b2ff2 | pbrook | |
1382 | a41b2ff2 | pbrook | s->bChipCmdState = val; |
1383 | a41b2ff2 | pbrook | } |
1384 | a41b2ff2 | pbrook | |
1385 | a41b2ff2 | pbrook | static int rtl8139_RxBufferEmpty(RTL8139State *s) |
1386 | a41b2ff2 | pbrook | { |
1387 | a41b2ff2 | pbrook | int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
|
1388 | a41b2ff2 | pbrook | |
1389 | a41b2ff2 | pbrook | if (unread != 0) |
1390 | a41b2ff2 | pbrook | { |
1391 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
|
1392 | a41b2ff2 | pbrook | return 0; |
1393 | a41b2ff2 | pbrook | } |
1394 | a41b2ff2 | pbrook | |
1395 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
|
1396 | a41b2ff2 | pbrook | |
1397 | a41b2ff2 | pbrook | return 1; |
1398 | a41b2ff2 | pbrook | } |
1399 | a41b2ff2 | pbrook | |
1400 | a41b2ff2 | pbrook | static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
|
1401 | a41b2ff2 | pbrook | { |
1402 | a41b2ff2 | pbrook | uint32_t ret = s->bChipCmdState; |
1403 | a41b2ff2 | pbrook | |
1404 | a41b2ff2 | pbrook | if (rtl8139_RxBufferEmpty(s))
|
1405 | a41b2ff2 | pbrook | ret |= RxBufEmpty; |
1406 | a41b2ff2 | pbrook | |
1407 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
|
1408 | a41b2ff2 | pbrook | |
1409 | a41b2ff2 | pbrook | return ret;
|
1410 | a41b2ff2 | pbrook | } |
1411 | a41b2ff2 | pbrook | |
1412 | a41b2ff2 | pbrook | static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) |
1413 | a41b2ff2 | pbrook | { |
1414 | a41b2ff2 | pbrook | val &= 0xffff;
|
1415 | a41b2ff2 | pbrook | |
1416 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
|
1417 | a41b2ff2 | pbrook | |
1418 | 2c3891ab | aliguori | s->cplus_enabled = 1;
|
1419 | 2c3891ab | aliguori | |
1420 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1421 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xff84, s->CpCmd);
|
1422 | a41b2ff2 | pbrook | |
1423 | a41b2ff2 | pbrook | s->CpCmd = val; |
1424 | a41b2ff2 | pbrook | } |
1425 | a41b2ff2 | pbrook | |
1426 | a41b2ff2 | pbrook | static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
|
1427 | a41b2ff2 | pbrook | { |
1428 | a41b2ff2 | pbrook | uint32_t ret = s->CpCmd; |
1429 | a41b2ff2 | pbrook | |
1430 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
|
1431 | 6cadb320 | bellard | |
1432 | 6cadb320 | bellard | return ret;
|
1433 | 6cadb320 | bellard | } |
1434 | 6cadb320 | bellard | |
1435 | 6cadb320 | bellard | static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) |
1436 | 6cadb320 | bellard | { |
1437 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
|
1438 | 6cadb320 | bellard | } |
1439 | 6cadb320 | bellard | |
1440 | 6cadb320 | bellard | static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
|
1441 | 6cadb320 | bellard | { |
1442 | 6cadb320 | bellard | uint32_t ret = 0;
|
1443 | 6cadb320 | bellard | |
1444 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
|
1445 | a41b2ff2 | pbrook | |
1446 | a41b2ff2 | pbrook | return ret;
|
1447 | a41b2ff2 | pbrook | } |
1448 | a41b2ff2 | pbrook | |
1449 | 9596ebb7 | pbrook | static int rtl8139_config_writeable(RTL8139State *s) |
1450 | a41b2ff2 | pbrook | { |
1451 | a41b2ff2 | pbrook | if (s->Cfg9346 & Cfg9346_Unlock)
|
1452 | a41b2ff2 | pbrook | { |
1453 | a41b2ff2 | pbrook | return 1; |
1454 | a41b2ff2 | pbrook | } |
1455 | a41b2ff2 | pbrook | |
1456 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
|
1457 | a41b2ff2 | pbrook | |
1458 | a41b2ff2 | pbrook | return 0; |
1459 | a41b2ff2 | pbrook | } |
1460 | a41b2ff2 | pbrook | |
1461 | a41b2ff2 | pbrook | static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) |
1462 | a41b2ff2 | pbrook | { |
1463 | a41b2ff2 | pbrook | val &= 0xffff;
|
1464 | a41b2ff2 | pbrook | |
1465 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
|
1466 | a41b2ff2 | pbrook | |
1467 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1468 | e3d7e843 | ths | uint32_t mask = 0x4cff;
|
1469 | a41b2ff2 | pbrook | |
1470 | a41b2ff2 | pbrook | if (1 || !rtl8139_config_writeable(s)) |
1471 | a41b2ff2 | pbrook | { |
1472 | a41b2ff2 | pbrook | /* Speed setting and autonegotiation enable bits are read-only */
|
1473 | a41b2ff2 | pbrook | mask |= 0x3000;
|
1474 | a41b2ff2 | pbrook | /* Duplex mode setting is read-only */
|
1475 | a41b2ff2 | pbrook | mask |= 0x0100;
|
1476 | a41b2ff2 | pbrook | } |
1477 | a41b2ff2 | pbrook | |
1478 | a41b2ff2 | pbrook | val = SET_MASKED(val, mask, s->BasicModeCtrl); |
1479 | a41b2ff2 | pbrook | |
1480 | a41b2ff2 | pbrook | s->BasicModeCtrl = val; |
1481 | a41b2ff2 | pbrook | } |
1482 | a41b2ff2 | pbrook | |
1483 | a41b2ff2 | pbrook | static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
|
1484 | a41b2ff2 | pbrook | { |
1485 | a41b2ff2 | pbrook | uint32_t ret = s->BasicModeCtrl; |
1486 | a41b2ff2 | pbrook | |
1487 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
|
1488 | a41b2ff2 | pbrook | |
1489 | a41b2ff2 | pbrook | return ret;
|
1490 | a41b2ff2 | pbrook | } |
1491 | a41b2ff2 | pbrook | |
1492 | a41b2ff2 | pbrook | static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) |
1493 | a41b2ff2 | pbrook | { |
1494 | a41b2ff2 | pbrook | val &= 0xffff;
|
1495 | a41b2ff2 | pbrook | |
1496 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
|
1497 | a41b2ff2 | pbrook | |
1498 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1499 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
|
1500 | a41b2ff2 | pbrook | |
1501 | a41b2ff2 | pbrook | s->BasicModeStatus = val; |
1502 | a41b2ff2 | pbrook | } |
1503 | a41b2ff2 | pbrook | |
1504 | a41b2ff2 | pbrook | static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
|
1505 | a41b2ff2 | pbrook | { |
1506 | a41b2ff2 | pbrook | uint32_t ret = s->BasicModeStatus; |
1507 | a41b2ff2 | pbrook | |
1508 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
|
1509 | a41b2ff2 | pbrook | |
1510 | a41b2ff2 | pbrook | return ret;
|
1511 | a41b2ff2 | pbrook | } |
1512 | a41b2ff2 | pbrook | |
1513 | a41b2ff2 | pbrook | static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) |
1514 | a41b2ff2 | pbrook | { |
1515 | a41b2ff2 | pbrook | val &= 0xff;
|
1516 | a41b2ff2 | pbrook | |
1517 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
|
1518 | a41b2ff2 | pbrook | |
1519 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1520 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x31, s->Cfg9346);
|
1521 | a41b2ff2 | pbrook | |
1522 | a41b2ff2 | pbrook | uint32_t opmode = val & 0xc0;
|
1523 | a41b2ff2 | pbrook | uint32_t eeprom_val = val & 0xf;
|
1524 | a41b2ff2 | pbrook | |
1525 | a41b2ff2 | pbrook | if (opmode == 0x80) { |
1526 | a41b2ff2 | pbrook | /* eeprom access */
|
1527 | a41b2ff2 | pbrook | int eecs = (eeprom_val & 0x08)?1:0; |
1528 | a41b2ff2 | pbrook | int eesk = (eeprom_val & 0x04)?1:0; |
1529 | a41b2ff2 | pbrook | int eedi = (eeprom_val & 0x02)?1:0; |
1530 | a41b2ff2 | pbrook | prom9346_set_wire(s, eecs, eesk, eedi); |
1531 | a41b2ff2 | pbrook | } else if (opmode == 0x40) { |
1532 | a41b2ff2 | pbrook | /* Reset. */
|
1533 | a41b2ff2 | pbrook | val = 0;
|
1534 | 7f23f812 | Michael S. Tsirkin | rtl8139_reset(&s->dev.qdev); |
1535 | a41b2ff2 | pbrook | } |
1536 | a41b2ff2 | pbrook | |
1537 | a41b2ff2 | pbrook | s->Cfg9346 = val; |
1538 | a41b2ff2 | pbrook | } |
1539 | a41b2ff2 | pbrook | |
1540 | a41b2ff2 | pbrook | static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
|
1541 | a41b2ff2 | pbrook | { |
1542 | a41b2ff2 | pbrook | uint32_t ret = s->Cfg9346; |
1543 | a41b2ff2 | pbrook | |
1544 | a41b2ff2 | pbrook | uint32_t opmode = ret & 0xc0;
|
1545 | a41b2ff2 | pbrook | |
1546 | a41b2ff2 | pbrook | if (opmode == 0x80) |
1547 | a41b2ff2 | pbrook | { |
1548 | a41b2ff2 | pbrook | /* eeprom access */
|
1549 | a41b2ff2 | pbrook | int eedo = prom9346_get_wire(s);
|
1550 | a41b2ff2 | pbrook | if (eedo)
|
1551 | a41b2ff2 | pbrook | { |
1552 | a41b2ff2 | pbrook | ret |= 0x01;
|
1553 | a41b2ff2 | pbrook | } |
1554 | a41b2ff2 | pbrook | else
|
1555 | a41b2ff2 | pbrook | { |
1556 | a41b2ff2 | pbrook | ret &= ~0x01;
|
1557 | a41b2ff2 | pbrook | } |
1558 | a41b2ff2 | pbrook | } |
1559 | a41b2ff2 | pbrook | |
1560 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
|
1561 | a41b2ff2 | pbrook | |
1562 | a41b2ff2 | pbrook | return ret;
|
1563 | a41b2ff2 | pbrook | } |
1564 | a41b2ff2 | pbrook | |
1565 | a41b2ff2 | pbrook | static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) |
1566 | a41b2ff2 | pbrook | { |
1567 | a41b2ff2 | pbrook | val &= 0xff;
|
1568 | a41b2ff2 | pbrook | |
1569 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
|
1570 | a41b2ff2 | pbrook | |
1571 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1572 | a41b2ff2 | pbrook | return;
|
1573 | a41b2ff2 | pbrook | |
1574 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1575 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf8, s->Config0);
|
1576 | a41b2ff2 | pbrook | |
1577 | a41b2ff2 | pbrook | s->Config0 = val; |
1578 | a41b2ff2 | pbrook | } |
1579 | a41b2ff2 | pbrook | |
1580 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config0_read(RTL8139State *s)
|
1581 | a41b2ff2 | pbrook | { |
1582 | a41b2ff2 | pbrook | uint32_t ret = s->Config0; |
1583 | a41b2ff2 | pbrook | |
1584 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
|
1585 | a41b2ff2 | pbrook | |
1586 | a41b2ff2 | pbrook | return ret;
|
1587 | a41b2ff2 | pbrook | } |
1588 | a41b2ff2 | pbrook | |
1589 | a41b2ff2 | pbrook | static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) |
1590 | a41b2ff2 | pbrook | { |
1591 | a41b2ff2 | pbrook | val &= 0xff;
|
1592 | a41b2ff2 | pbrook | |
1593 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
|
1594 | a41b2ff2 | pbrook | |
1595 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1596 | a41b2ff2 | pbrook | return;
|
1597 | a41b2ff2 | pbrook | |
1598 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1599 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xC, s->Config1);
|
1600 | a41b2ff2 | pbrook | |
1601 | a41b2ff2 | pbrook | s->Config1 = val; |
1602 | a41b2ff2 | pbrook | } |
1603 | a41b2ff2 | pbrook | |
1604 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config1_read(RTL8139State *s)
|
1605 | a41b2ff2 | pbrook | { |
1606 | a41b2ff2 | pbrook | uint32_t ret = s->Config1; |
1607 | a41b2ff2 | pbrook | |
1608 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
|
1609 | a41b2ff2 | pbrook | |
1610 | a41b2ff2 | pbrook | return ret;
|
1611 | a41b2ff2 | pbrook | } |
1612 | a41b2ff2 | pbrook | |
1613 | a41b2ff2 | pbrook | static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) |
1614 | a41b2ff2 | pbrook | { |
1615 | a41b2ff2 | pbrook | val &= 0xff;
|
1616 | a41b2ff2 | pbrook | |
1617 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
|
1618 | a41b2ff2 | pbrook | |
1619 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1620 | a41b2ff2 | pbrook | return;
|
1621 | a41b2ff2 | pbrook | |
1622 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1623 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x8F, s->Config3);
|
1624 | a41b2ff2 | pbrook | |
1625 | a41b2ff2 | pbrook | s->Config3 = val; |
1626 | a41b2ff2 | pbrook | } |
1627 | a41b2ff2 | pbrook | |
1628 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config3_read(RTL8139State *s)
|
1629 | a41b2ff2 | pbrook | { |
1630 | a41b2ff2 | pbrook | uint32_t ret = s->Config3; |
1631 | a41b2ff2 | pbrook | |
1632 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
|
1633 | a41b2ff2 | pbrook | |
1634 | a41b2ff2 | pbrook | return ret;
|
1635 | a41b2ff2 | pbrook | } |
1636 | a41b2ff2 | pbrook | |
1637 | a41b2ff2 | pbrook | static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) |
1638 | a41b2ff2 | pbrook | { |
1639 | a41b2ff2 | pbrook | val &= 0xff;
|
1640 | a41b2ff2 | pbrook | |
1641 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
|
1642 | a41b2ff2 | pbrook | |
1643 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1644 | a41b2ff2 | pbrook | return;
|
1645 | a41b2ff2 | pbrook | |
1646 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1647 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x0a, s->Config4);
|
1648 | a41b2ff2 | pbrook | |
1649 | a41b2ff2 | pbrook | s->Config4 = val; |
1650 | a41b2ff2 | pbrook | } |
1651 | a41b2ff2 | pbrook | |
1652 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config4_read(RTL8139State *s)
|
1653 | a41b2ff2 | pbrook | { |
1654 | a41b2ff2 | pbrook | uint32_t ret = s->Config4; |
1655 | a41b2ff2 | pbrook | |
1656 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
|
1657 | a41b2ff2 | pbrook | |
1658 | a41b2ff2 | pbrook | return ret;
|
1659 | a41b2ff2 | pbrook | } |
1660 | a41b2ff2 | pbrook | |
1661 | a41b2ff2 | pbrook | static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) |
1662 | a41b2ff2 | pbrook | { |
1663 | a41b2ff2 | pbrook | val &= 0xff;
|
1664 | a41b2ff2 | pbrook | |
1665 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
|
1666 | a41b2ff2 | pbrook | |
1667 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1668 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x80, s->Config5);
|
1669 | a41b2ff2 | pbrook | |
1670 | a41b2ff2 | pbrook | s->Config5 = val; |
1671 | a41b2ff2 | pbrook | } |
1672 | a41b2ff2 | pbrook | |
1673 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config5_read(RTL8139State *s)
|
1674 | a41b2ff2 | pbrook | { |
1675 | a41b2ff2 | pbrook | uint32_t ret = s->Config5; |
1676 | a41b2ff2 | pbrook | |
1677 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
|
1678 | a41b2ff2 | pbrook | |
1679 | a41b2ff2 | pbrook | return ret;
|
1680 | a41b2ff2 | pbrook | } |
1681 | a41b2ff2 | pbrook | |
1682 | a41b2ff2 | pbrook | static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) |
1683 | a41b2ff2 | pbrook | { |
1684 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1685 | a41b2ff2 | pbrook | { |
1686 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
|
1687 | a41b2ff2 | pbrook | return;
|
1688 | a41b2ff2 | pbrook | } |
1689 | a41b2ff2 | pbrook | |
1690 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
|
1691 | a41b2ff2 | pbrook | |
1692 | a41b2ff2 | pbrook | val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
|
1693 | a41b2ff2 | pbrook | |
1694 | a41b2ff2 | pbrook | s->TxConfig = val; |
1695 | a41b2ff2 | pbrook | } |
1696 | a41b2ff2 | pbrook | |
1697 | a41b2ff2 | pbrook | static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) |
1698 | a41b2ff2 | pbrook | { |
1699 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
|
1700 | 6cadb320 | bellard | |
1701 | 6cadb320 | bellard | uint32_t tc = s->TxConfig; |
1702 | 6cadb320 | bellard | tc &= 0xFFFFFF00;
|
1703 | 6cadb320 | bellard | tc |= (val & 0x000000FF);
|
1704 | 6cadb320 | bellard | rtl8139_TxConfig_write(s, tc); |
1705 | a41b2ff2 | pbrook | } |
1706 | a41b2ff2 | pbrook | |
1707 | a41b2ff2 | pbrook | static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
|
1708 | a41b2ff2 | pbrook | { |
1709 | a41b2ff2 | pbrook | uint32_t ret = s->TxConfig; |
1710 | a41b2ff2 | pbrook | |
1711 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
|
1712 | a41b2ff2 | pbrook | |
1713 | a41b2ff2 | pbrook | return ret;
|
1714 | a41b2ff2 | pbrook | } |
1715 | a41b2ff2 | pbrook | |
1716 | a41b2ff2 | pbrook | static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) |
1717 | a41b2ff2 | pbrook | { |
1718 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
|
1719 | a41b2ff2 | pbrook | |
1720 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1721 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
|
1722 | a41b2ff2 | pbrook | |
1723 | a41b2ff2 | pbrook | s->RxConfig = val; |
1724 | a41b2ff2 | pbrook | |
1725 | a41b2ff2 | pbrook | /* reset buffer size and read/write pointers */
|
1726 | a41b2ff2 | pbrook | rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); |
1727 | a41b2ff2 | pbrook | |
1728 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
|
1729 | a41b2ff2 | pbrook | } |
1730 | a41b2ff2 | pbrook | |
1731 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
|
1732 | a41b2ff2 | pbrook | { |
1733 | a41b2ff2 | pbrook | uint32_t ret = s->RxConfig; |
1734 | a41b2ff2 | pbrook | |
1735 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
|
1736 | a41b2ff2 | pbrook | |
1737 | a41b2ff2 | pbrook | return ret;
|
1738 | a41b2ff2 | pbrook | } |
1739 | a41b2ff2 | pbrook | |
1740 | 718da2b9 | bellard | static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt) |
1741 | 718da2b9 | bellard | { |
1742 | 718da2b9 | bellard | if (!size)
|
1743 | 718da2b9 | bellard | { |
1744 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
|
1745 | 718da2b9 | bellard | return;
|
1746 | 718da2b9 | bellard | } |
1747 | 718da2b9 | bellard | |
1748 | 718da2b9 | bellard | if (TxLoopBack == (s->TxConfig & TxLoopBack))
|
1749 | 718da2b9 | bellard | { |
1750 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
|
1751 | 1673ad51 | Mark McLoughlin | rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt); |
1752 | 718da2b9 | bellard | } |
1753 | 718da2b9 | bellard | else
|
1754 | 718da2b9 | bellard | { |
1755 | 1673ad51 | Mark McLoughlin | qemu_send_packet(&s->nic->nc, buf, size); |
1756 | 718da2b9 | bellard | } |
1757 | 718da2b9 | bellard | } |
1758 | 718da2b9 | bellard | |
1759 | a41b2ff2 | pbrook | static int rtl8139_transmit_one(RTL8139State *s, int descriptor) |
1760 | a41b2ff2 | pbrook | { |
1761 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1762 | a41b2ff2 | pbrook | { |
1763 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
|
1764 | 6cadb320 | bellard | descriptor)); |
1765 | a41b2ff2 | pbrook | return 0; |
1766 | a41b2ff2 | pbrook | } |
1767 | a41b2ff2 | pbrook | |
1768 | a41b2ff2 | pbrook | if (s->TxStatus[descriptor] & TxHostOwns)
|
1769 | a41b2ff2 | pbrook | { |
1770 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
|
1771 | 6cadb320 | bellard | descriptor, s->TxStatus[descriptor])); |
1772 | a41b2ff2 | pbrook | return 0; |
1773 | a41b2ff2 | pbrook | } |
1774 | a41b2ff2 | pbrook | |
1775 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
|
1776 | a41b2ff2 | pbrook | |
1777 | a41b2ff2 | pbrook | int txsize = s->TxStatus[descriptor] & 0x1fff; |
1778 | a41b2ff2 | pbrook | uint8_t txbuffer[0x2000];
|
1779 | a41b2ff2 | pbrook | |
1780 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
|
1781 | 6cadb320 | bellard | txsize, s->TxAddr[descriptor])); |
1782 | a41b2ff2 | pbrook | |
1783 | 6cadb320 | bellard | cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize); |
1784 | a41b2ff2 | pbrook | |
1785 | a41b2ff2 | pbrook | /* Mark descriptor as transferred */
|
1786 | a41b2ff2 | pbrook | s->TxStatus[descriptor] |= TxHostOwns; |
1787 | a41b2ff2 | pbrook | s->TxStatus[descriptor] |= TxStatOK; |
1788 | a41b2ff2 | pbrook | |
1789 | 718da2b9 | bellard | rtl8139_transfer_frame(s, txbuffer, txsize, 0);
|
1790 | 6cadb320 | bellard | |
1791 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
|
1792 | a41b2ff2 | pbrook | |
1793 | a41b2ff2 | pbrook | /* update interrupt */
|
1794 | a41b2ff2 | pbrook | s->IntrStatus |= TxOK; |
1795 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1796 | a41b2ff2 | pbrook | |
1797 | a41b2ff2 | pbrook | return 1; |
1798 | a41b2ff2 | pbrook | } |
1799 | a41b2ff2 | pbrook | |
1800 | 718da2b9 | bellard | /* structures and macros for task offloading */
|
1801 | 718da2b9 | bellard | typedef struct ip_header |
1802 | 718da2b9 | bellard | { |
1803 | 718da2b9 | bellard | uint8_t ip_ver_len; /* version and header length */
|
1804 | 718da2b9 | bellard | uint8_t ip_tos; /* type of service */
|
1805 | 718da2b9 | bellard | uint16_t ip_len; /* total length */
|
1806 | 718da2b9 | bellard | uint16_t ip_id; /* identification */
|
1807 | 718da2b9 | bellard | uint16_t ip_off; /* fragment offset field */
|
1808 | 718da2b9 | bellard | uint8_t ip_ttl; /* time to live */
|
1809 | 718da2b9 | bellard | uint8_t ip_p; /* protocol */
|
1810 | 718da2b9 | bellard | uint16_t ip_sum; /* checksum */
|
1811 | 718da2b9 | bellard | uint32_t ip_src,ip_dst; /* source and dest address */
|
1812 | 718da2b9 | bellard | } ip_header; |
1813 | 718da2b9 | bellard | |
1814 | 718da2b9 | bellard | #define IP_HEADER_VERSION_4 4 |
1815 | 718da2b9 | bellard | #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf) |
1816 | 718da2b9 | bellard | #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2) |
1817 | 718da2b9 | bellard | |
1818 | 718da2b9 | bellard | typedef struct tcp_header |
1819 | 718da2b9 | bellard | { |
1820 | 718da2b9 | bellard | uint16_t th_sport; /* source port */
|
1821 | 718da2b9 | bellard | uint16_t th_dport; /* destination port */
|
1822 | 718da2b9 | bellard | uint32_t th_seq; /* sequence number */
|
1823 | 718da2b9 | bellard | uint32_t th_ack; /* acknowledgement number */
|
1824 | 718da2b9 | bellard | uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
|
1825 | 718da2b9 | bellard | uint16_t th_win; /* window */
|
1826 | 718da2b9 | bellard | uint16_t th_sum; /* checksum */
|
1827 | 718da2b9 | bellard | uint16_t th_urp; /* urgent pointer */
|
1828 | 718da2b9 | bellard | } tcp_header; |
1829 | 718da2b9 | bellard | |
1830 | 718da2b9 | bellard | typedef struct udp_header |
1831 | 718da2b9 | bellard | { |
1832 | 718da2b9 | bellard | uint16_t uh_sport; /* source port */
|
1833 | 718da2b9 | bellard | uint16_t uh_dport; /* destination port */
|
1834 | 718da2b9 | bellard | uint16_t uh_ulen; /* udp length */
|
1835 | 718da2b9 | bellard | uint16_t uh_sum; /* udp checksum */
|
1836 | 718da2b9 | bellard | } udp_header; |
1837 | 718da2b9 | bellard | |
1838 | 718da2b9 | bellard | typedef struct ip_pseudo_header |
1839 | 718da2b9 | bellard | { |
1840 | 718da2b9 | bellard | uint32_t ip_src; |
1841 | 718da2b9 | bellard | uint32_t ip_dst; |
1842 | 718da2b9 | bellard | uint8_t zeros; |
1843 | 718da2b9 | bellard | uint8_t ip_proto; |
1844 | 718da2b9 | bellard | uint16_t ip_payload; |
1845 | 718da2b9 | bellard | } ip_pseudo_header; |
1846 | 718da2b9 | bellard | |
1847 | 718da2b9 | bellard | #define IP_PROTO_TCP 6 |
1848 | 718da2b9 | bellard | #define IP_PROTO_UDP 17 |
1849 | 718da2b9 | bellard | |
1850 | 718da2b9 | bellard | #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2) |
1851 | 718da2b9 | bellard | #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f) |
1852 | 718da2b9 | bellard | #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
|
1853 | 718da2b9 | bellard | |
1854 | 718da2b9 | bellard | #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
|
1855 | 718da2b9 | bellard | |
1856 | 718da2b9 | bellard | #define TCP_FLAG_FIN 0x01 |
1857 | 718da2b9 | bellard | #define TCP_FLAG_PUSH 0x08 |
1858 | 718da2b9 | bellard | |
1859 | 718da2b9 | bellard | /* produces ones' complement sum of data */
|
1860 | 718da2b9 | bellard | static uint16_t ones_complement_sum(uint8_t *data, size_t len)
|
1861 | 718da2b9 | bellard | { |
1862 | 718da2b9 | bellard | uint32_t result = 0;
|
1863 | 718da2b9 | bellard | |
1864 | 718da2b9 | bellard | for (; len > 1; data+=2, len-=2) |
1865 | 718da2b9 | bellard | { |
1866 | 718da2b9 | bellard | result += *(uint16_t*)data; |
1867 | 718da2b9 | bellard | } |
1868 | 718da2b9 | bellard | |
1869 | 718da2b9 | bellard | /* add the remainder byte */
|
1870 | 718da2b9 | bellard | if (len)
|
1871 | 718da2b9 | bellard | { |
1872 | 718da2b9 | bellard | uint8_t odd[2] = {*data, 0}; |
1873 | 718da2b9 | bellard | result += *(uint16_t*)odd; |
1874 | 718da2b9 | bellard | } |
1875 | 718da2b9 | bellard | |
1876 | 718da2b9 | bellard | while (result>>16) |
1877 | 718da2b9 | bellard | result = (result & 0xffff) + (result >> 16); |
1878 | 718da2b9 | bellard | |
1879 | 718da2b9 | bellard | return result;
|
1880 | 718da2b9 | bellard | } |
1881 | 718da2b9 | bellard | |
1882 | 718da2b9 | bellard | static uint16_t ip_checksum(void *data, size_t len) |
1883 | 718da2b9 | bellard | { |
1884 | 718da2b9 | bellard | return ~ones_complement_sum((uint8_t*)data, len);
|
1885 | 718da2b9 | bellard | } |
1886 | 718da2b9 | bellard | |
1887 | a41b2ff2 | pbrook | static int rtl8139_cplus_transmit_one(RTL8139State *s) |
1888 | a41b2ff2 | pbrook | { |
1889 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1890 | a41b2ff2 | pbrook | { |
1891 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
|
1892 | a41b2ff2 | pbrook | return 0; |
1893 | a41b2ff2 | pbrook | } |
1894 | a41b2ff2 | pbrook | |
1895 | a41b2ff2 | pbrook | if (!rtl8139_cp_transmitter_enabled(s))
|
1896 | a41b2ff2 | pbrook | { |
1897 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
|
1898 | a41b2ff2 | pbrook | return 0 ; |
1899 | a41b2ff2 | pbrook | } |
1900 | a41b2ff2 | pbrook | |
1901 | a41b2ff2 | pbrook | int descriptor = s->currCPlusTxDesc;
|
1902 | a41b2ff2 | pbrook | |
1903 | c227f099 | Anthony Liguori | target_phys_addr_t cplus_tx_ring_desc = |
1904 | a41b2ff2 | pbrook | rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); |
1905 | a41b2ff2 | pbrook | |
1906 | a41b2ff2 | pbrook | /* Normal priority ring */
|
1907 | a41b2ff2 | pbrook | cplus_tx_ring_desc += 16 * descriptor;
|
1908 | a41b2ff2 | pbrook | |
1909 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
|
1910 | 6cadb320 | bellard | descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc)); |
1911 | a41b2ff2 | pbrook | |
1912 | a41b2ff2 | pbrook | uint32_t val, txdw0,txdw1,txbufLO,txbufHI; |
1913 | a41b2ff2 | pbrook | |
1914 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
1915 | a41b2ff2 | pbrook | txdw0 = le32_to_cpu(val); |
1916 | 4ef1a3d3 | Igor V. Kovalenko | /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
|
1917 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4); |
1918 | a41b2ff2 | pbrook | txdw1 = le32_to_cpu(val); |
1919 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4); |
1920 | a41b2ff2 | pbrook | txbufLO = le32_to_cpu(val); |
1921 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4); |
1922 | a41b2ff2 | pbrook | txbufHI = le32_to_cpu(val); |
1923 | a41b2ff2 | pbrook | |
1924 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
|
1925 | a41b2ff2 | pbrook | descriptor, |
1926 | 6cadb320 | bellard | txdw0, txdw1, txbufLO, txbufHI)); |
1927 | a41b2ff2 | pbrook | |
1928 | 4ef1a3d3 | Igor V. Kovalenko | /* TODO: the following discard cast should clean clang analyzer output */
|
1929 | 4ef1a3d3 | Igor V. Kovalenko | (void)txdw1;
|
1930 | 4ef1a3d3 | Igor V. Kovalenko | |
1931 | a41b2ff2 | pbrook | /* w0 ownership flag */
|
1932 | a41b2ff2 | pbrook | #define CP_TX_OWN (1<<31) |
1933 | a41b2ff2 | pbrook | /* w0 end of ring flag */
|
1934 | a41b2ff2 | pbrook | #define CP_TX_EOR (1<<30) |
1935 | a41b2ff2 | pbrook | /* first segment of received packet flag */
|
1936 | a41b2ff2 | pbrook | #define CP_TX_FS (1<<29) |
1937 | a41b2ff2 | pbrook | /* last segment of received packet flag */
|
1938 | a41b2ff2 | pbrook | #define CP_TX_LS (1<<28) |
1939 | a41b2ff2 | pbrook | /* large send packet flag */
|
1940 | a41b2ff2 | pbrook | #define CP_TX_LGSEN (1<<27) |
1941 | 718da2b9 | bellard | /* large send MSS mask, bits 16...25 */
|
1942 | 718da2b9 | bellard | #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1) |
1943 | 718da2b9 | bellard | |
1944 | a41b2ff2 | pbrook | /* IP checksum offload flag */
|
1945 | a41b2ff2 | pbrook | #define CP_TX_IPCS (1<<18) |
1946 | a41b2ff2 | pbrook | /* UDP checksum offload flag */
|
1947 | a41b2ff2 | pbrook | #define CP_TX_UDPCS (1<<17) |
1948 | a41b2ff2 | pbrook | /* TCP checksum offload flag */
|
1949 | a41b2ff2 | pbrook | #define CP_TX_TCPCS (1<<16) |
1950 | a41b2ff2 | pbrook | |
1951 | a41b2ff2 | pbrook | /* w0 bits 0...15 : buffer size */
|
1952 | a41b2ff2 | pbrook | #define CP_TX_BUFFER_SIZE (1<<16) |
1953 | a41b2ff2 | pbrook | #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) |
1954 | a41b2ff2 | pbrook | /* w1 tag available flag */
|
1955 | a41b2ff2 | pbrook | #define CP_RX_TAGC (1<<17) |
1956 | a41b2ff2 | pbrook | /* w1 bits 0...15 : VLAN tag */
|
1957 | a41b2ff2 | pbrook | #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) |
1958 | a41b2ff2 | pbrook | /* w2 low 32bit of Rx buffer ptr */
|
1959 | a41b2ff2 | pbrook | /* w3 high 32bit of Rx buffer ptr */
|
1960 | a41b2ff2 | pbrook | |
1961 | a41b2ff2 | pbrook | /* set after transmission */
|
1962 | a41b2ff2 | pbrook | /* FIFO underrun flag */
|
1963 | a41b2ff2 | pbrook | #define CP_TX_STATUS_UNF (1<<25) |
1964 | a41b2ff2 | pbrook | /* transmit error summary flag, valid if set any of three below */
|
1965 | a41b2ff2 | pbrook | #define CP_TX_STATUS_TES (1<<23) |
1966 | a41b2ff2 | pbrook | /* out-of-window collision flag */
|
1967 | a41b2ff2 | pbrook | #define CP_TX_STATUS_OWC (1<<22) |
1968 | a41b2ff2 | pbrook | /* link failure flag */
|
1969 | a41b2ff2 | pbrook | #define CP_TX_STATUS_LNKF (1<<21) |
1970 | a41b2ff2 | pbrook | /* excessive collisions flag */
|
1971 | a41b2ff2 | pbrook | #define CP_TX_STATUS_EXC (1<<20) |
1972 | a41b2ff2 | pbrook | |
1973 | a41b2ff2 | pbrook | if (!(txdw0 & CP_TX_OWN))
|
1974 | a41b2ff2 | pbrook | { |
1975 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
|
1976 | a41b2ff2 | pbrook | return 0 ; |
1977 | a41b2ff2 | pbrook | } |
1978 | a41b2ff2 | pbrook | |
1979 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
|
1980 | 6cadb320 | bellard | |
1981 | 6cadb320 | bellard | if (txdw0 & CP_TX_FS)
|
1982 | 6cadb320 | bellard | { |
1983 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
|
1984 | 6cadb320 | bellard | |
1985 | 6cadb320 | bellard | /* reset internal buffer offset */
|
1986 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
1987 | 6cadb320 | bellard | } |
1988 | a41b2ff2 | pbrook | |
1989 | a41b2ff2 | pbrook | int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
|
1990 | c227f099 | Anthony Liguori | target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); |
1991 | a41b2ff2 | pbrook | |
1992 | 6cadb320 | bellard | /* make sure we have enough space to assemble the packet */
|
1993 | 6cadb320 | bellard | if (!s->cplus_txbuffer)
|
1994 | 6cadb320 | bellard | { |
1995 | 6cadb320 | bellard | s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; |
1996 | 2bc6f59b | Jean-Christophe DUBOIS | s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len); |
1997 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
1998 | 718da2b9 | bellard | |
1999 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
|
2000 | 6cadb320 | bellard | } |
2001 | 6cadb320 | bellard | |
2002 | 6cadb320 | bellard | while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
|
2003 | 6cadb320 | bellard | { |
2004 | 6cadb320 | bellard | s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE; |
2005 | 2137b4cc | ths | s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len); |
2006 | a41b2ff2 | pbrook | |
2007 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
|
2008 | 6cadb320 | bellard | } |
2009 | 6cadb320 | bellard | |
2010 | 6cadb320 | bellard | if (!s->cplus_txbuffer)
|
2011 | 6cadb320 | bellard | { |
2012 | 6cadb320 | bellard | /* out of memory */
|
2013 | a41b2ff2 | pbrook | |
2014 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
|
2015 | 6cadb320 | bellard | |
2016 | 6cadb320 | bellard | /* update tally counter */
|
2017 | 6cadb320 | bellard | ++s->tally_counters.TxERR; |
2018 | 6cadb320 | bellard | ++s->tally_counters.TxAbt; |
2019 | 6cadb320 | bellard | |
2020 | 6cadb320 | bellard | return 0; |
2021 | 6cadb320 | bellard | } |
2022 | 6cadb320 | bellard | |
2023 | 6cadb320 | bellard | /* append more data to the packet */
|
2024 | 6cadb320 | bellard | |
2025 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n", |
2026 | 6cadb320 | bellard | txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset)); |
2027 | 6cadb320 | bellard | |
2028 | 6cadb320 | bellard | cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); |
2029 | 6cadb320 | bellard | s->cplus_txbuffer_offset += txsize; |
2030 | 6cadb320 | bellard | |
2031 | 6cadb320 | bellard | /* seek to next Rx descriptor */
|
2032 | 6cadb320 | bellard | if (txdw0 & CP_TX_EOR)
|
2033 | 6cadb320 | bellard | { |
2034 | 6cadb320 | bellard | s->currCPlusTxDesc = 0;
|
2035 | 6cadb320 | bellard | } |
2036 | 6cadb320 | bellard | else
|
2037 | 6cadb320 | bellard | { |
2038 | 6cadb320 | bellard | ++s->currCPlusTxDesc; |
2039 | 6cadb320 | bellard | if (s->currCPlusTxDesc >= 64) |
2040 | 6cadb320 | bellard | s->currCPlusTxDesc = 0;
|
2041 | 6cadb320 | bellard | } |
2042 | a41b2ff2 | pbrook | |
2043 | a41b2ff2 | pbrook | /* transfer ownership to target */
|
2044 | a41b2ff2 | pbrook | txdw0 &= ~CP_RX_OWN; |
2045 | a41b2ff2 | pbrook | |
2046 | a41b2ff2 | pbrook | /* reset error indicator bits */
|
2047 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_UNF; |
2048 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_TES; |
2049 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_OWC; |
2050 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_LNKF; |
2051 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_EXC; |
2052 | a41b2ff2 | pbrook | |
2053 | a41b2ff2 | pbrook | /* update ring data */
|
2054 | a41b2ff2 | pbrook | val = cpu_to_le32(txdw0); |
2055 | a41b2ff2 | pbrook | cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
2056 | 4ef1a3d3 | Igor V. Kovalenko | /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
|
2057 | a41b2ff2 | pbrook | // val = cpu_to_le32(txdw1);
|
2058 | a41b2ff2 | pbrook | // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
|
2059 | a41b2ff2 | pbrook | |
2060 | 6cadb320 | bellard | /* Now decide if descriptor being processed is holding the last segment of packet */
|
2061 | 6cadb320 | bellard | if (txdw0 & CP_TX_LS)
|
2062 | a41b2ff2 | pbrook | { |
2063 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
|
2064 | 6cadb320 | bellard | |
2065 | 6cadb320 | bellard | /* can transfer fully assembled packet */
|
2066 | 6cadb320 | bellard | |
2067 | 6cadb320 | bellard | uint8_t *saved_buffer = s->cplus_txbuffer; |
2068 | 6cadb320 | bellard | int saved_size = s->cplus_txbuffer_offset;
|
2069 | 6cadb320 | bellard | int saved_buffer_len = s->cplus_txbuffer_len;
|
2070 | 6cadb320 | bellard | |
2071 | 6cadb320 | bellard | /* reset the card space to protect from recursive call */
|
2072 | 6cadb320 | bellard | s->cplus_txbuffer = NULL;
|
2073 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
2074 | 6cadb320 | bellard | s->cplus_txbuffer_len = 0;
|
2075 | 6cadb320 | bellard | |
2076 | 718da2b9 | bellard | if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
|
2077 | 6cadb320 | bellard | { |
2078 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
|
2079 | 6cadb320 | bellard | |
2080 | 6cadb320 | bellard | #define ETH_P_IP 0x0800 /* Internet Protocol packet */ |
2081 | 6cadb320 | bellard | #define ETH_HLEN 14 |
2082 | 718da2b9 | bellard | #define ETH_MTU 1500 |
2083 | 6cadb320 | bellard | |
2084 | 6cadb320 | bellard | /* ip packet header */
|
2085 | 660f11be | Blue Swirl | ip_header *ip = NULL;
|
2086 | 6cadb320 | bellard | int hlen = 0; |
2087 | 718da2b9 | bellard | uint8_t ip_protocol = 0;
|
2088 | 718da2b9 | bellard | uint16_t ip_data_len = 0;
|
2089 | 6cadb320 | bellard | |
2090 | 660f11be | Blue Swirl | uint8_t *eth_payload_data = NULL;
|
2091 | 718da2b9 | bellard | size_t eth_payload_len = 0;
|
2092 | 6cadb320 | bellard | |
2093 | 718da2b9 | bellard | int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); |
2094 | 6cadb320 | bellard | if (proto == ETH_P_IP)
|
2095 | 6cadb320 | bellard | { |
2096 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
|
2097 | 6cadb320 | bellard | |
2098 | 6cadb320 | bellard | /* not aligned */
|
2099 | 718da2b9 | bellard | eth_payload_data = saved_buffer + ETH_HLEN; |
2100 | 718da2b9 | bellard | eth_payload_len = saved_size - ETH_HLEN; |
2101 | 6cadb320 | bellard | |
2102 | 718da2b9 | bellard | ip = (ip_header*)eth_payload_data; |
2103 | 6cadb320 | bellard | |
2104 | 718da2b9 | bellard | if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
|
2105 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
|
2106 | 6cadb320 | bellard | ip = NULL;
|
2107 | 6cadb320 | bellard | } else {
|
2108 | 718da2b9 | bellard | hlen = IP_HEADER_LENGTH(ip); |
2109 | 718da2b9 | bellard | ip_protocol = ip->ip_p; |
2110 | 718da2b9 | bellard | ip_data_len = be16_to_cpu(ip->ip_len) - hlen; |
2111 | 6cadb320 | bellard | } |
2112 | 6cadb320 | bellard | } |
2113 | 6cadb320 | bellard | |
2114 | 6cadb320 | bellard | if (ip)
|
2115 | 6cadb320 | bellard | { |
2116 | 6cadb320 | bellard | if (txdw0 & CP_TX_IPCS)
|
2117 | 6cadb320 | bellard | { |
2118 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
|
2119 | 6cadb320 | bellard | |
2120 | 718da2b9 | bellard | if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */ |
2121 | 6cadb320 | bellard | /* bad packet header len */
|
2122 | 6cadb320 | bellard | /* or packet too short */
|
2123 | 6cadb320 | bellard | } |
2124 | 6cadb320 | bellard | else
|
2125 | 6cadb320 | bellard | { |
2126 | 6cadb320 | bellard | ip->ip_sum = 0;
|
2127 | 718da2b9 | bellard | ip->ip_sum = ip_checksum(ip, hlen); |
2128 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
|
2129 | 6cadb320 | bellard | } |
2130 | 6cadb320 | bellard | } |
2131 | 6cadb320 | bellard | |
2132 | 718da2b9 | bellard | if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
|
2133 | 6cadb320 | bellard | { |
2134 | 718da2b9 | bellard | #if defined (DEBUG_RTL8139)
|
2135 | 718da2b9 | bellard | int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK; |
2136 | 718da2b9 | bellard | #endif
|
2137 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
|
2138 | 718da2b9 | bellard | ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss)); |
2139 | 6cadb320 | bellard | |
2140 | 718da2b9 | bellard | int tcp_send_offset = 0; |
2141 | 718da2b9 | bellard | int send_count = 0; |
2142 | 6cadb320 | bellard | |
2143 | 6cadb320 | bellard | /* maximum IP header length is 60 bytes */
|
2144 | 6cadb320 | bellard | uint8_t saved_ip_header[60];
|
2145 | 6cadb320 | bellard | |
2146 | 718da2b9 | bellard | /* save IP header template; data area is used in tcp checksum calculation */
|
2147 | 718da2b9 | bellard | memcpy(saved_ip_header, eth_payload_data, hlen); |
2148 | 718da2b9 | bellard | |
2149 | 718da2b9 | bellard | /* a placeholder for checksum calculation routine in tcp case */
|
2150 | 718da2b9 | bellard | uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
|
2151 | 718da2b9 | bellard | // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
|
2152 | 718da2b9 | bellard | |
2153 | 718da2b9 | bellard | /* pointer to TCP header */
|
2154 | 718da2b9 | bellard | tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); |
2155 | 718da2b9 | bellard | |
2156 | 718da2b9 | bellard | int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
|
2157 | 718da2b9 | bellard | |
2158 | 718da2b9 | bellard | /* ETH_MTU = ip header len + tcp header len + payload */
|
2159 | 718da2b9 | bellard | int tcp_data_len = ip_data_len - tcp_hlen;
|
2160 | 718da2b9 | bellard | int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
|
2161 | 718da2b9 | bellard | |
2162 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
|
2163 | 718da2b9 | bellard | ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size)); |
2164 | 718da2b9 | bellard | |
2165 | 718da2b9 | bellard | /* note the cycle below overwrites IP header data,
|
2166 | 718da2b9 | bellard | but restores it from saved_ip_header before sending packet */
|
2167 | 718da2b9 | bellard | |
2168 | 718da2b9 | bellard | int is_last_frame = 0; |
2169 | 718da2b9 | bellard | |
2170 | 718da2b9 | bellard | for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size) |
2171 | 718da2b9 | bellard | { |
2172 | 718da2b9 | bellard | uint16_t chunk_size = tcp_chunk_size; |
2173 | 718da2b9 | bellard | |
2174 | 718da2b9 | bellard | /* check if this is the last frame */
|
2175 | 718da2b9 | bellard | if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
|
2176 | 718da2b9 | bellard | { |
2177 | 718da2b9 | bellard | is_last_frame = 1;
|
2178 | 718da2b9 | bellard | chunk_size = tcp_data_len - tcp_send_offset; |
2179 | 718da2b9 | bellard | } |
2180 | 718da2b9 | bellard | |
2181 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
|
2182 | 718da2b9 | bellard | |
2183 | 718da2b9 | bellard | /* add 4 TCP pseudoheader fields */
|
2184 | 718da2b9 | bellard | /* copy IP source and destination fields */
|
2185 | 718da2b9 | bellard | memcpy(data_to_checksum, saved_ip_header + 12, 8); |
2186 | 718da2b9 | bellard | |
2187 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
|
2188 | 718da2b9 | bellard | |
2189 | 718da2b9 | bellard | if (tcp_send_offset)
|
2190 | 718da2b9 | bellard | { |
2191 | 718da2b9 | bellard | memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); |
2192 | 718da2b9 | bellard | } |
2193 | 718da2b9 | bellard | |
2194 | 718da2b9 | bellard | /* keep PUSH and FIN flags only for the last frame */
|
2195 | 718da2b9 | bellard | if (!is_last_frame)
|
2196 | 718da2b9 | bellard | { |
2197 | 718da2b9 | bellard | TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN); |
2198 | 718da2b9 | bellard | } |
2199 | 6cadb320 | bellard | |
2200 | 718da2b9 | bellard | /* recalculate TCP checksum */
|
2201 | 718da2b9 | bellard | ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; |
2202 | 718da2b9 | bellard | p_tcpip_hdr->zeros = 0;
|
2203 | 718da2b9 | bellard | p_tcpip_hdr->ip_proto = IP_PROTO_TCP; |
2204 | 718da2b9 | bellard | p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); |
2205 | 718da2b9 | bellard | |
2206 | 718da2b9 | bellard | p_tcp_hdr->th_sum = 0;
|
2207 | 718da2b9 | bellard | |
2208 | 718da2b9 | bellard | int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); |
2209 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
|
2210 | 718da2b9 | bellard | |
2211 | 718da2b9 | bellard | p_tcp_hdr->th_sum = tcp_checksum; |
2212 | 718da2b9 | bellard | |
2213 | 718da2b9 | bellard | /* restore IP header */
|
2214 | 718da2b9 | bellard | memcpy(eth_payload_data, saved_ip_header, hlen); |
2215 | 718da2b9 | bellard | |
2216 | 718da2b9 | bellard | /* set IP data length and recalculate IP checksum */
|
2217 | 718da2b9 | bellard | ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); |
2218 | 718da2b9 | bellard | |
2219 | 718da2b9 | bellard | /* increment IP id for subsequent frames */
|
2220 | 718da2b9 | bellard | ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id)); |
2221 | 718da2b9 | bellard | |
2222 | 718da2b9 | bellard | ip->ip_sum = 0;
|
2223 | 718da2b9 | bellard | ip->ip_sum = ip_checksum(eth_payload_data, hlen); |
2224 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
|
2225 | 718da2b9 | bellard | |
2226 | 718da2b9 | bellard | int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
|
2227 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
|
2228 | 718da2b9 | bellard | rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
|
2229 | 718da2b9 | bellard | |
2230 | 718da2b9 | bellard | /* add transferred count to TCP sequence number */
|
2231 | 718da2b9 | bellard | p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq)); |
2232 | 718da2b9 | bellard | ++send_count; |
2233 | 718da2b9 | bellard | } |
2234 | 718da2b9 | bellard | |
2235 | 718da2b9 | bellard | /* Stop sending this frame */
|
2236 | 718da2b9 | bellard | saved_size = 0;
|
2237 | 718da2b9 | bellard | } |
2238 | 718da2b9 | bellard | else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)) |
2239 | 718da2b9 | bellard | { |
2240 | 718da2b9 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
|
2241 | 718da2b9 | bellard | |
2242 | 718da2b9 | bellard | /* maximum IP header length is 60 bytes */
|
2243 | 718da2b9 | bellard | uint8_t saved_ip_header[60];
|
2244 | 718da2b9 | bellard | memcpy(saved_ip_header, eth_payload_data, hlen); |
2245 | 718da2b9 | bellard | |
2246 | 718da2b9 | bellard | uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
|
2247 | 718da2b9 | bellard | // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
|
2248 | 6cadb320 | bellard | |
2249 | 6cadb320 | bellard | /* add 4 TCP pseudoheader fields */
|
2250 | 6cadb320 | bellard | /* copy IP source and destination fields */
|
2251 | 718da2b9 | bellard | memcpy(data_to_checksum, saved_ip_header + 12, 8); |
2252 | 6cadb320 | bellard | |
2253 | 718da2b9 | bellard | if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
|
2254 | 6cadb320 | bellard | { |
2255 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
|
2256 | 6cadb320 | bellard | |
2257 | 718da2b9 | bellard | ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; |
2258 | 718da2b9 | bellard | p_tcpip_hdr->zeros = 0;
|
2259 | 718da2b9 | bellard | p_tcpip_hdr->ip_proto = IP_PROTO_TCP; |
2260 | 718da2b9 | bellard | p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); |
2261 | 6cadb320 | bellard | |
2262 | 718da2b9 | bellard | tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
|
2263 | 6cadb320 | bellard | |
2264 | 6cadb320 | bellard | p_tcp_hdr->th_sum = 0;
|
2265 | 6cadb320 | bellard | |
2266 | 718da2b9 | bellard | int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
2267 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
|
2268 | 6cadb320 | bellard | |
2269 | 6cadb320 | bellard | p_tcp_hdr->th_sum = tcp_checksum; |
2270 | 6cadb320 | bellard | } |
2271 | 718da2b9 | bellard | else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) |
2272 | 6cadb320 | bellard | { |
2273 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
|
2274 | 6cadb320 | bellard | |
2275 | 718da2b9 | bellard | ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; |
2276 | 718da2b9 | bellard | p_udpip_hdr->zeros = 0;
|
2277 | 718da2b9 | bellard | p_udpip_hdr->ip_proto = IP_PROTO_UDP; |
2278 | 718da2b9 | bellard | p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); |
2279 | 6cadb320 | bellard | |
2280 | 718da2b9 | bellard | udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
|
2281 | 6cadb320 | bellard | |
2282 | 6cadb320 | bellard | p_udp_hdr->uh_sum = 0;
|
2283 | 6cadb320 | bellard | |
2284 | 718da2b9 | bellard | int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
2285 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
|
2286 | 6cadb320 | bellard | |
2287 | 6cadb320 | bellard | p_udp_hdr->uh_sum = udp_checksum; |
2288 | 6cadb320 | bellard | } |
2289 | 6cadb320 | bellard | |
2290 | 6cadb320 | bellard | /* restore IP header */
|
2291 | 718da2b9 | bellard | memcpy(eth_payload_data, saved_ip_header, hlen); |
2292 | 6cadb320 | bellard | } |
2293 | 6cadb320 | bellard | } |
2294 | 6cadb320 | bellard | } |
2295 | 6cadb320 | bellard | |
2296 | 6cadb320 | bellard | /* update tally counter */
|
2297 | 6cadb320 | bellard | ++s->tally_counters.TxOk; |
2298 | 6cadb320 | bellard | |
2299 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
|
2300 | 6cadb320 | bellard | |
2301 | 718da2b9 | bellard | rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
|
2302 | 6cadb320 | bellard | |
2303 | 6cadb320 | bellard | /* restore card space if there was no recursion and reset offset */
|
2304 | 6cadb320 | bellard | if (!s->cplus_txbuffer)
|
2305 | 6cadb320 | bellard | { |
2306 | 6cadb320 | bellard | s->cplus_txbuffer = saved_buffer; |
2307 | 6cadb320 | bellard | s->cplus_txbuffer_len = saved_buffer_len; |
2308 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
2309 | 6cadb320 | bellard | } |
2310 | 6cadb320 | bellard | else
|
2311 | 6cadb320 | bellard | { |
2312 | 2bc6f59b | Jean-Christophe DUBOIS | qemu_free(saved_buffer); |
2313 | 6cadb320 | bellard | } |
2314 | a41b2ff2 | pbrook | } |
2315 | a41b2ff2 | pbrook | else
|
2316 | a41b2ff2 | pbrook | { |
2317 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
|
2318 | a41b2ff2 | pbrook | } |
2319 | a41b2ff2 | pbrook | |
2320 | a41b2ff2 | pbrook | return 1; |
2321 | a41b2ff2 | pbrook | } |
2322 | a41b2ff2 | pbrook | |
2323 | a41b2ff2 | pbrook | static void rtl8139_cplus_transmit(RTL8139State *s) |
2324 | a41b2ff2 | pbrook | { |
2325 | a41b2ff2 | pbrook | int txcount = 0; |
2326 | a41b2ff2 | pbrook | |
2327 | a41b2ff2 | pbrook | while (rtl8139_cplus_transmit_one(s))
|
2328 | a41b2ff2 | pbrook | { |
2329 | a41b2ff2 | pbrook | ++txcount; |
2330 | a41b2ff2 | pbrook | } |
2331 | a41b2ff2 | pbrook | |
2332 | a41b2ff2 | pbrook | /* Mark transfer completed */
|
2333 | a41b2ff2 | pbrook | if (!txcount)
|
2334 | a41b2ff2 | pbrook | { |
2335 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
|
2336 | 6cadb320 | bellard | s->currCPlusTxDesc)); |
2337 | a41b2ff2 | pbrook | } |
2338 | a41b2ff2 | pbrook | else
|
2339 | a41b2ff2 | pbrook | { |
2340 | a41b2ff2 | pbrook | /* update interrupt status */
|
2341 | a41b2ff2 | pbrook | s->IntrStatus |= TxOK; |
2342 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2343 | a41b2ff2 | pbrook | } |
2344 | a41b2ff2 | pbrook | } |
2345 | a41b2ff2 | pbrook | |
2346 | a41b2ff2 | pbrook | static void rtl8139_transmit(RTL8139State *s) |
2347 | a41b2ff2 | pbrook | { |
2348 | a41b2ff2 | pbrook | int descriptor = s->currTxDesc, txcount = 0; |
2349 | a41b2ff2 | pbrook | |
2350 | a41b2ff2 | pbrook | /*while*/
|
2351 | a41b2ff2 | pbrook | if (rtl8139_transmit_one(s, descriptor))
|
2352 | a41b2ff2 | pbrook | { |
2353 | a41b2ff2 | pbrook | ++s->currTxDesc; |
2354 | a41b2ff2 | pbrook | s->currTxDesc %= 4;
|
2355 | a41b2ff2 | pbrook | ++txcount; |
2356 | a41b2ff2 | pbrook | } |
2357 | a41b2ff2 | pbrook | |
2358 | a41b2ff2 | pbrook | /* Mark transfer completed */
|
2359 | a41b2ff2 | pbrook | if (!txcount)
|
2360 | a41b2ff2 | pbrook | { |
2361 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
|
2362 | a41b2ff2 | pbrook | } |
2363 | a41b2ff2 | pbrook | } |
2364 | a41b2ff2 | pbrook | |
2365 | a41b2ff2 | pbrook | static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) |
2366 | a41b2ff2 | pbrook | { |
2367 | a41b2ff2 | pbrook | |
2368 | a41b2ff2 | pbrook | int descriptor = txRegOffset/4; |
2369 | 6cadb320 | bellard | |
2370 | 6cadb320 | bellard | /* handle C+ transmit mode register configuration */
|
2371 | 6cadb320 | bellard | |
2372 | 2c3891ab | aliguori | if (s->cplus_enabled)
|
2373 | 6cadb320 | bellard | { |
2374 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
|
2375 | 6cadb320 | bellard | |
2376 | 6cadb320 | bellard | /* handle Dump Tally Counters command */
|
2377 | 6cadb320 | bellard | s->TxStatus[descriptor] = val; |
2378 | 6cadb320 | bellard | |
2379 | 6cadb320 | bellard | if (descriptor == 0 && (val & 0x8)) |
2380 | 6cadb320 | bellard | { |
2381 | c227f099 | Anthony Liguori | target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); |
2382 | 6cadb320 | bellard | |
2383 | 6cadb320 | bellard | /* dump tally counters to specified memory location */
|
2384 | 6cadb320 | bellard | RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters); |
2385 | 6cadb320 | bellard | |
2386 | 6cadb320 | bellard | /* mark dump completed */
|
2387 | 6cadb320 | bellard | s->TxStatus[0] &= ~0x8; |
2388 | 6cadb320 | bellard | } |
2389 | 6cadb320 | bellard | |
2390 | 6cadb320 | bellard | return;
|
2391 | 6cadb320 | bellard | } |
2392 | 6cadb320 | bellard | |
2393 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
|
2394 | a41b2ff2 | pbrook | |
2395 | a41b2ff2 | pbrook | /* mask only reserved bits */
|
2396 | a41b2ff2 | pbrook | val &= ~0xff00c000; /* these bits are reset on write */ |
2397 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
|
2398 | a41b2ff2 | pbrook | |
2399 | a41b2ff2 | pbrook | s->TxStatus[descriptor] = val; |
2400 | a41b2ff2 | pbrook | |
2401 | a41b2ff2 | pbrook | /* attempt to start transmission */
|
2402 | a41b2ff2 | pbrook | rtl8139_transmit(s); |
2403 | a41b2ff2 | pbrook | } |
2404 | a41b2ff2 | pbrook | |
2405 | a41b2ff2 | pbrook | static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
|
2406 | a41b2ff2 | pbrook | { |
2407 | a41b2ff2 | pbrook | uint32_t ret = s->TxStatus[txRegOffset/4];
|
2408 | a41b2ff2 | pbrook | |
2409 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
|
2410 | a41b2ff2 | pbrook | |
2411 | a41b2ff2 | pbrook | return ret;
|
2412 | a41b2ff2 | pbrook | } |
2413 | a41b2ff2 | pbrook | |
2414 | a41b2ff2 | pbrook | static uint16_t rtl8139_TSAD_read(RTL8139State *s)
|
2415 | a41b2ff2 | pbrook | { |
2416 | a41b2ff2 | pbrook | uint16_t ret = 0;
|
2417 | a41b2ff2 | pbrook | |
2418 | a41b2ff2 | pbrook | /* Simulate TSAD, it is read only anyway */
|
2419 | a41b2ff2 | pbrook | |
2420 | a41b2ff2 | pbrook | ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) |
2421 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) |
2422 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) |
2423 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) |
2424 | a41b2ff2 | pbrook | |
2425 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) |
2426 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) |
2427 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) |
2428 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) |
2429 | 3b46e624 | ths | |
2430 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) |
2431 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) |
2432 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) |
2433 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) |
2434 | 3b46e624 | ths | |
2435 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) |
2436 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) |
2437 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) |
2438 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; |
2439 | 3b46e624 | ths | |
2440 | a41b2ff2 | pbrook | |
2441 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
|
2442 | a41b2ff2 | pbrook | |
2443 | a41b2ff2 | pbrook | return ret;
|
2444 | a41b2ff2 | pbrook | } |
2445 | a41b2ff2 | pbrook | |
2446 | a41b2ff2 | pbrook | static uint16_t rtl8139_CSCR_read(RTL8139State *s)
|
2447 | a41b2ff2 | pbrook | { |
2448 | a41b2ff2 | pbrook | uint16_t ret = s->CSCR; |
2449 | a41b2ff2 | pbrook | |
2450 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
|
2451 | a41b2ff2 | pbrook | |
2452 | a41b2ff2 | pbrook | return ret;
|
2453 | a41b2ff2 | pbrook | } |
2454 | a41b2ff2 | pbrook | |
2455 | a41b2ff2 | pbrook | static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) |
2456 | a41b2ff2 | pbrook | { |
2457 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
|
2458 | a41b2ff2 | pbrook | |
2459 | 290a0933 | ths | s->TxAddr[txAddrOffset/4] = val;
|
2460 | a41b2ff2 | pbrook | } |
2461 | a41b2ff2 | pbrook | |
2462 | a41b2ff2 | pbrook | static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
|
2463 | a41b2ff2 | pbrook | { |
2464 | 290a0933 | ths | uint32_t ret = s->TxAddr[txAddrOffset/4];
|
2465 | a41b2ff2 | pbrook | |
2466 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
|
2467 | a41b2ff2 | pbrook | |
2468 | a41b2ff2 | pbrook | return ret;
|
2469 | a41b2ff2 | pbrook | } |
2470 | a41b2ff2 | pbrook | |
2471 | a41b2ff2 | pbrook | static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) |
2472 | a41b2ff2 | pbrook | { |
2473 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
|
2474 | a41b2ff2 | pbrook | |
2475 | a41b2ff2 | pbrook | /* this value is off by 16 */
|
2476 | a41b2ff2 | pbrook | s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
|
2477 | a41b2ff2 | pbrook | |
2478 | 6cadb320 | bellard | DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
|
2479 | 6cadb320 | bellard | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr)); |
2480 | a41b2ff2 | pbrook | } |
2481 | a41b2ff2 | pbrook | |
2482 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
|
2483 | a41b2ff2 | pbrook | { |
2484 | a41b2ff2 | pbrook | /* this value is off by 16 */
|
2485 | a41b2ff2 | pbrook | uint32_t ret = s->RxBufPtr - 0x10;
|
2486 | a41b2ff2 | pbrook | |
2487 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
|
2488 | 6cadb320 | bellard | |
2489 | 6cadb320 | bellard | return ret;
|
2490 | 6cadb320 | bellard | } |
2491 | 6cadb320 | bellard | |
2492 | 6cadb320 | bellard | static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
|
2493 | 6cadb320 | bellard | { |
2494 | 6cadb320 | bellard | /* this value is NOT off by 16 */
|
2495 | 6cadb320 | bellard | uint32_t ret = s->RxBufAddr; |
2496 | 6cadb320 | bellard | |
2497 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
|
2498 | a41b2ff2 | pbrook | |
2499 | a41b2ff2 | pbrook | return ret;
|
2500 | a41b2ff2 | pbrook | } |
2501 | a41b2ff2 | pbrook | |
2502 | a41b2ff2 | pbrook | static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) |
2503 | a41b2ff2 | pbrook | { |
2504 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
|
2505 | a41b2ff2 | pbrook | |
2506 | a41b2ff2 | pbrook | s->RxBuf = val; |
2507 | a41b2ff2 | pbrook | |
2508 | a41b2ff2 | pbrook | /* may need to reset rxring here */
|
2509 | a41b2ff2 | pbrook | } |
2510 | a41b2ff2 | pbrook | |
2511 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
|
2512 | a41b2ff2 | pbrook | { |
2513 | a41b2ff2 | pbrook | uint32_t ret = s->RxBuf; |
2514 | a41b2ff2 | pbrook | |
2515 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
|
2516 | a41b2ff2 | pbrook | |
2517 | a41b2ff2 | pbrook | return ret;
|
2518 | a41b2ff2 | pbrook | } |
2519 | a41b2ff2 | pbrook | |
2520 | a41b2ff2 | pbrook | static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) |
2521 | a41b2ff2 | pbrook | { |
2522 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
|
2523 | a41b2ff2 | pbrook | |
2524 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
2525 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x1e00, s->IntrMask);
|
2526 | a41b2ff2 | pbrook | |
2527 | a41b2ff2 | pbrook | s->IntrMask = val; |
2528 | a41b2ff2 | pbrook | |
2529 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
2530 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2531 | 05447803 | Frediano Ziglio | |
2532 | a41b2ff2 | pbrook | } |
2533 | a41b2ff2 | pbrook | |
2534 | a41b2ff2 | pbrook | static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
|
2535 | a41b2ff2 | pbrook | { |
2536 | a41b2ff2 | pbrook | uint32_t ret = s->IntrMask; |
2537 | a41b2ff2 | pbrook | |
2538 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
|
2539 | a41b2ff2 | pbrook | |
2540 | a41b2ff2 | pbrook | return ret;
|
2541 | a41b2ff2 | pbrook | } |
2542 | a41b2ff2 | pbrook | |
2543 | a41b2ff2 | pbrook | static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) |
2544 | a41b2ff2 | pbrook | { |
2545 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
|
2546 | a41b2ff2 | pbrook | |
2547 | a41b2ff2 | pbrook | #if 0
|
2548 | a41b2ff2 | pbrook | |
2549 | a41b2ff2 | pbrook | /* writing to ISR has no effect */
|
2550 | a41b2ff2 | pbrook | |
2551 | a41b2ff2 | pbrook | return;
|
2552 | a41b2ff2 | pbrook | |
2553 | a41b2ff2 | pbrook | #else
|
2554 | a41b2ff2 | pbrook | uint16_t newStatus = s->IntrStatus & ~val; |
2555 | a41b2ff2 | pbrook | |
2556 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
2557 | a41b2ff2 | pbrook | newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
|
2558 | a41b2ff2 | pbrook | |
2559 | a41b2ff2 | pbrook | /* writing 1 to interrupt status register bit clears it */
|
2560 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
2561 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2562 | a41b2ff2 | pbrook | |
2563 | a41b2ff2 | pbrook | s->IntrStatus = newStatus; |
2564 | 05447803 | Frediano Ziglio | /*
|
2565 | 05447803 | Frediano Ziglio | * Computing if we miss an interrupt here is not that correct but
|
2566 | 05447803 | Frediano Ziglio | * considered that we should have had already an interrupt
|
2567 | 05447803 | Frediano Ziglio | * and probably emulated is slower is better to assume this resetting was
|
2568 | 05447803 | Frediano Ziglio | * done before testing on previous rtl8139_update_irq lead to IRQ loosing
|
2569 | 05447803 | Frediano Ziglio | */
|
2570 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
2571 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2572 | 05447803 | Frediano Ziglio | |
2573 | a41b2ff2 | pbrook | #endif
|
2574 | a41b2ff2 | pbrook | } |
2575 | a41b2ff2 | pbrook | |
2576 | a41b2ff2 | pbrook | static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
|
2577 | a41b2ff2 | pbrook | { |
2578 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
2579 | 05447803 | Frediano Ziglio | |
2580 | a41b2ff2 | pbrook | uint32_t ret = s->IntrStatus; |
2581 | a41b2ff2 | pbrook | |
2582 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
|
2583 | a41b2ff2 | pbrook | |
2584 | a41b2ff2 | pbrook | #if 0
|
2585 | a41b2ff2 | pbrook | |
2586 | a41b2ff2 | pbrook | /* reading ISR clears all interrupts */
|
2587 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
2588 | a41b2ff2 | pbrook | |
2589 | a41b2ff2 | pbrook | rtl8139_update_irq(s);
|
2590 | a41b2ff2 | pbrook | |
2591 | a41b2ff2 | pbrook | #endif
|
2592 | a41b2ff2 | pbrook | |
2593 | a41b2ff2 | pbrook | return ret;
|
2594 | a41b2ff2 | pbrook | } |
2595 | a41b2ff2 | pbrook | |
2596 | a41b2ff2 | pbrook | static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) |
2597 | a41b2ff2 | pbrook | { |
2598 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
|
2599 | a41b2ff2 | pbrook | |
2600 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
2601 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf000, s->MultiIntr);
|
2602 | a41b2ff2 | pbrook | |
2603 | a41b2ff2 | pbrook | s->MultiIntr = val; |
2604 | a41b2ff2 | pbrook | } |
2605 | a41b2ff2 | pbrook | |
2606 | a41b2ff2 | pbrook | static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
|
2607 | a41b2ff2 | pbrook | { |
2608 | a41b2ff2 | pbrook | uint32_t ret = s->MultiIntr; |
2609 | a41b2ff2 | pbrook | |
2610 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
|
2611 | a41b2ff2 | pbrook | |
2612 | a41b2ff2 | pbrook | return ret;
|
2613 | a41b2ff2 | pbrook | } |
2614 | a41b2ff2 | pbrook | |
2615 | a41b2ff2 | pbrook | static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) |
2616 | a41b2ff2 | pbrook | { |
2617 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2618 | a41b2ff2 | pbrook | |
2619 | a41b2ff2 | pbrook | addr &= 0xff;
|
2620 | a41b2ff2 | pbrook | |
2621 | a41b2ff2 | pbrook | switch (addr)
|
2622 | a41b2ff2 | pbrook | { |
2623 | a41b2ff2 | pbrook | case MAC0 ... MAC0+5: |
2624 | a41b2ff2 | pbrook | s->phys[addr - MAC0] = val; |
2625 | a41b2ff2 | pbrook | break;
|
2626 | a41b2ff2 | pbrook | case MAC0+6 ... MAC0+7: |
2627 | a41b2ff2 | pbrook | /* reserved */
|
2628 | a41b2ff2 | pbrook | break;
|
2629 | a41b2ff2 | pbrook | case MAR0 ... MAR0+7: |
2630 | a41b2ff2 | pbrook | s->mult[addr - MAR0] = val; |
2631 | a41b2ff2 | pbrook | break;
|
2632 | a41b2ff2 | pbrook | case ChipCmd:
|
2633 | a41b2ff2 | pbrook | rtl8139_ChipCmd_write(s, val); |
2634 | a41b2ff2 | pbrook | break;
|
2635 | a41b2ff2 | pbrook | case Cfg9346:
|
2636 | a41b2ff2 | pbrook | rtl8139_Cfg9346_write(s, val); |
2637 | a41b2ff2 | pbrook | break;
|
2638 | a41b2ff2 | pbrook | case TxConfig: /* windows driver sometimes writes using byte-lenth call */ |
2639 | a41b2ff2 | pbrook | rtl8139_TxConfig_writeb(s, val); |
2640 | a41b2ff2 | pbrook | break;
|
2641 | a41b2ff2 | pbrook | case Config0:
|
2642 | a41b2ff2 | pbrook | rtl8139_Config0_write(s, val); |
2643 | a41b2ff2 | pbrook | break;
|
2644 | a41b2ff2 | pbrook | case Config1:
|
2645 | a41b2ff2 | pbrook | rtl8139_Config1_write(s, val); |
2646 | a41b2ff2 | pbrook | break;
|
2647 | a41b2ff2 | pbrook | case Config3:
|
2648 | a41b2ff2 | pbrook | rtl8139_Config3_write(s, val); |
2649 | a41b2ff2 | pbrook | break;
|
2650 | a41b2ff2 | pbrook | case Config4:
|
2651 | a41b2ff2 | pbrook | rtl8139_Config4_write(s, val); |
2652 | a41b2ff2 | pbrook | break;
|
2653 | a41b2ff2 | pbrook | case Config5:
|
2654 | a41b2ff2 | pbrook | rtl8139_Config5_write(s, val); |
2655 | a41b2ff2 | pbrook | break;
|
2656 | a41b2ff2 | pbrook | case MediaStatus:
|
2657 | a41b2ff2 | pbrook | /* ignore */
|
2658 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
|
2659 | a41b2ff2 | pbrook | break;
|
2660 | a41b2ff2 | pbrook | |
2661 | a41b2ff2 | pbrook | case HltClk:
|
2662 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
|
2663 | a41b2ff2 | pbrook | if (val == 'R') |
2664 | a41b2ff2 | pbrook | { |
2665 | a41b2ff2 | pbrook | s->clock_enabled = 1;
|
2666 | a41b2ff2 | pbrook | } |
2667 | a41b2ff2 | pbrook | else if (val == 'H') |
2668 | a41b2ff2 | pbrook | { |
2669 | a41b2ff2 | pbrook | s->clock_enabled = 0;
|
2670 | a41b2ff2 | pbrook | } |
2671 | a41b2ff2 | pbrook | break;
|
2672 | a41b2ff2 | pbrook | |
2673 | a41b2ff2 | pbrook | case TxThresh:
|
2674 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
|
2675 | a41b2ff2 | pbrook | s->TxThresh = val; |
2676 | a41b2ff2 | pbrook | break;
|
2677 | a41b2ff2 | pbrook | |
2678 | a41b2ff2 | pbrook | case TxPoll:
|
2679 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
|
2680 | a41b2ff2 | pbrook | if (val & (1 << 7)) |
2681 | a41b2ff2 | pbrook | { |
2682 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
|
2683 | a41b2ff2 | pbrook | //rtl8139_cplus_transmit(s);
|
2684 | a41b2ff2 | pbrook | } |
2685 | a41b2ff2 | pbrook | if (val & (1 << 6)) |
2686 | a41b2ff2 | pbrook | { |
2687 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
|
2688 | a41b2ff2 | pbrook | rtl8139_cplus_transmit(s); |
2689 | a41b2ff2 | pbrook | } |
2690 | a41b2ff2 | pbrook | |
2691 | a41b2ff2 | pbrook | break;
|
2692 | a41b2ff2 | pbrook | |
2693 | a41b2ff2 | pbrook | default:
|
2694 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
|
2695 | a41b2ff2 | pbrook | break;
|
2696 | a41b2ff2 | pbrook | } |
2697 | a41b2ff2 | pbrook | } |
2698 | a41b2ff2 | pbrook | |
2699 | a41b2ff2 | pbrook | static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) |
2700 | a41b2ff2 | pbrook | { |
2701 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2702 | a41b2ff2 | pbrook | |
2703 | a41b2ff2 | pbrook | addr &= 0xfe;
|
2704 | a41b2ff2 | pbrook | |
2705 | a41b2ff2 | pbrook | switch (addr)
|
2706 | a41b2ff2 | pbrook | { |
2707 | a41b2ff2 | pbrook | case IntrMask:
|
2708 | a41b2ff2 | pbrook | rtl8139_IntrMask_write(s, val); |
2709 | a41b2ff2 | pbrook | break;
|
2710 | a41b2ff2 | pbrook | |
2711 | a41b2ff2 | pbrook | case IntrStatus:
|
2712 | a41b2ff2 | pbrook | rtl8139_IntrStatus_write(s, val); |
2713 | a41b2ff2 | pbrook | break;
|
2714 | a41b2ff2 | pbrook | |
2715 | a41b2ff2 | pbrook | case MultiIntr:
|
2716 | a41b2ff2 | pbrook | rtl8139_MultiIntr_write(s, val); |
2717 | a41b2ff2 | pbrook | break;
|
2718 | a41b2ff2 | pbrook | |
2719 | a41b2ff2 | pbrook | case RxBufPtr:
|
2720 | a41b2ff2 | pbrook | rtl8139_RxBufPtr_write(s, val); |
2721 | a41b2ff2 | pbrook | break;
|
2722 | a41b2ff2 | pbrook | |
2723 | a41b2ff2 | pbrook | case BasicModeCtrl:
|
2724 | a41b2ff2 | pbrook | rtl8139_BasicModeCtrl_write(s, val); |
2725 | a41b2ff2 | pbrook | break;
|
2726 | a41b2ff2 | pbrook | case BasicModeStatus:
|
2727 | a41b2ff2 | pbrook | rtl8139_BasicModeStatus_write(s, val); |
2728 | a41b2ff2 | pbrook | break;
|
2729 | a41b2ff2 | pbrook | case NWayAdvert:
|
2730 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
|
2731 | a41b2ff2 | pbrook | s->NWayAdvert = val; |
2732 | a41b2ff2 | pbrook | break;
|
2733 | a41b2ff2 | pbrook | case NWayLPAR:
|
2734 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
|
2735 | a41b2ff2 | pbrook | break;
|
2736 | a41b2ff2 | pbrook | case NWayExpansion:
|
2737 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
|
2738 | a41b2ff2 | pbrook | s->NWayExpansion = val; |
2739 | a41b2ff2 | pbrook | break;
|
2740 | a41b2ff2 | pbrook | |
2741 | a41b2ff2 | pbrook | case CpCmd:
|
2742 | a41b2ff2 | pbrook | rtl8139_CpCmd_write(s, val); |
2743 | a41b2ff2 | pbrook | break;
|
2744 | a41b2ff2 | pbrook | |
2745 | 6cadb320 | bellard | case IntrMitigate:
|
2746 | 6cadb320 | bellard | rtl8139_IntrMitigate_write(s, val); |
2747 | 6cadb320 | bellard | break;
|
2748 | 6cadb320 | bellard | |
2749 | a41b2ff2 | pbrook | default:
|
2750 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
|
2751 | a41b2ff2 | pbrook | |
2752 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr, val & 0xff);
|
2753 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2754 | a41b2ff2 | pbrook | break;
|
2755 | a41b2ff2 | pbrook | } |
2756 | a41b2ff2 | pbrook | } |
2757 | a41b2ff2 | pbrook | |
2758 | 05447803 | Frediano Ziglio | static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time) |
2759 | 05447803 | Frediano Ziglio | { |
2760 | 05447803 | Frediano Ziglio | int64_t pci_time, next_time; |
2761 | 05447803 | Frediano Ziglio | uint32_t low_pci; |
2762 | 05447803 | Frediano Ziglio | |
2763 | 05447803 | Frediano Ziglio | DEBUG_PRINT(("RTL8139: entered rtl8139_set_next_tctr_time\n"));
|
2764 | 05447803 | Frediano Ziglio | |
2765 | 05447803 | Frediano Ziglio | if (s->TimerExpire && current_time >= s->TimerExpire) {
|
2766 | 05447803 | Frediano Ziglio | s->IntrStatus |= PCSTimeout; |
2767 | 05447803 | Frediano Ziglio | rtl8139_update_irq(s); |
2768 | 05447803 | Frediano Ziglio | } |
2769 | 05447803 | Frediano Ziglio | |
2770 | 05447803 | Frediano Ziglio | /* Set QEMU timer only if needed that is
|
2771 | 05447803 | Frediano Ziglio | * - TimerInt <> 0 (we have a timer)
|
2772 | 05447803 | Frediano Ziglio | * - mask = 1 (we want an interrupt timer)
|
2773 | 05447803 | Frediano Ziglio | * - irq = 0 (irq is not already active)
|
2774 | 05447803 | Frediano Ziglio | * If any of above change we need to compute timer again
|
2775 | 05447803 | Frediano Ziglio | * Also we must check if timer is passed without QEMU timer
|
2776 | 05447803 | Frediano Ziglio | */
|
2777 | 05447803 | Frediano Ziglio | s->TimerExpire = 0;
|
2778 | 05447803 | Frediano Ziglio | if (!s->TimerInt) {
|
2779 | 05447803 | Frediano Ziglio | return;
|
2780 | 05447803 | Frediano Ziglio | } |
2781 | 05447803 | Frediano Ziglio | |
2782 | 05447803 | Frediano Ziglio | pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, |
2783 | 05447803 | Frediano Ziglio | get_ticks_per_sec()); |
2784 | 05447803 | Frediano Ziglio | low_pci = pci_time & 0xffffffff;
|
2785 | 05447803 | Frediano Ziglio | pci_time = pci_time - low_pci + s->TimerInt; |
2786 | 05447803 | Frediano Ziglio | if (low_pci >= s->TimerInt) {
|
2787 | 05447803 | Frediano Ziglio | pci_time += 0x100000000LL;
|
2788 | 05447803 | Frediano Ziglio | } |
2789 | 05447803 | Frediano Ziglio | next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(), |
2790 | 05447803 | Frediano Ziglio | PCI_FREQUENCY); |
2791 | 05447803 | Frediano Ziglio | s->TimerExpire = next_time; |
2792 | 05447803 | Frediano Ziglio | |
2793 | 05447803 | Frediano Ziglio | if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) { |
2794 | 05447803 | Frediano Ziglio | qemu_mod_timer(s->timer, next_time); |
2795 | 05447803 | Frediano Ziglio | } |
2796 | 05447803 | Frediano Ziglio | } |
2797 | 05447803 | Frediano Ziglio | |
2798 | a41b2ff2 | pbrook | static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) |
2799 | a41b2ff2 | pbrook | { |
2800 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2801 | a41b2ff2 | pbrook | |
2802 | a41b2ff2 | pbrook | addr &= 0xfc;
|
2803 | a41b2ff2 | pbrook | |
2804 | a41b2ff2 | pbrook | switch (addr)
|
2805 | a41b2ff2 | pbrook | { |
2806 | a41b2ff2 | pbrook | case RxMissed:
|
2807 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
|
2808 | a41b2ff2 | pbrook | s->RxMissed = 0;
|
2809 | a41b2ff2 | pbrook | break;
|
2810 | a41b2ff2 | pbrook | |
2811 | a41b2ff2 | pbrook | case TxConfig:
|
2812 | a41b2ff2 | pbrook | rtl8139_TxConfig_write(s, val); |
2813 | a41b2ff2 | pbrook | break;
|
2814 | a41b2ff2 | pbrook | |
2815 | a41b2ff2 | pbrook | case RxConfig:
|
2816 | a41b2ff2 | pbrook | rtl8139_RxConfig_write(s, val); |
2817 | a41b2ff2 | pbrook | break;
|
2818 | a41b2ff2 | pbrook | |
2819 | a41b2ff2 | pbrook | case TxStatus0 ... TxStatus0+4*4-1: |
2820 | a41b2ff2 | pbrook | rtl8139_TxStatus_write(s, addr-TxStatus0, val); |
2821 | a41b2ff2 | pbrook | break;
|
2822 | a41b2ff2 | pbrook | |
2823 | a41b2ff2 | pbrook | case TxAddr0 ... TxAddr0+4*4-1: |
2824 | a41b2ff2 | pbrook | rtl8139_TxAddr_write(s, addr-TxAddr0, val); |
2825 | a41b2ff2 | pbrook | break;
|
2826 | a41b2ff2 | pbrook | |
2827 | a41b2ff2 | pbrook | case RxBuf:
|
2828 | a41b2ff2 | pbrook | rtl8139_RxBuf_write(s, val); |
2829 | a41b2ff2 | pbrook | break;
|
2830 | a41b2ff2 | pbrook | |
2831 | a41b2ff2 | pbrook | case RxRingAddrLO:
|
2832 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
|
2833 | a41b2ff2 | pbrook | s->RxRingAddrLO = val; |
2834 | a41b2ff2 | pbrook | break;
|
2835 | a41b2ff2 | pbrook | |
2836 | a41b2ff2 | pbrook | case RxRingAddrHI:
|
2837 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
|
2838 | a41b2ff2 | pbrook | s->RxRingAddrHI = val; |
2839 | a41b2ff2 | pbrook | break;
|
2840 | a41b2ff2 | pbrook | |
2841 | 6cadb320 | bellard | case Timer:
|
2842 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
|
2843 | 6cadb320 | bellard | s->TCTR_base = qemu_get_clock(vm_clock); |
2844 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, s->TCTR_base); |
2845 | 6cadb320 | bellard | break;
|
2846 | 6cadb320 | bellard | |
2847 | 6cadb320 | bellard | case FlashReg:
|
2848 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
|
2849 | 05447803 | Frediano Ziglio | if (s->TimerInt != val) {
|
2850 | 05447803 | Frediano Ziglio | s->TimerInt = val; |
2851 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
2852 | 05447803 | Frediano Ziglio | } |
2853 | 6cadb320 | bellard | break;
|
2854 | 6cadb320 | bellard | |
2855 | a41b2ff2 | pbrook | default:
|
2856 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
|
2857 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr, val & 0xff);
|
2858 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2859 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2860 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2861 | a41b2ff2 | pbrook | break;
|
2862 | a41b2ff2 | pbrook | } |
2863 | a41b2ff2 | pbrook | } |
2864 | a41b2ff2 | pbrook | |
2865 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) |
2866 | a41b2ff2 | pbrook | { |
2867 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2868 | a41b2ff2 | pbrook | int ret;
|
2869 | a41b2ff2 | pbrook | |
2870 | a41b2ff2 | pbrook | addr &= 0xff;
|
2871 | a41b2ff2 | pbrook | |
2872 | a41b2ff2 | pbrook | switch (addr)
|
2873 | a41b2ff2 | pbrook | { |
2874 | a41b2ff2 | pbrook | case MAC0 ... MAC0+5: |
2875 | a41b2ff2 | pbrook | ret = s->phys[addr - MAC0]; |
2876 | a41b2ff2 | pbrook | break;
|
2877 | a41b2ff2 | pbrook | case MAC0+6 ... MAC0+7: |
2878 | a41b2ff2 | pbrook | ret = 0;
|
2879 | a41b2ff2 | pbrook | break;
|
2880 | a41b2ff2 | pbrook | case MAR0 ... MAR0+7: |
2881 | a41b2ff2 | pbrook | ret = s->mult[addr - MAR0]; |
2882 | a41b2ff2 | pbrook | break;
|
2883 | a41b2ff2 | pbrook | case ChipCmd:
|
2884 | a41b2ff2 | pbrook | ret = rtl8139_ChipCmd_read(s); |
2885 | a41b2ff2 | pbrook | break;
|
2886 | a41b2ff2 | pbrook | case Cfg9346:
|
2887 | a41b2ff2 | pbrook | ret = rtl8139_Cfg9346_read(s); |
2888 | a41b2ff2 | pbrook | break;
|
2889 | a41b2ff2 | pbrook | case Config0:
|
2890 | a41b2ff2 | pbrook | ret = rtl8139_Config0_read(s); |
2891 | a41b2ff2 | pbrook | break;
|
2892 | a41b2ff2 | pbrook | case Config1:
|
2893 | a41b2ff2 | pbrook | ret = rtl8139_Config1_read(s); |
2894 | a41b2ff2 | pbrook | break;
|
2895 | a41b2ff2 | pbrook | case Config3:
|
2896 | a41b2ff2 | pbrook | ret = rtl8139_Config3_read(s); |
2897 | a41b2ff2 | pbrook | break;
|
2898 | a41b2ff2 | pbrook | case Config4:
|
2899 | a41b2ff2 | pbrook | ret = rtl8139_Config4_read(s); |
2900 | a41b2ff2 | pbrook | break;
|
2901 | a41b2ff2 | pbrook | case Config5:
|
2902 | a41b2ff2 | pbrook | ret = rtl8139_Config5_read(s); |
2903 | a41b2ff2 | pbrook | break;
|
2904 | a41b2ff2 | pbrook | |
2905 | a41b2ff2 | pbrook | case MediaStatus:
|
2906 | a41b2ff2 | pbrook | ret = 0xd0;
|
2907 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
|
2908 | a41b2ff2 | pbrook | break;
|
2909 | a41b2ff2 | pbrook | |
2910 | a41b2ff2 | pbrook | case HltClk:
|
2911 | a41b2ff2 | pbrook | ret = s->clock_enabled; |
2912 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
|
2913 | a41b2ff2 | pbrook | break;
|
2914 | a41b2ff2 | pbrook | |
2915 | a41b2ff2 | pbrook | case PCIRevisionID:
|
2916 | 6cadb320 | bellard | ret = RTL8139_PCI_REVID; |
2917 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
|
2918 | a41b2ff2 | pbrook | break;
|
2919 | a41b2ff2 | pbrook | |
2920 | a41b2ff2 | pbrook | case TxThresh:
|
2921 | a41b2ff2 | pbrook | ret = s->TxThresh; |
2922 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
|
2923 | a41b2ff2 | pbrook | break;
|
2924 | a41b2ff2 | pbrook | |
2925 | a41b2ff2 | pbrook | case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ |
2926 | a41b2ff2 | pbrook | ret = s->TxConfig >> 24;
|
2927 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
|
2928 | a41b2ff2 | pbrook | break;
|
2929 | a41b2ff2 | pbrook | |
2930 | a41b2ff2 | pbrook | default:
|
2931 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
|
2932 | a41b2ff2 | pbrook | ret = 0;
|
2933 | a41b2ff2 | pbrook | break;
|
2934 | a41b2ff2 | pbrook | } |
2935 | a41b2ff2 | pbrook | |
2936 | a41b2ff2 | pbrook | return ret;
|
2937 | a41b2ff2 | pbrook | } |
2938 | a41b2ff2 | pbrook | |
2939 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) |
2940 | a41b2ff2 | pbrook | { |
2941 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2942 | a41b2ff2 | pbrook | uint32_t ret; |
2943 | a41b2ff2 | pbrook | |
2944 | a41b2ff2 | pbrook | addr &= 0xfe; /* mask lower bit */ |
2945 | a41b2ff2 | pbrook | |
2946 | a41b2ff2 | pbrook | switch (addr)
|
2947 | a41b2ff2 | pbrook | { |
2948 | a41b2ff2 | pbrook | case IntrMask:
|
2949 | a41b2ff2 | pbrook | ret = rtl8139_IntrMask_read(s); |
2950 | a41b2ff2 | pbrook | break;
|
2951 | a41b2ff2 | pbrook | |
2952 | a41b2ff2 | pbrook | case IntrStatus:
|
2953 | a41b2ff2 | pbrook | ret = rtl8139_IntrStatus_read(s); |
2954 | a41b2ff2 | pbrook | break;
|
2955 | a41b2ff2 | pbrook | |
2956 | a41b2ff2 | pbrook | case MultiIntr:
|
2957 | a41b2ff2 | pbrook | ret = rtl8139_MultiIntr_read(s); |
2958 | a41b2ff2 | pbrook | break;
|
2959 | a41b2ff2 | pbrook | |
2960 | a41b2ff2 | pbrook | case RxBufPtr:
|
2961 | a41b2ff2 | pbrook | ret = rtl8139_RxBufPtr_read(s); |
2962 | a41b2ff2 | pbrook | break;
|
2963 | a41b2ff2 | pbrook | |
2964 | 6cadb320 | bellard | case RxBufAddr:
|
2965 | 6cadb320 | bellard | ret = rtl8139_RxBufAddr_read(s); |
2966 | 6cadb320 | bellard | break;
|
2967 | 6cadb320 | bellard | |
2968 | a41b2ff2 | pbrook | case BasicModeCtrl:
|
2969 | a41b2ff2 | pbrook | ret = rtl8139_BasicModeCtrl_read(s); |
2970 | a41b2ff2 | pbrook | break;
|
2971 | a41b2ff2 | pbrook | case BasicModeStatus:
|
2972 | a41b2ff2 | pbrook | ret = rtl8139_BasicModeStatus_read(s); |
2973 | a41b2ff2 | pbrook | break;
|
2974 | a41b2ff2 | pbrook | case NWayAdvert:
|
2975 | a41b2ff2 | pbrook | ret = s->NWayAdvert; |
2976 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
|
2977 | a41b2ff2 | pbrook | break;
|
2978 | a41b2ff2 | pbrook | case NWayLPAR:
|
2979 | a41b2ff2 | pbrook | ret = s->NWayLPAR; |
2980 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
|
2981 | a41b2ff2 | pbrook | break;
|
2982 | a41b2ff2 | pbrook | case NWayExpansion:
|
2983 | a41b2ff2 | pbrook | ret = s->NWayExpansion; |
2984 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
|
2985 | a41b2ff2 | pbrook | break;
|
2986 | a41b2ff2 | pbrook | |
2987 | a41b2ff2 | pbrook | case CpCmd:
|
2988 | a41b2ff2 | pbrook | ret = rtl8139_CpCmd_read(s); |
2989 | a41b2ff2 | pbrook | break;
|
2990 | a41b2ff2 | pbrook | |
2991 | 6cadb320 | bellard | case IntrMitigate:
|
2992 | 6cadb320 | bellard | ret = rtl8139_IntrMitigate_read(s); |
2993 | 6cadb320 | bellard | break;
|
2994 | 6cadb320 | bellard | |
2995 | a41b2ff2 | pbrook | case TxSummary:
|
2996 | a41b2ff2 | pbrook | ret = rtl8139_TSAD_read(s); |
2997 | a41b2ff2 | pbrook | break;
|
2998 | a41b2ff2 | pbrook | |
2999 | a41b2ff2 | pbrook | case CSCR:
|
3000 | a41b2ff2 | pbrook | ret = rtl8139_CSCR_read(s); |
3001 | a41b2ff2 | pbrook | break;
|
3002 | a41b2ff2 | pbrook | |
3003 | a41b2ff2 | pbrook | default:
|
3004 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
|
3005 | a41b2ff2 | pbrook | |
3006 | a41b2ff2 | pbrook | ret = rtl8139_io_readb(opaque, addr); |
3007 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
3008 | a41b2ff2 | pbrook | |
3009 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
|
3010 | a41b2ff2 | pbrook | break;
|
3011 | a41b2ff2 | pbrook | } |
3012 | a41b2ff2 | pbrook | |
3013 | a41b2ff2 | pbrook | return ret;
|
3014 | a41b2ff2 | pbrook | } |
3015 | a41b2ff2 | pbrook | |
3016 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) |
3017 | a41b2ff2 | pbrook | { |
3018 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
3019 | a41b2ff2 | pbrook | uint32_t ret; |
3020 | a41b2ff2 | pbrook | |
3021 | a41b2ff2 | pbrook | addr &= 0xfc; /* also mask low 2 bits */ |
3022 | a41b2ff2 | pbrook | |
3023 | a41b2ff2 | pbrook | switch (addr)
|
3024 | a41b2ff2 | pbrook | { |
3025 | a41b2ff2 | pbrook | case RxMissed:
|
3026 | a41b2ff2 | pbrook | ret = s->RxMissed; |
3027 | a41b2ff2 | pbrook | |
3028 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
|
3029 | a41b2ff2 | pbrook | break;
|
3030 | a41b2ff2 | pbrook | |
3031 | a41b2ff2 | pbrook | case TxConfig:
|
3032 | a41b2ff2 | pbrook | ret = rtl8139_TxConfig_read(s); |
3033 | a41b2ff2 | pbrook | break;
|
3034 | a41b2ff2 | pbrook | |
3035 | a41b2ff2 | pbrook | case RxConfig:
|
3036 | a41b2ff2 | pbrook | ret = rtl8139_RxConfig_read(s); |
3037 | a41b2ff2 | pbrook | break;
|
3038 | a41b2ff2 | pbrook | |
3039 | a41b2ff2 | pbrook | case TxStatus0 ... TxStatus0+4*4-1: |
3040 | a41b2ff2 | pbrook | ret = rtl8139_TxStatus_read(s, addr-TxStatus0); |
3041 | a41b2ff2 | pbrook | break;
|
3042 | a41b2ff2 | pbrook | |
3043 | a41b2ff2 | pbrook | case TxAddr0 ... TxAddr0+4*4-1: |
3044 | a41b2ff2 | pbrook | ret = rtl8139_TxAddr_read(s, addr-TxAddr0); |
3045 | a41b2ff2 | pbrook | break;
|
3046 | a41b2ff2 | pbrook | |
3047 | a41b2ff2 | pbrook | case RxBuf:
|
3048 | a41b2ff2 | pbrook | ret = rtl8139_RxBuf_read(s); |
3049 | a41b2ff2 | pbrook | break;
|
3050 | a41b2ff2 | pbrook | |
3051 | a41b2ff2 | pbrook | case RxRingAddrLO:
|
3052 | a41b2ff2 | pbrook | ret = s->RxRingAddrLO; |
3053 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
|
3054 | a41b2ff2 | pbrook | break;
|
3055 | a41b2ff2 | pbrook | |
3056 | a41b2ff2 | pbrook | case RxRingAddrHI:
|
3057 | a41b2ff2 | pbrook | ret = s->RxRingAddrHI; |
3058 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
|
3059 | 6cadb320 | bellard | break;
|
3060 | 6cadb320 | bellard | |
3061 | 6cadb320 | bellard | case Timer:
|
3062 | 05447803 | Frediano Ziglio | ret = muldiv64(qemu_get_clock(vm_clock) - s->TCTR_base, |
3063 | 05447803 | Frediano Ziglio | PCI_FREQUENCY, get_ticks_per_sec()); |
3064 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
|
3065 | 6cadb320 | bellard | break;
|
3066 | 6cadb320 | bellard | |
3067 | 6cadb320 | bellard | case FlashReg:
|
3068 | 6cadb320 | bellard | ret = s->TimerInt; |
3069 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
|
3070 | a41b2ff2 | pbrook | break;
|
3071 | a41b2ff2 | pbrook | |
3072 | a41b2ff2 | pbrook | default:
|
3073 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
|
3074 | a41b2ff2 | pbrook | |
3075 | a41b2ff2 | pbrook | ret = rtl8139_io_readb(opaque, addr); |
3076 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
3077 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 2) << 16; |
3078 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 3) << 24; |
3079 | a41b2ff2 | pbrook | |
3080 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
|
3081 | a41b2ff2 | pbrook | break;
|
3082 | a41b2ff2 | pbrook | } |
3083 | a41b2ff2 | pbrook | |
3084 | a41b2ff2 | pbrook | return ret;
|
3085 | a41b2ff2 | pbrook | } |
3086 | a41b2ff2 | pbrook | |
3087 | a41b2ff2 | pbrook | /* */
|
3088 | a41b2ff2 | pbrook | |
3089 | a41b2ff2 | pbrook | static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
3090 | a41b2ff2 | pbrook | { |
3091 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
3092 | a41b2ff2 | pbrook | } |
3093 | a41b2ff2 | pbrook | |
3094 | a41b2ff2 | pbrook | static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
3095 | a41b2ff2 | pbrook | { |
3096 | a41b2ff2 | pbrook | rtl8139_io_writew(opaque, addr & 0xFF, val);
|
3097 | a41b2ff2 | pbrook | } |
3098 | a41b2ff2 | pbrook | |
3099 | a41b2ff2 | pbrook | static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
3100 | a41b2ff2 | pbrook | { |
3101 | a41b2ff2 | pbrook | rtl8139_io_writel(opaque, addr & 0xFF, val);
|
3102 | a41b2ff2 | pbrook | } |
3103 | a41b2ff2 | pbrook | |
3104 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr) |
3105 | a41b2ff2 | pbrook | { |
3106 | a41b2ff2 | pbrook | return rtl8139_io_readb(opaque, addr & 0xFF); |
3107 | a41b2ff2 | pbrook | } |
3108 | a41b2ff2 | pbrook | |
3109 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr) |
3110 | a41b2ff2 | pbrook | { |
3111 | a41b2ff2 | pbrook | return rtl8139_io_readw(opaque, addr & 0xFF); |
3112 | a41b2ff2 | pbrook | } |
3113 | a41b2ff2 | pbrook | |
3114 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr) |
3115 | a41b2ff2 | pbrook | { |
3116 | a41b2ff2 | pbrook | return rtl8139_io_readl(opaque, addr & 0xFF); |
3117 | a41b2ff2 | pbrook | } |
3118 | a41b2ff2 | pbrook | |
3119 | a41b2ff2 | pbrook | /* */
|
3120 | a41b2ff2 | pbrook | |
3121 | c227f099 | Anthony Liguori | static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
3122 | a41b2ff2 | pbrook | { |
3123 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
3124 | a41b2ff2 | pbrook | } |
3125 | a41b2ff2 | pbrook | |
3126 | c227f099 | Anthony Liguori | static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
3127 | a41b2ff2 | pbrook | { |
3128 | 5fedc612 | aurel32 | #ifdef TARGET_WORDS_BIGENDIAN
|
3129 | 5fedc612 | aurel32 | val = bswap16(val); |
3130 | 5fedc612 | aurel32 | #endif
|
3131 | a41b2ff2 | pbrook | rtl8139_io_writew(opaque, addr & 0xFF, val);
|
3132 | a41b2ff2 | pbrook | } |
3133 | a41b2ff2 | pbrook | |
3134 | c227f099 | Anthony Liguori | static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
3135 | a41b2ff2 | pbrook | { |
3136 | 5fedc612 | aurel32 | #ifdef TARGET_WORDS_BIGENDIAN
|
3137 | 5fedc612 | aurel32 | val = bswap32(val); |
3138 | 5fedc612 | aurel32 | #endif
|
3139 | a41b2ff2 | pbrook | rtl8139_io_writel(opaque, addr & 0xFF, val);
|
3140 | a41b2ff2 | pbrook | } |
3141 | a41b2ff2 | pbrook | |
3142 | c227f099 | Anthony Liguori | static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr) |
3143 | a41b2ff2 | pbrook | { |
3144 | a41b2ff2 | pbrook | return rtl8139_io_readb(opaque, addr & 0xFF); |
3145 | a41b2ff2 | pbrook | } |
3146 | a41b2ff2 | pbrook | |
3147 | c227f099 | Anthony Liguori | static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr) |
3148 | a41b2ff2 | pbrook | { |
3149 | 5fedc612 | aurel32 | uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
|
3150 | 5fedc612 | aurel32 | #ifdef TARGET_WORDS_BIGENDIAN
|
3151 | 5fedc612 | aurel32 | val = bswap16(val); |
3152 | 5fedc612 | aurel32 | #endif
|
3153 | 5fedc612 | aurel32 | return val;
|
3154 | a41b2ff2 | pbrook | } |
3155 | a41b2ff2 | pbrook | |
3156 | c227f099 | Anthony Liguori | static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr) |
3157 | a41b2ff2 | pbrook | { |
3158 | 5fedc612 | aurel32 | uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
|
3159 | 5fedc612 | aurel32 | #ifdef TARGET_WORDS_BIGENDIAN
|
3160 | 5fedc612 | aurel32 | val = bswap32(val); |
3161 | 5fedc612 | aurel32 | #endif
|
3162 | 5fedc612 | aurel32 | return val;
|
3163 | a41b2ff2 | pbrook | } |
3164 | a41b2ff2 | pbrook | |
3165 | 060110c3 | Juan Quintela | static int rtl8139_post_load(void *opaque, int version_id) |
3166 | a41b2ff2 | pbrook | { |
3167 | 6597ebbb | Juan Quintela | RTL8139State* s = opaque; |
3168 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
3169 | 060110c3 | Juan Quintela | if (version_id < 4) { |
3170 | 2c3891ab | aliguori | s->cplus_enabled = s->CpCmd != 0;
|
3171 | 2c3891ab | aliguori | } |
3172 | 2c3891ab | aliguori | |
3173 | a41b2ff2 | pbrook | return 0; |
3174 | a41b2ff2 | pbrook | } |
3175 | a41b2ff2 | pbrook | |
3176 | 05447803 | Frediano Ziglio | static void rtl8139_pre_save(void *opaque) |
3177 | 05447803 | Frediano Ziglio | { |
3178 | 05447803 | Frediano Ziglio | RTL8139State* s = opaque; |
3179 | 05447803 | Frediano Ziglio | int64_t current_time = qemu_get_clock(vm_clock); |
3180 | 05447803 | Frediano Ziglio | |
3181 | 05447803 | Frediano Ziglio | /* set IntrStatus correctly */
|
3182 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, current_time); |
3183 | 05447803 | Frediano Ziglio | s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, |
3184 | 05447803 | Frediano Ziglio | get_ticks_per_sec()); |
3185 | 05447803 | Frediano Ziglio | } |
3186 | 05447803 | Frediano Ziglio | |
3187 | 060110c3 | Juan Quintela | static const VMStateDescription vmstate_rtl8139 = { |
3188 | 060110c3 | Juan Quintela | .name = "rtl8139",
|
3189 | 060110c3 | Juan Quintela | .version_id = 4,
|
3190 | 060110c3 | Juan Quintela | .minimum_version_id = 3,
|
3191 | 060110c3 | Juan Quintela | .minimum_version_id_old = 3,
|
3192 | 060110c3 | Juan Quintela | .post_load = rtl8139_post_load, |
3193 | 05447803 | Frediano Ziglio | .pre_save = rtl8139_pre_save, |
3194 | 060110c3 | Juan Quintela | .fields = (VMStateField []) { |
3195 | 060110c3 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, RTL8139State), |
3196 | 060110c3 | Juan Quintela | VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
|
3197 | 060110c3 | Juan Quintela | VMSTATE_BUFFER(mult, RTL8139State), |
3198 | 060110c3 | Juan Quintela | VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
|
3199 | 060110c3 | Juan Quintela | VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
|
3200 | 060110c3 | Juan Quintela | |
3201 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBuf, RTL8139State), |
3202 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBufferSize, RTL8139State), |
3203 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBufPtr, RTL8139State), |
3204 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBufAddr, RTL8139State), |
3205 | 060110c3 | Juan Quintela | |
3206 | 060110c3 | Juan Quintela | VMSTATE_UINT16(IntrStatus, RTL8139State), |
3207 | 060110c3 | Juan Quintela | VMSTATE_UINT16(IntrMask, RTL8139State), |
3208 | 060110c3 | Juan Quintela | |
3209 | 060110c3 | Juan Quintela | VMSTATE_UINT32(TxConfig, RTL8139State), |
3210 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxConfig, RTL8139State), |
3211 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxMissed, RTL8139State), |
3212 | 060110c3 | Juan Quintela | VMSTATE_UINT16(CSCR, RTL8139State), |
3213 | 060110c3 | Juan Quintela | |
3214 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Cfg9346, RTL8139State), |
3215 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config0, RTL8139State), |
3216 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config1, RTL8139State), |
3217 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config3, RTL8139State), |
3218 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config4, RTL8139State), |
3219 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config5, RTL8139State), |
3220 | 060110c3 | Juan Quintela | |
3221 | 060110c3 | Juan Quintela | VMSTATE_UINT8(clock_enabled, RTL8139State), |
3222 | 060110c3 | Juan Quintela | VMSTATE_UINT8(bChipCmdState, RTL8139State), |
3223 | 060110c3 | Juan Quintela | |
3224 | 060110c3 | Juan Quintela | VMSTATE_UINT16(MultiIntr, RTL8139State), |
3225 | 060110c3 | Juan Quintela | |
3226 | 060110c3 | Juan Quintela | VMSTATE_UINT16(BasicModeCtrl, RTL8139State), |
3227 | 060110c3 | Juan Quintela | VMSTATE_UINT16(BasicModeStatus, RTL8139State), |
3228 | 060110c3 | Juan Quintela | VMSTATE_UINT16(NWayAdvert, RTL8139State), |
3229 | 060110c3 | Juan Quintela | VMSTATE_UINT16(NWayLPAR, RTL8139State), |
3230 | 060110c3 | Juan Quintela | VMSTATE_UINT16(NWayExpansion, RTL8139State), |
3231 | 060110c3 | Juan Quintela | |
3232 | 060110c3 | Juan Quintela | VMSTATE_UINT16(CpCmd, RTL8139State), |
3233 | 060110c3 | Juan Quintela | VMSTATE_UINT8(TxThresh, RTL8139State), |
3234 | 060110c3 | Juan Quintela | |
3235 | 060110c3 | Juan Quintela | VMSTATE_UNUSED(4),
|
3236 | 060110c3 | Juan Quintela | VMSTATE_MACADDR(conf.macaddr, RTL8139State), |
3237 | 060110c3 | Juan Quintela | VMSTATE_INT32(rtl8139_mmio_io_addr, RTL8139State), |
3238 | 060110c3 | Juan Quintela | |
3239 | 060110c3 | Juan Quintela | VMSTATE_UINT32(currTxDesc, RTL8139State), |
3240 | 060110c3 | Juan Quintela | VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), |
3241 | 060110c3 | Juan Quintela | VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), |
3242 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxRingAddrLO, RTL8139State), |
3243 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxRingAddrHI, RTL8139State), |
3244 | 060110c3 | Juan Quintela | |
3245 | 060110c3 | Juan Quintela | VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), |
3246 | 060110c3 | Juan Quintela | VMSTATE_INT32(eeprom.mode, RTL8139State), |
3247 | 060110c3 | Juan Quintela | VMSTATE_UINT32(eeprom.tick, RTL8139State), |
3248 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.address, RTL8139State), |
3249 | 060110c3 | Juan Quintela | VMSTATE_UINT16(eeprom.input, RTL8139State), |
3250 | 060110c3 | Juan Quintela | VMSTATE_UINT16(eeprom.output, RTL8139State), |
3251 | 060110c3 | Juan Quintela | |
3252 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eecs, RTL8139State), |
3253 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eesk, RTL8139State), |
3254 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eedi, RTL8139State), |
3255 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eedo, RTL8139State), |
3256 | 060110c3 | Juan Quintela | |
3257 | 060110c3 | Juan Quintela | VMSTATE_UINT32(TCTR, RTL8139State), |
3258 | 060110c3 | Juan Quintela | VMSTATE_UINT32(TimerInt, RTL8139State), |
3259 | 060110c3 | Juan Quintela | VMSTATE_INT64(TCTR_base, RTL8139State), |
3260 | 060110c3 | Juan Quintela | |
3261 | 060110c3 | Juan Quintela | VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
|
3262 | 060110c3 | Juan Quintela | vmstate_tally_counters, RTL8139TallyCounters), |
3263 | 060110c3 | Juan Quintela | |
3264 | 060110c3 | Juan Quintela | VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
|
3265 | 060110c3 | Juan Quintela | VMSTATE_END_OF_LIST() |
3266 | 060110c3 | Juan Quintela | } |
3267 | 060110c3 | Juan Quintela | }; |
3268 | 060110c3 | Juan Quintela | |
3269 | a41b2ff2 | pbrook | /***********************************************************/
|
3270 | a41b2ff2 | pbrook | /* PCI RTL8139 definitions */
|
3271 | a41b2ff2 | pbrook | |
3272 | 5fafdf24 | ths | static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num, |
3273 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
3274 | a41b2ff2 | pbrook | { |
3275 | efd6dd45 | Juan Quintela | RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev); |
3276 | a41b2ff2 | pbrook | |
3277 | a41b2ff2 | pbrook | cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr); |
3278 | a41b2ff2 | pbrook | } |
3279 | a41b2ff2 | pbrook | |
3280 | 5fafdf24 | ths | static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num, |
3281 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
3282 | a41b2ff2 | pbrook | { |
3283 | efd6dd45 | Juan Quintela | RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev); |
3284 | a41b2ff2 | pbrook | |
3285 | a41b2ff2 | pbrook | register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s); |
3286 | a41b2ff2 | pbrook | register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s); |
3287 | a41b2ff2 | pbrook | |
3288 | a41b2ff2 | pbrook | register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s); |
3289 | a41b2ff2 | pbrook | register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s); |
3290 | a41b2ff2 | pbrook | |
3291 | a41b2ff2 | pbrook | register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s); |
3292 | a41b2ff2 | pbrook | register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s); |
3293 | a41b2ff2 | pbrook | } |
3294 | a41b2ff2 | pbrook | |
3295 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = { |
3296 | a41b2ff2 | pbrook | rtl8139_mmio_readb, |
3297 | a41b2ff2 | pbrook | rtl8139_mmio_readw, |
3298 | a41b2ff2 | pbrook | rtl8139_mmio_readl, |
3299 | a41b2ff2 | pbrook | }; |
3300 | a41b2ff2 | pbrook | |
3301 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = { |
3302 | a41b2ff2 | pbrook | rtl8139_mmio_writeb, |
3303 | a41b2ff2 | pbrook | rtl8139_mmio_writew, |
3304 | a41b2ff2 | pbrook | rtl8139_mmio_writel, |
3305 | a41b2ff2 | pbrook | }; |
3306 | a41b2ff2 | pbrook | |
3307 | 6cadb320 | bellard | static void rtl8139_timer(void *opaque) |
3308 | 6cadb320 | bellard | { |
3309 | 6cadb320 | bellard | RTL8139State *s = opaque; |
3310 | 6cadb320 | bellard | |
3311 | 6cadb320 | bellard | if (!s->clock_enabled)
|
3312 | 6cadb320 | bellard | { |
3313 | 6cadb320 | bellard | DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
|
3314 | 6cadb320 | bellard | return;
|
3315 | 6cadb320 | bellard | } |
3316 | 6cadb320 | bellard | |
3317 | 05447803 | Frediano Ziglio | s->IntrStatus |= PCSTimeout; |
3318 | 05447803 | Frediano Ziglio | rtl8139_update_irq(s); |
3319 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
3320 | 6cadb320 | bellard | } |
3321 | 6cadb320 | bellard | |
3322 | 1673ad51 | Mark McLoughlin | static void rtl8139_cleanup(VLANClientState *nc) |
3323 | b946a153 | aliguori | { |
3324 | 1673ad51 | Mark McLoughlin | RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
3325 | b946a153 | aliguori | |
3326 | 1673ad51 | Mark McLoughlin | s->nic = NULL;
|
3327 | 254111ec | Gerd Hoffmann | } |
3328 | 254111ec | Gerd Hoffmann | |
3329 | 254111ec | Gerd Hoffmann | static int pci_rtl8139_uninit(PCIDevice *dev) |
3330 | 254111ec | Gerd Hoffmann | { |
3331 | 254111ec | Gerd Hoffmann | RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev); |
3332 | 254111ec | Gerd Hoffmann | |
3333 | 254111ec | Gerd Hoffmann | cpu_unregister_io_memory(s->rtl8139_mmio_io_addr); |
3334 | b946a153 | aliguori | if (s->cplus_txbuffer) {
|
3335 | b946a153 | aliguori | qemu_free(s->cplus_txbuffer); |
3336 | b946a153 | aliguori | s->cplus_txbuffer = NULL;
|
3337 | b946a153 | aliguori | } |
3338 | b946a153 | aliguori | qemu_del_timer(s->timer); |
3339 | b946a153 | aliguori | qemu_free_timer(s->timer); |
3340 | 1673ad51 | Mark McLoughlin | qemu_del_vlan_client(&s->nic->nc); |
3341 | b946a153 | aliguori | return 0; |
3342 | b946a153 | aliguori | } |
3343 | b946a153 | aliguori | |
3344 | 1673ad51 | Mark McLoughlin | static NetClientInfo net_rtl8139_info = {
|
3345 | 1673ad51 | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
3346 | 1673ad51 | Mark McLoughlin | .size = sizeof(NICState),
|
3347 | 1673ad51 | Mark McLoughlin | .can_receive = rtl8139_can_receive, |
3348 | 1673ad51 | Mark McLoughlin | .receive = rtl8139_receive, |
3349 | 1673ad51 | Mark McLoughlin | .cleanup = rtl8139_cleanup, |
3350 | 1673ad51 | Mark McLoughlin | }; |
3351 | 1673ad51 | Mark McLoughlin | |
3352 | 81a322d4 | Gerd Hoffmann | static int pci_rtl8139_init(PCIDevice *dev) |
3353 | a41b2ff2 | pbrook | { |
3354 | efd6dd45 | Juan Quintela | RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev); |
3355 | a41b2ff2 | pbrook | uint8_t *pci_conf; |
3356 | 3b46e624 | ths | |
3357 | efd6dd45 | Juan Quintela | pci_conf = s->dev.config; |
3358 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK); |
3359 | deb54399 | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139); |
3360 | 0b5b3547 | Michael S. Tsirkin | pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
|
3361 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
3362 | 0b5b3547 | Michael S. Tsirkin | pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */ |
3363 | 0b5b3547 | Michael S. Tsirkin | /* TODO: start of capability list, but no capability
|
3364 | 0b5b3547 | Michael S. Tsirkin | * list bit in status register, and offset 0xdc seems unused. */
|
3365 | 0b5b3547 | Michael S. Tsirkin | pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
|
3366 | a41b2ff2 | pbrook | |
3367 | a41b2ff2 | pbrook | /* I/O handler for memory-mapped I/O */
|
3368 | a41b2ff2 | pbrook | s->rtl8139_mmio_io_addr = |
3369 | 0b5b3547 | Michael S. Tsirkin | cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s); |
3370 | a41b2ff2 | pbrook | |
3371 | efd6dd45 | Juan Quintela | pci_register_bar(&s->dev, 0, 0x100, |
3372 | 0392a017 | Isaku Yamahata | PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map); |
3373 | a41b2ff2 | pbrook | |
3374 | efd6dd45 | Juan Quintela | pci_register_bar(&s->dev, 1, 0x100, |
3375 | 0392a017 | Isaku Yamahata | PCI_BASE_ADDRESS_SPACE_MEMORY, rtl8139_mmio_map); |
3376 | a41b2ff2 | pbrook | |
3377 | 254111ec | Gerd Hoffmann | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
3378 | c1699988 | Glauber Costa | |
3379 | 1673ad51 | Mark McLoughlin | s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, |
3380 | 1673ad51 | Mark McLoughlin | dev->qdev.info->name, dev->qdev.id, s); |
3381 | 1673ad51 | Mark McLoughlin | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
3382 | 6cadb320 | bellard | |
3383 | 6cadb320 | bellard | s->cplus_txbuffer = NULL;
|
3384 | 6cadb320 | bellard | s->cplus_txbuffer_len = 0;
|
3385 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
3386 | 3b46e624 | ths | |
3387 | 05447803 | Frediano Ziglio | s->TimerExpire = 0;
|
3388 | 6cadb320 | bellard | s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s); |
3389 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); |
3390 | 81a322d4 | Gerd Hoffmann | return 0; |
3391 | a41b2ff2 | pbrook | } |
3392 | 9d07d757 | Paul Brook | |
3393 | 0aab0d3a | Gerd Hoffmann | static PCIDeviceInfo rtl8139_info = {
|
3394 | f82de8f0 | Gerd Hoffmann | .qdev.name = "rtl8139",
|
3395 | f82de8f0 | Gerd Hoffmann | .qdev.size = sizeof(RTL8139State),
|
3396 | f82de8f0 | Gerd Hoffmann | .qdev.reset = rtl8139_reset, |
3397 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_rtl8139, |
3398 | f82de8f0 | Gerd Hoffmann | .init = pci_rtl8139_init, |
3399 | e3936fa5 | Gerd Hoffmann | .exit = pci_rtl8139_uninit, |
3400 | 8c52c8f3 | Gerd Hoffmann | .romfile = "pxe-rtl8139.bin",
|
3401 | 254111ec | Gerd Hoffmann | .qdev.props = (Property[]) { |
3402 | 254111ec | Gerd Hoffmann | DEFINE_NIC_PROPERTIES(RTL8139State, conf), |
3403 | 254111ec | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
3404 | 254111ec | Gerd Hoffmann | } |
3405 | 0aab0d3a | Gerd Hoffmann | }; |
3406 | 0aab0d3a | Gerd Hoffmann | |
3407 | 9d07d757 | Paul Brook | static void rtl8139_register_devices(void) |
3408 | 9d07d757 | Paul Brook | { |
3409 | 0aab0d3a | Gerd Hoffmann | pci_qdev_register(&rtl8139_info); |
3410 | 9d07d757 | Paul Brook | } |
3411 | 9d07d757 | Paul Brook | |
3412 | 9d07d757 | Paul Brook | device_init(rtl8139_register_devices) |