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/*

 * QEMU Cirrus VGA Emulator.

 * 

 * Copyright (c) 2004 Fabrice Bellard

 * Copyright (c) 2004 Suzu

 * 

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "vl.h"

#include "vga_int.h"

/***************************************

 *

 *  definitions

 *

 ***************************************/

#define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))

// ID

#define CIRRUS_ID_CLGD5422  (0x23<<2)

#define CIRRUS_ID_CLGD5426  (0x24<<2)

#define CIRRUS_ID_CLGD5424  (0x25<<2)

#define CIRRUS_ID_CLGD5428  (0x26<<2)

#define CIRRUS_ID_CLGD5430  (0x28<<2)

#define CIRRUS_ID_CLGD5434  (0x2A<<2)

#define CIRRUS_ID_CLGD5446  (0x2E<<2)

// sequencer 0x07

#define CIRRUS_SR7_BPP_VGA            0x00

#define CIRRUS_SR7_BPP_SVGA           0x01

#define CIRRUS_SR7_BPP_MASK           0x0e

#define CIRRUS_SR7_BPP_8              0x00

#define CIRRUS_SR7_BPP_16_DOUBLEVCLK  0x02

#define CIRRUS_SR7_BPP_24             0x04

#define CIRRUS_SR7_BPP_16             0x06

#define CIRRUS_SR7_BPP_32             0x08

#define CIRRUS_SR7_ISAADDR_MASK       0xe0

// sequencer 0x0f

#define CIRRUS_MEMSIZE_512k        0x08

#define CIRRUS_MEMSIZE_1M          0x10

#define CIRRUS_MEMSIZE_2M          0x18

#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80	// bank switching is enabled.

// sequencer 0x12

#define CIRRUS_CURSOR_SHOW         0x01

#define CIRRUS_CURSOR_HIDDENPEL    0x02

#define CIRRUS_CURSOR_LARGE        0x04	// 64x64 if set, 32x32 if clear

// sequencer 0x17

#define CIRRUS_BUSTYPE_VLBFAST   0x10

#define CIRRUS_BUSTYPE_PCI       0x20

#define CIRRUS_BUSTYPE_VLBSLOW   0x30

#define CIRRUS_BUSTYPE_ISA       0x38

#define CIRRUS_MMIO_ENABLE       0x04

#define CIRRUS_MMIO_USE_PCIADDR  0x40	// 0xb8000 if cleared.

#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80

// control 0x0b

#define CIRRUS_BANKING_DUAL             0x01

#define CIRRUS_BANKING_GRANULARITY_16K  0x20	// set:16k, clear:4k

// control 0x30

#define CIRRUS_BLTMODE_BACKWARDS        0x01

#define CIRRUS_BLTMODE_MEMSYSDEST       0x02

#define CIRRUS_BLTMODE_MEMSYSSRC        0x04

#define CIRRUS_BLTMODE_TRANSPARENTCOMP  0x08

#define CIRRUS_BLTMODE_PATTERNCOPY      0x40

#define CIRRUS_BLTMODE_COLOREXPAND      0x80

#define CIRRUS_BLTMODE_PIXELWIDTHMASK   0x30

#define CIRRUS_BLTMODE_PIXELWIDTH8      0x00

#define CIRRUS_BLTMODE_PIXELWIDTH16     0x10

#define CIRRUS_BLTMODE_PIXELWIDTH24     0x20

#define CIRRUS_BLTMODE_PIXELWIDTH32     0x30

// control 0x31

#define CIRRUS_BLT_BUSY                 0x01

#define CIRRUS_BLT_START                0x02

#define CIRRUS_BLT_RESET                0x04

#define CIRRUS_BLT_FIFOUSED             0x10

// control 0x32

#define CIRRUS_ROP_0                    0x00

#define CIRRUS_ROP_SRC_AND_DST          0x05

#define CIRRUS_ROP_NOP                  0x06

#define CIRRUS_ROP_SRC_AND_NOTDST       0x09

#define CIRRUS_ROP_NOTDST               0x0b

#define CIRRUS_ROP_SRC                  0x0d

#define CIRRUS_ROP_1                    0x0e

#define CIRRUS_ROP_NOTSRC_AND_DST       0x50

#define CIRRUS_ROP_SRC_XOR_DST          0x59

#define CIRRUS_ROP_SRC_OR_DST           0x6d

#define CIRRUS_ROP_NOTSRC_OR_NOTDST     0x90

#define CIRRUS_ROP_SRC_NOTXOR_DST       0x95

#define CIRRUS_ROP_SRC_OR_NOTDST        0xad

#define CIRRUS_ROP_NOTSRC               0xd0

#define CIRRUS_ROP_NOTSRC_OR_DST        0xd6

#define CIRRUS_ROP_NOTSRC_AND_NOTDST    0xda

// memory-mapped IO

#define CIRRUS_MMIO_BLTBGCOLOR        0x00	// dword

#define CIRRUS_MMIO_BLTFGCOLOR        0x04	// dword

#define CIRRUS_MMIO_BLTWIDTH          0x08	// word

#define CIRRUS_MMIO_BLTHEIGHT         0x0a	// word

#define CIRRUS_MMIO_BLTDESTPITCH      0x0c	// word

#define CIRRUS_MMIO_BLTSRCPITCH       0x0e	// word

#define CIRRUS_MMIO_BLTDESTADDR       0x10	// dword

#define CIRRUS_MMIO_BLTSRCADDR        0x14	// dword

#define CIRRUS_MMIO_BLTWRITEMASK      0x17	// byte

#define CIRRUS_MMIO_BLTMODE           0x18	// byte

#define CIRRUS_MMIO_BLTROP            0x1a	// byte

#define CIRRUS_MMIO_BLTMODEEXT        0x1b	// byte

#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c	// word?

#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20	// word?

#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24	// word

#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26	// word

#define CIRRUS_MMIO_LINEARDRAW_END_X  0x28	// word

#define CIRRUS_MMIO_LINEARDRAW_END_Y  0x2a	// word

#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c	// byte

#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d	// byte

#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e	// byte

#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f	// byte

#define CIRRUS_MMIO_BRESENHAM_K1      0x30	// word

#define CIRRUS_MMIO_BRESENHAM_K3      0x32	// word

#define CIRRUS_MMIO_BRESENHAM_ERROR   0x34	// word

#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36	// word

#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38	// byte

#define CIRRUS_MMIO_LINEDRAW_MODE     0x39	// byte

#define CIRRUS_MMIO_BLTSTATUS         0x40	// byte

// PCI 0x00: vendor, 0x02: device

#define PCI_VENDOR_CIRRUS             0x1013

#define PCI_DEVICE_CLGD5430           0x00a0	// CLGD5430 or CLGD5440

#define PCI_DEVICE_CLGD5434           0x00a8

#define PCI_DEVICE_CLGD5436           0x00ac

#define PCI_DEVICE_CLGD5446           0x00b8

#define PCI_DEVICE_CLGD5462           0x00d0

#define PCI_DEVICE_CLGD5465           0x00d6

// PCI 0x04: command(word), 0x06(word): status

#define PCI_COMMAND_IOACCESS                0x0001

#define PCI_COMMAND_MEMACCESS               0x0002

#define PCI_COMMAND_BUSMASTER               0x0004

#define PCI_COMMAND_SPECIALCYCLE            0x0008

#define PCI_COMMAND_MEMWRITEINVALID         0x0010

#define PCI_COMMAND_PALETTESNOOPING         0x0020

#define PCI_COMMAND_PARITYDETECTION         0x0040

#define PCI_COMMAND_ADDRESSDATASTEPPING     0x0080

#define PCI_COMMAND_SERR                    0x0100

#define PCI_COMMAND_BACKTOBACKTRANS         0x0200

// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)

#define PCI_CLASS_BASE_DISPLAY        0x03

// PCI 0x08, 0x00ff0000

#define PCI_CLASS_SUB_VGA             0x00

// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)

#define PCI_CLASS_HEADERTYPE_00h  0x00

// 0x10-0x3f (headertype 00h)

// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers

//   0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)

#define PCI_MAP_MEM                 0x0

#define PCI_MAP_IO                  0x1

#define PCI_MAP_MEM_ADDR_MASK       (~0xf)

#define PCI_MAP_IO_ADDR_MASK        (~0x3)

#define PCI_MAP_MEMFLAGS_32BIT      0x0

#define PCI_MAP_MEMFLAGS_32BIT_1M   0x1

#define PCI_MAP_MEMFLAGS_64BIT      0x4

#define PCI_MAP_MEMFLAGS_CACHEABLE  0x8

// PCI 0x28: cardbus CIS pointer

// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id

// PCI 0x30: expansion ROM base address

#define PCI_ROMBIOS_ENABLED         0x1

// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer

// PCI 0x38: reserved

// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat

#define CIRRUS_PNPMMIO_SIZE         0x800

/* I/O and memory hook */

#define CIRRUS_HOOK_NOT_HANDLED 0

#define CIRRUS_HOOK_HANDLED 1

typedef void (*cirrus_bitblt_rop_t) (uint8_t * dst, const uint8_t * src,

				     int dstpitch, int srcpitch,

				     int bltwidth, int bltheight);

typedef void (*cirrus_bitblt_handler_t) (void *opaque);

typedef struct CirrusVGAState {

    /* XXX: we use the anonymous struct/union gcc 3.x extension */

    struct VGAState;

    int cirrus_linear_io_addr;

    int cirrus_mmio_io_addr;

    uint32_t cirrus_addr_mask;

    uint8_t cirrus_shadow_gr0;

    uint8_t cirrus_shadow_gr1;

    uint8_t cirrus_hidden_dac_lockindex;

    uint8_t cirrus_hidden_dac_data;

    uint32_t cirrus_bank_base[2];

    uint32_t cirrus_bank_limit[2];

    uint8_t cirrus_hidden_palette[48];

    uint32_t cirrus_hw_cursor_x;

    uint32_t cirrus_hw_cursor_y;

    int cirrus_blt_pixelwidth;

    int cirrus_blt_width;

    int cirrus_blt_height;

    int cirrus_blt_dstpitch;

    int cirrus_blt_srcpitch;

    uint32_t cirrus_blt_dstaddr;

    uint32_t cirrus_blt_srcaddr;

    uint8_t cirrus_blt_mode;

    cirrus_bitblt_rop_t cirrus_rop;

#define CIRRUS_BLTBUFSIZE 256

    uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];

    uint8_t *cirrus_srcptr;

    uint8_t *cirrus_srcptr_end;

    uint32_t cirrus_srccounter;

    uint8_t *cirrus_dstptr;

    uint8_t *cirrus_dstptr_end;

    uint32_t cirrus_dstcounter;

    cirrus_bitblt_handler_t cirrus_blt_handler;

    int cirrus_blt_horz_counter;

} CirrusVGAState;

typedef struct PCICirrusVGAState {

    PCIDevice dev;

    CirrusVGAState cirrus_vga;

} PCICirrusVGAState;

/***************************************

 *

 *  prototypes.

 *

 ***************************************/

static void cirrus_bitblt_reset(CirrusVGAState * s);

/***************************************

 *

 *  raster operations

 *

 ***************************************/

#define IMPLEMENT_FORWARD_BITBLT(name,opline) \

  static void \

  cirrus_bitblt_rop_fwd_##name( \

    uint8_t *dst,const uint8_t *src, \

    int dstpitch,int srcpitch, \

    int bltwidth,int bltheight) \

  { \

    int x,y; \

    dstpitch -= bltwidth; \

    srcpitch -= bltwidth; \

    for (y = 0; y < bltheight; y++) { \

      for (x = 0; x < bltwidth; x++) { \

        opline; \

        dst++; \

        src++; \

        } \

      dst += dstpitch; \

      src += srcpitch; \

      } \

    }

#define IMPLEMENT_BACKWARD_BITBLT(name,opline) \

  static void \

  cirrus_bitblt_rop_bkwd_##name( \

    uint8_t *dst,const uint8_t *src, \

    int dstpitch,int srcpitch, \

    int bltwidth,int bltheight) \

  { \

    int x,y; \

    dstpitch += bltwidth; \

    srcpitch += bltwidth; \

    for (y = 0; y < bltheight; y++) { \

      for (x = 0; x < bltwidth; x++) { \

        opline; \

        dst--; \

        src--; \

      } \

      dst += dstpitch; \

      src += srcpitch; \

    } \

  }

IMPLEMENT_FORWARD_BITBLT(0, *dst = 0)

    IMPLEMENT_FORWARD_BITBLT(src_and_dst, *dst = (*src) & (*dst))

    IMPLEMENT_FORWARD_BITBLT(nop, (void) 0)

    IMPLEMENT_FORWARD_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst)))

    IMPLEMENT_FORWARD_BITBLT(notdst, *dst = ~(*dst))

    IMPLEMENT_FORWARD_BITBLT(src, *dst = *src)

    IMPLEMENT_FORWARD_BITBLT(1, *dst = 0xff)

    IMPLEMENT_FORWARD_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst))

    IMPLEMENT_FORWARD_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst))

    IMPLEMENT_FORWARD_BITBLT(src_or_dst, *dst = (*src) | (*dst))

    IMPLEMENT_FORWARD_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst)))

    IMPLEMENT_FORWARD_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst)))

    IMPLEMENT_FORWARD_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst)))

    IMPLEMENT_FORWARD_BITBLT(notsrc, *dst = (~(*src)))

    IMPLEMENT_FORWARD_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst))

    IMPLEMENT_FORWARD_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst)))

    IMPLEMENT_BACKWARD_BITBLT(0, *dst = 0)

    IMPLEMENT_BACKWARD_BITBLT(src_and_dst, *dst = (*src) & (*dst))

    IMPLEMENT_BACKWARD_BITBLT(nop, (void) 0)

    IMPLEMENT_BACKWARD_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst)))

    IMPLEMENT_BACKWARD_BITBLT(notdst, *dst = ~(*dst))

    IMPLEMENT_BACKWARD_BITBLT(src, *dst = *src)

    IMPLEMENT_BACKWARD_BITBLT(1, *dst = 0xff)

    IMPLEMENT_BACKWARD_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst))

    IMPLEMENT_BACKWARD_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst))

    IMPLEMENT_BACKWARD_BITBLT(src_or_dst, *dst = (*src) | (*dst))

    IMPLEMENT_BACKWARD_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst)))

    IMPLEMENT_BACKWARD_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst)))

    IMPLEMENT_BACKWARD_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst)))

    IMPLEMENT_BACKWARD_BITBLT(notsrc, *dst = (~(*src)))

    IMPLEMENT_BACKWARD_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst))

    IMPLEMENT_BACKWARD_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst)))

static cirrus_bitblt_rop_t cirrus_get_fwd_rop_handler(uint8_t rop)

{

    cirrus_bitblt_rop_t rop_handler = cirrus_bitblt_rop_fwd_nop;

    switch (rop) {

    case CIRRUS_ROP_0:

	rop_handler = cirrus_bitblt_rop_fwd_0;

	break;

    case CIRRUS_ROP_SRC_AND_DST:

	rop_handler = cirrus_bitblt_rop_fwd_src_and_dst;

	break;

    case CIRRUS_ROP_NOP:

	rop_handler = cirrus_bitblt_rop_fwd_nop;

	break;

    case CIRRUS_ROP_SRC_AND_NOTDST:

	rop_handler = cirrus_bitblt_rop_fwd_src_and_notdst;

	break;

    case CIRRUS_ROP_NOTDST:

	rop_handler = cirrus_bitblt_rop_fwd_notdst;

	break;

    case CIRRUS_ROP_SRC:

	rop_handler = cirrus_bitblt_rop_fwd_src;

	break;

    case CIRRUS_ROP_1:

	rop_handler = cirrus_bitblt_rop_fwd_1;

	break;

    case CIRRUS_ROP_NOTSRC_AND_DST:

	rop_handler = cirrus_bitblt_rop_fwd_notsrc_and_dst;

	break;

    case CIRRUS_ROP_SRC_XOR_DST:

	rop_handler = cirrus_bitblt_rop_fwd_src_xor_dst;

	break;

    case CIRRUS_ROP_SRC_OR_DST:

	rop_handler = cirrus_bitblt_rop_fwd_src_or_dst;

	break;

    case CIRRUS_ROP_NOTSRC_OR_NOTDST:

	rop_handler = cirrus_bitblt_rop_fwd_notsrc_or_notdst;

	break;

    case CIRRUS_ROP_SRC_NOTXOR_DST:

	rop_handler = cirrus_bitblt_rop_fwd_src_notxor_dst;

	break;

    case CIRRUS_ROP_SRC_OR_NOTDST:

	rop_handler = cirrus_bitblt_rop_fwd_src_or_notdst;

	break;

    case CIRRUS_ROP_NOTSRC:

	rop_handler = cirrus_bitblt_rop_fwd_notsrc;

	break;

    case CIRRUS_ROP_NOTSRC_OR_DST:

	rop_handler = cirrus_bitblt_rop_fwd_notsrc_or_dst;

	break;

    case CIRRUS_ROP_NOTSRC_AND_NOTDST:

	rop_handler = cirrus_bitblt_rop_fwd_notsrc_and_notdst;

	break;

    default:

#ifdef DEBUG_CIRRUS

	printf("unknown ROP %02x\n", rop);

#endif

	break;

    }

    return rop_handler;

}

static cirrus_bitblt_rop_t cirrus_get_bkwd_rop_handler(uint8_t rop)

{

    cirrus_bitblt_rop_t rop_handler = cirrus_bitblt_rop_bkwd_nop;

    switch (rop) {

    case CIRRUS_ROP_0:

	rop_handler = cirrus_bitblt_rop_bkwd_0;

	break;

    case CIRRUS_ROP_SRC_AND_DST:

	rop_handler = cirrus_bitblt_rop_bkwd_src_and_dst;

	break;

    case CIRRUS_ROP_NOP:

	rop_handler = cirrus_bitblt_rop_bkwd_nop;

	break;

    case CIRRUS_ROP_SRC_AND_NOTDST:

	rop_handler = cirrus_bitblt_rop_bkwd_src_and_notdst;

	break;

    case CIRRUS_ROP_NOTDST:

	rop_handler = cirrus_bitblt_rop_bkwd_notdst;

	break;

    case CIRRUS_ROP_SRC:

	rop_handler = cirrus_bitblt_rop_bkwd_src;

	break;

    case CIRRUS_ROP_1:

	rop_handler = cirrus_bitblt_rop_bkwd_1;

	break;

    case CIRRUS_ROP_NOTSRC_AND_DST:

	rop_handler = cirrus_bitblt_rop_bkwd_notsrc_and_dst;

	break;

    case CIRRUS_ROP_SRC_XOR_DST:

	rop_handler = cirrus_bitblt_rop_bkwd_src_xor_dst;

	break;

    case CIRRUS_ROP_SRC_OR_DST:

	rop_handler = cirrus_bitblt_rop_bkwd_src_or_dst;

	break;

    case CIRRUS_ROP_NOTSRC_OR_NOTDST:

	rop_handler = cirrus_bitblt_rop_bkwd_notsrc_or_notdst;

	break;

    case CIRRUS_ROP_SRC_NOTXOR_DST:

	rop_handler = cirrus_bitblt_rop_bkwd_src_notxor_dst;

	break;

    case CIRRUS_ROP_SRC_OR_NOTDST:

	rop_handler = cirrus_bitblt_rop_bkwd_src_or_notdst;

	break;

    case CIRRUS_ROP_NOTSRC:

	rop_handler = cirrus_bitblt_rop_bkwd_notsrc;

	break;

    case CIRRUS_ROP_NOTSRC_OR_DST:

	rop_handler = cirrus_bitblt_rop_bkwd_notsrc_or_dst;

	break;

    case CIRRUS_ROP_NOTSRC_AND_NOTDST:

	rop_handler = cirrus_bitblt_rop_bkwd_notsrc_and_notdst;

	break;

    default:

#ifdef DEBUG_CIRRUS

	printf("unknown ROP %02x\n", rop);

#endif

	break;

    }

    return rop_handler;

}

/***************************************

 *

 *  color expansion

 *

 ***************************************/

static void

cirrus_colorexpand_8(CirrusVGAState * s, uint8_t * dst,

		     const uint8_t * src, int count)

{

    int x;

    uint8_t colors[2];

    unsigned bits;

    unsigned bitmask;

    int srcskipleft = 0;

    colors[0] = s->gr[0x00];

    colors[1] = s->gr[0x01];

    bitmask = 0x80 >> srcskipleft;

    bits = *src++;

    for (x = 0; x < count; x++) {

	if ((bitmask & 0xff) == 0) {

	    bitmask = 0x80;

	    bits = *src++;

	}

	*dst++ = colors[!!(bits & bitmask)];

	bitmask >>= 1;

    }

}

static void

cirrus_colorexpand_16(CirrusVGAState * s, uint8_t * dst,

		      const uint8_t * src, int count)

{

    int x;

    uint8_t colors[2][2];

    unsigned bits;

    unsigned bitmask;

    unsigned index;

    int srcskipleft = 0;

    colors[0][0] = s->gr[0x00];

    colors[0][1] = s->gr[0x10];

    colors[1][0] = s->gr[0x01];

    colors[1][1] = s->gr[0x11];

    bitmask = 0x80 >> srcskipleft;

    bits = *src++;

    for (x = 0; x < count; x++) {

	if ((bitmask & 0xff) == 0) {

	    bitmask = 0x80;

	    bits = *src++;

	}

	index = !!(bits & bitmask);

	*dst++ = colors[index][0];

	*dst++ = colors[index][1];

	bitmask >>= 1;

    }

}

static void

cirrus_colorexpand_24(CirrusVGAState * s, uint8_t * dst,

		      const uint8_t * src, int count)

{

    int x;

    uint8_t colors[2][3];

    unsigned bits;

    unsigned bitmask;

    unsigned index;

    int srcskipleft = 0;

    colors[0][0] = s->gr[0x00];

    colors[0][1] = s->gr[0x10];

    colors[0][2] = s->gr[0x12];

    colors[1][0] = s->gr[0x01];

    colors[1][1] = s->gr[0x11];

    colors[1][2] = s->gr[0x13];

    bitmask = 0x80 << srcskipleft;

    bits = *src++;

    for (x = 0; x < count; x++) {

	if ((bitmask & 0xff) == 0) {

	    bitmask = 0x80;

	    bits = *src++;

	}

	index = !!(bits & bitmask);

	*dst++ = colors[index][0];

	*dst++ = colors[index][1];

	*dst++ = colors[index][2];

	bitmask >>= 1;

    }

}

static void

cirrus_colorexpand_32(CirrusVGAState * s, uint8_t * dst,

		      const uint8_t * src, int count)

{

    int x;

    uint8_t colors[2][4];

    unsigned bits;

    unsigned bitmask;

    unsigned index;

    int srcskipleft = 0;

    colors[0][0] = s->gr[0x00];

    colors[0][1] = s->gr[0x10];

    colors[0][2] = s->gr[0x12];

    colors[0][3] = s->gr[0x14];

    colors[1][0] = s->gr[0x01];

    colors[1][1] = s->gr[0x11];

    colors[1][2] = s->gr[0x13];

    colors[1][3] = s->gr[0x15];

    bitmask = 0x80 << srcskipleft;

    bits = *src++;

    for (x = 0; x < count; x++) {

	if ((bitmask & 0xff) == 0) {

	    bitmask = 0x80;

	    bits = *src++;

	}

	index = !!(bits & bitmask);

	*dst++ = colors[index][0];

	*dst++ = colors[index][1];

	*dst++ = colors[index][2];

	*dst++ = colors[index][3];

	bitmask >>= 1;

    }

}

static void

cirrus_colorexpand(CirrusVGAState * s, uint8_t * dst, const uint8_t * src,

		   int count)

{

    switch (s->cirrus_blt_pixelwidth) {

    case 1:

	cirrus_colorexpand_8(s, dst, src, count);

	break;

    case 2:

	cirrus_colorexpand_16(s, dst, src, count);

	break;

    case 3:

	cirrus_colorexpand_24(s, dst, src, count);

	break;

    case 4:

	cirrus_colorexpand_32(s, dst, src, count);

	break;

    default:

#ifdef DEBUG_CIRRUS

	printf("cirrus: COLOREXPAND pixelwidth %d - unimplemented\n",

	       s->cirrus_blt_pixelwidth);

#endif

	break;

    }

}

static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,

				     int off_pitch, int bytesperline,

				     int lines)

{

    int y;

    int off_cur;

    int off_cur_end;

    for (y = 0; y < lines; y++) {

	off_cur = off_begin;

	off_cur_end = off_cur + bytesperline;

	off_cur &= TARGET_PAGE_MASK;

	while (off_cur < off_cur_end) {

	    cpu_physical_memory_set_dirty(s->vram_offset + off_cur);

	    off_cur += TARGET_PAGE_SIZE;

	}

	off_begin += off_pitch;

    }

}

static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,

					    const uint8_t * src)

{

    uint8_t work_colorexp[256];

    uint8_t *dst;

    uint8_t *dstc;

    int x, y;

    int tilewidth, tileheight;

    int patternbytes = s->cirrus_blt_pixelwidth * 8;

    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {

	cirrus_colorexpand(s, work_colorexp, src, 8 * 8);

	src = work_colorexp;

	s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_COLOREXPAND;

    }

    if (s->cirrus_blt_mode & ~CIRRUS_BLTMODE_PATTERNCOPY) {

#ifdef DEBUG_CIRRUS

	printf("cirrus: blt mode %02x (pattercopy) - unimplemented\n",

	       s->cirrus_blt_mode);

#endif

	return 0;

    }

    dst = s->vram_ptr + s->cirrus_blt_dstaddr;

    for (y = 0; y < s->cirrus_blt_height; y += 8) {

	dstc = dst;

	tileheight = qemu_MIN(8, s->cirrus_blt_height - y);

	for (x = 0; x < s->cirrus_blt_width; x += patternbytes) {

	    tilewidth = qemu_MIN(patternbytes, s->cirrus_blt_width - x);

	    (*s->cirrus_rop) (dstc, src,

			      s->cirrus_blt_dstpitch, patternbytes,

			      tilewidth, tileheight);

	    dstc += patternbytes;

	}

	dst += s->cirrus_blt_dstpitch * 8;

    }

    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,

			     s->cirrus_blt_dstpitch, s->cirrus_blt_width,

			     s->cirrus_blt_height);

    return 1;

}

/***************************************

 *

 *  bitblt (video-to-video)

 *

 ***************************************/

static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)

{

    return cirrus_bitblt_common_patterncopy(s,

					    s->vram_ptr +

					    s->cirrus_blt_srcaddr);

}

static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)

{

    if ((s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) != 0) {

#ifdef DEBUG_CIRRUS

	printf("cirrus: CIRRUS_BLTMODE_COLOREXPAND - unimplemented\n");

#endif

	return 0;

    }

    if ((s->cirrus_blt_mode & (~CIRRUS_BLTMODE_BACKWARDS)) != 0) {

#ifdef DEBUG_CIRRUS

	printf("cirrus: blt mode %02x - unimplemented\n",

	       s->cirrus_blt_mode);

#endif

	return 0;

    }

    (*s->cirrus_rop) (s->vram_ptr + s->cirrus_blt_dstaddr,

		      s->vram_ptr + s->cirrus_blt_srcaddr,

		      s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,

		      s->cirrus_blt_width, s->cirrus_blt_height);

    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,

			     s->cirrus_blt_dstpitch, s->cirrus_blt_width,

			     s->cirrus_blt_height);

    return 1;

}

/***************************************

 *

 *  bitblt (cpu-to-video)

 *

 ***************************************/

static void cirrus_bitblt_cputovideo_patterncopy(void *opaque)

{

    CirrusVGAState *s = (CirrusVGAState *) opaque;

    int data_count;

    data_count = s->cirrus_srcptr - &s->cirrus_bltbuf[0];

    if (data_count > 0) {

	if (data_count != s->cirrus_srccounter) {

#ifdef DEBUG_CIRRUS

	    printf("cirrus: internal error\n");

#endif

	} else {

	    cirrus_bitblt_common_patterncopy(s, &s->cirrus_bltbuf[0]);

	}

	cirrus_bitblt_reset(s);

    }

}

static void cirrus_bitblt_cputovideo_copy(void *opaque)

{

    CirrusVGAState *s = (CirrusVGAState *) opaque;

    int data_count;

    int data_avail;

    uint8_t work_colorexp[256];

    uint8_t *src_ptr = NULL;

    int src_avail = 0;

    int src_processing;

    int src_linepad = 0;

    if (s->cirrus_blt_height <= 0) {

	s->cirrus_srcptr = s->cirrus_srcptr_end;

	return;

    }

    s->cirrus_srcptr = &s->cirrus_bltbuf[0];

    while (1) {

	/* get BLT source. */

	if (src_avail <= 0) {

	    data_count = s->cirrus_srcptr_end - s->cirrus_srcptr;

	    if (data_count <= 0)

		break;

	    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {

		if (s->cirrus_blt_mode & ~CIRRUS_BLTMODE_COLOREXPAND) {

#ifdef DEBUG_CIRRUS

		    printf("cirrus: unsupported\n");

#endif

		    cirrus_bitblt_reset(s);

		    return;

		}

		data_avail = qemu_MIN(data_count, 256 / 32);

		cirrus_colorexpand(s, work_colorexp, s->cirrus_srcptr,

				   data_avail * 8);

		src_ptr = &work_colorexp[0];

		src_avail = data_avail * 8 * s->cirrus_blt_pixelwidth;

		s->cirrus_srcptr += data_avail;

		src_linepad =

		    ((s->cirrus_blt_width + 7) / 8) * 8 -

		    s->cirrus_blt_width;

		src_linepad *= s->cirrus_blt_pixelwidth;

	    } else {

		if (s->cirrus_blt_mode != 0) {

#ifdef DEBUG_CIRRUS

		    printf("cirrus: unsupported\n");

#endif

		    cirrus_bitblt_reset(s);

		    return;

		}

		src_ptr = s->cirrus_srcptr;

		src_avail =

		    data_count / s->cirrus_blt_pixelwidth *

		    s->cirrus_blt_pixelwidth;

		s->cirrus_srcptr += src_avail;

	    }

	    if (src_avail <= 0)

		break;

	}

	/* 1-line BLT */

	src_processing =

	    s->cirrus_blt_srcpitch - s->cirrus_blt_horz_counter;

	src_processing = qemu_MIN(src_avail, src_processing);

	(*s->cirrus_rop) (s->vram_ptr + s->cirrus_blt_dstaddr,

			  src_ptr, 0, 0, src_processing, 1);

	cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,

				 src_processing, 1);

	s->cirrus_blt_dstaddr += src_processing;

	src_ptr += src_processing;

	src_avail -= src_processing;

	s->cirrus_blt_horz_counter += src_processing;

	if (s->cirrus_blt_horz_counter >= s->cirrus_blt_srcpitch) {

	    src_ptr += src_linepad;

	    src_avail -= src_linepad;

	    s->cirrus_blt_dstaddr +=

		s->cirrus_blt_dstpitch - s->cirrus_blt_srcpitch;

	    s->cirrus_blt_horz_counter = 0;

	    s->cirrus_blt_height--;

	    if (s->cirrus_blt_height <= 0) {

		s->cirrus_srcptr = s->cirrus_srcptr_end;

		return;

	    }

	}

    }

}

static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)

{

    int copy_count;

    int avail_count;

    s->cirrus_blt_handler(s);

    if (s->cirrus_srccounter > 0) {

	s->cirrus_srccounter -= s->cirrus_srcptr - &s->cirrus_bltbuf[0];

	copy_count = s->cirrus_srcptr_end - s->cirrus_srcptr;

	memmove(&s->cirrus_bltbuf[0], s->cirrus_srcptr, copy_count);

	avail_count = qemu_MIN(CIRRUS_BLTBUFSIZE, s->cirrus_srccounter);

	s->cirrus_srcptr = &s->cirrus_bltbuf[0];

	s->cirrus_srcptr_end = s->cirrus_srcptr + avail_count;

	if (s->cirrus_srccounter <= 0) {

	    cirrus_bitblt_reset(s);

	}

    }

}

/***************************************

 *

 *  bitblt wrapper

 *

 ***************************************/

static void cirrus_bitblt_reset(CirrusVGAState * s)

{

    s->gr[0x31] &=

	~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);

    s->cirrus_srcptr = &s->cirrus_bltbuf[0];

    s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];

    s->cirrus_srccounter = 0;

    s->cirrus_dstptr = &s->cirrus_bltbuf[0];

    s->cirrus_dstptr_end = &s->cirrus_bltbuf[0];

    s->cirrus_dstcounter = 0;

    s->cirrus_blt_handler = NULL;

}

static int cirrus_bitblt_cputovideo(CirrusVGAState * s)

{

    s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;

    s->cirrus_srcptr = &s->cirrus_bltbuf[0];

    s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];

    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {

	if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {

	    s->cirrus_srccounter = 8;

	} else {

	    s->cirrus_srccounter = 8 * 8 * s->cirrus_blt_pixelwidth;

	}

	s->cirrus_blt_srcpitch = 0;

	s->cirrus_blt_handler = cirrus_bitblt_cputovideo_patterncopy;

    } else {

	if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {

	    s->cirrus_srccounter =

		((s->cirrus_blt_width + 7) / 8) * s->cirrus_blt_height;

	    s->cirrus_blt_srcpitch =

		s->cirrus_blt_width * s->cirrus_blt_pixelwidth;

	} else {

	    s->cirrus_srccounter =

		s->cirrus_blt_width * s->cirrus_blt_height;

	    s->cirrus_blt_srcpitch = s->cirrus_blt_width;

	}

	/* 4-byte alignment */

	s->cirrus_srccounter = (s->cirrus_srccounter + 3) & (~3);

	s->cirrus_blt_handler = cirrus_bitblt_cputovideo_copy;

	s->cirrus_blt_horz_counter = 0;

    }

    cirrus_bitblt_cputovideo_next(s);

    return 1;

}

static int cirrus_bitblt_videotocpu(CirrusVGAState * s)

{

    /* XXX */

#ifdef DEBUG_CIRRUS

    printf("cirrus: bitblt (video to cpu) is not implemented yet\n");

#endif

    return 0;

}

static int cirrus_bitblt_videotovideo(CirrusVGAState * s)

{

    int ret;

    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {

	ret = cirrus_bitblt_videotovideo_patterncopy(s);

    } else {

	ret = cirrus_bitblt_videotovideo_copy(s);

    }

    if (ret)

	cirrus_bitblt_reset(s);

    return ret;

}

static void cirrus_bitblt_start(CirrusVGAState * s)

{

    uint8_t blt_rop;

    s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;

    s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;

    s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));

    s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));

    s->cirrus_blt_dstaddr =

	(s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));

    s->cirrus_blt_srcaddr =

	(s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));

    s->cirrus_blt_mode = s->gr[0x30];

    blt_rop = s->gr[0x32];

    switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {

    case CIRRUS_BLTMODE_PIXELWIDTH8:

	s->cirrus_blt_pixelwidth = 1;

	break;

    case CIRRUS_BLTMODE_PIXELWIDTH16:

	s->cirrus_blt_pixelwidth = 2;

	break;

    case CIRRUS_BLTMODE_PIXELWIDTH24:

	s->cirrus_blt_pixelwidth = 3;

	break;

    case CIRRUS_BLTMODE_PIXELWIDTH32:

	s->cirrus_blt_pixelwidth = 4;

	break;

    default:

#ifdef DEBUG_CIRRUS

	printf("cirrus: bitblt - pixel width is unknown\n");

#endif

	goto bitblt_ignore;

    }

    s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;

    if ((s->

	 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |

			    CIRRUS_BLTMODE_MEMSYSDEST))

	== (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {

#ifdef DEBUG_CIRRUS

	printf("cirrus: bitblt - memory-to-memory copy is requested\n");

#endif

	goto bitblt_ignore;

    }

    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {

	s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;

	s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;

	s->cirrus_rop = cirrus_get_bkwd_rop_handler(blt_rop);

    } else {

	s->cirrus_rop = cirrus_get_fwd_rop_handler(blt_rop);

    }

    // setup bitblt engine.

    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {

	if (!cirrus_bitblt_cputovideo(s))

	    goto bitblt_ignore;

    } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {

	if (!cirrus_bitblt_videotocpu(s))

	    goto bitblt_ignore;

    } else {

	if (!cirrus_bitblt_videotovideo(s))

	    goto bitblt_ignore;

    }

    return;

  bitblt_ignore:;

    cirrus_bitblt_reset(s);

}

static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)

{

    unsigned old_value;

    old_value = s->gr[0x31];

    s->gr[0x31] = reg_value;

    if (((old_value & CIRRUS_BLT_RESET) != 0) &&

	((reg_value & CIRRUS_BLT_RESET) == 0)) {

	cirrus_bitblt_reset(s);

    } else if (((old_value & CIRRUS_BLT_START) == 0) &&

	       ((reg_value & CIRRUS_BLT_START) != 0)) {

	s->gr[0x31] |= CIRRUS_BLT_BUSY;

	cirrus_bitblt_start(s);

    }

}

/***************************************

 *

 *  basic parameters

 *

 ***************************************/

static void cirrus_get_offsets(VGAState *s1, 

                                   uint32_t *pline_offset,

                                   uint32_t *pstart_addr)

{

    CirrusVGAState * s = (CirrusVGAState *)s1;

    uint32_t start_addr;

    uint32_t line_offset;

    line_offset = s->cr[0x13]

	| ((s->cr[0x1b] & 0x10) << 8);

    line_offset <<= 3;

    *pline_offset = line_offset;

    start_addr = (s->cr[0x0c] << 8)

	| s->cr[0x0d]

	| ((s->cr[0x1b] & 0x01) << 16)

	| ((s->cr[0x1b] & 0x0c) << 15)

	| ((s->cr[0x1d] & 0x80) << 12);

    *pstart_addr = start_addr;

}

static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)

{

    uint32_t ret = 16;

    switch (s->cirrus_hidden_dac_data & 0xf) {

    case 0:

	ret = 15;

	break;			/* Sierra HiColor */

    case 1:

	ret = 16;

	break;			/* XGA HiColor */

    default:

#ifdef DEBUG_CIRRUS

	printf("cirrus: invalid DAC value %x in 16bpp\n",

	       (s->cirrus_hidden_dac_data & 0xf));

#endif

	ret = 15;		/* XXX */

	break;

    }

    return ret;

}

static int cirrus_get_bpp(VGAState *s1)

{

    CirrusVGAState * s = (CirrusVGAState *)s1;

    uint32_t ret = 8;

    if ((s->sr[0x07] & 0x01) != 0) {

	/* Cirrus SVGA */

	switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {

	case CIRRUS_SR7_BPP_8:

	    ret = 8;

	    break;

	case CIRRUS_SR7_BPP_16_DOUBLEVCLK:

	    ret = cirrus_get_bpp16_depth(s);

	    break;

	case CIRRUS_SR7_BPP_24:

	    ret = 24;

	    break;

	case CIRRUS_SR7_BPP_16:

	    ret = cirrus_get_bpp16_depth(s);

	    break;

	case CIRRUS_SR7_BPP_32:

	    ret = 32;

	    break;

	default:

#ifdef DEBUG_CIRRUS

	    printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);

#endif

	    ret = 8;

	    break;

	}

    } else {

	/* VGA */

	ret = 8;

    }

    return ret;

}

/***************************************

 *

 * bank memory

 *

 ***************************************/

static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)

{

    unsigned offset;

    unsigned limit;

    if ((s->gr[0x0b] & 0x01) != 0)	/* dual bank */

	offset = s->gr[0x09 + bank_index];

    else			/* single bank */

	offset = s->gr[0x09];

    if ((s->gr[0x0b] & 0x20) != 0)

	offset <<= 14;

    else

	offset <<= 12;

    if (s->vram_size <= offset)

	limit = 0;

    else

	limit = s->vram_size - offset;

    if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {

	if (limit > 0x8000) {

	    offset += 0x8000;

	    limit -= 0x8000;

	} else {

	    limit = 0;

	}

    }

    if (limit > 0) {

	s->cirrus_bank_base[bank_index] = offset;

	s->cirrus_bank_limit[bank_index] = limit;

    } else {

	s->cirrus_bank_base[bank_index] = 0;

	s->cirrus_bank_limit[bank_index] = 0;

    }

}

/***************************************

 *

 *  I/O access between 0x3c4-0x3c5

 *

 ***************************************/

static int

cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)

{

    switch (reg_index) {

    case 0x00:			// Standard VGA

    case 0x01:			// Standard VGA

    case 0x02:			// Standard VGA

    case 0x03:			// Standard VGA

    case 0x04:			// Standard VGA

	return CIRRUS_HOOK_NOT_HANDLED;

    case 0x06:			// Unlock Cirrus extensions

	*reg_value = s->sr[reg_index];

	break;

    case 0x05:			// ???

    case 0x07:			// Extended Sequencer Mode

    case 0x08:			// EEPROM Control

    case 0x09:			// Scratch Register 0

    case 0x0a:			// Scratch Register 1

    case 0x0b:			// VCLK 0

    case 0x0c:			// VCLK 1

    case 0x0d:			// VCLK 2

    case 0x0e:			// VCLK 3

    case 0x0f:			// DRAM Control

    case 0x10:

    case 0x30:

    case 0x50:

    case 0x70:			// Graphics Cursor X

    case 0x90:

    case 0xb0:

    case 0xd0:

    case 0xf0:			// Graphics Cursor X

    case 0x11:

    case 0x31:

    case 0x51:

    case 0x71:			// Graphics Cursor Y

    case 0x91:

    case 0xb1:

    case 0xd1:

    case 0xf1:			// Graphics Cursor Y

    case 0x12:			// Graphics Cursor Attribute

    case 0x13:			// Graphics Cursor Pattern Address

    case 0x14:			// Scratch Register 2

    case 0x15:			// Scratch Register 3

    case 0x16:			// Performance Tuning Register

    case 0x17:			// Configuration Readback and Extended Control

    case 0x18:			// Signature Generator Control

    case 0x19:			// Signal Generator Result

    case 0x1a:			// Signal Generator Result

    case 0x1b:			// VCLK 0 Denominator & Post

    case 0x1c:			// VCLK 1 Denominator & Post

    case 0x1d:			// VCLK 2 Denominator & Post

    case 0x1e:			// VCLK 3 Denominator & Post

    case 0x1f:			// BIOS Write Enable and MCLK select

#ifdef DEBUG_CIRRUS

	printf("cirrus: handled inport sr_index %02x\n", reg_index);

#endif

	*reg_value = s->sr[reg_index];

	break;

    default:

#ifdef DEBUG_CIRRUS

	printf("cirrus: inport sr_index %02x\n", reg_index);

#endif

	*reg_value = 0xff;

	break;

    }

    return CIRRUS_HOOK_HANDLED;

}

static int

cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)

{

    switch (reg_index) {

    case 0x00:			// Standard VGA

    case 0x01:			// Standard VGA

    case 0x02:			// Standard VGA

    case 0x03:			// Standard VGA

    case 0x04:			// Standard VGA

	return CIRRUS_HOOK_NOT_HANDLED;

    case 0x06:			// Unlock Cirrus extensions

	reg_value &= 0x17;

	if (reg_value == 0x12) {

	    s->sr[reg_index] = 0x12;

	} else {

	    s->sr[reg_index] = 0x0f;

	}

	break;

    case 0x10:

    case 0x30:

    case 0x50:

    case 0x70:			// Graphics Cursor X

    case 0x90:

    case 0xb0:

    case 0xd0:

    case 0xf0:			// Graphics Cursor X

	s->sr[0x10] = reg_value;

	s->cirrus_hw_cursor_x = ((reg_index << 3) & 0x700) | reg_value;

	break;

    case 0x11:

    case 0x31:

    case 0x51:

    case 0x71:			// Graphics Cursor Y

    case 0x91:

    case 0xb1:

    case 0xd1:

    case 0xf1:			// Graphics Cursor Y

	s->sr[0x11] = reg_value;

	s->cirrus_hw_cursor_y = ((reg_index << 3) & 0x700) | reg_value;

	break;

    case 0x07:			// Extended Sequencer Mode

    case 0x08:			// EEPROM Control

    case 0x09:			// Scratch Register 0

    case 0x0a:			// Scratch Register 1

    case 0x0b:			// VCLK 0

    case 0x0c:			// VCLK 1

    case 0x0d:			// VCLK 2

    case 0x0e:			// VCLK 3

    case 0x0f:			// DRAM Control

    case 0x12:			// Graphics Cursor Attribute

    case 0x13:			// Graphics Cursor Pattern Address

    case 0x14:			// Scratch Register 2

    case 0x15:			// Scratch Register 3

    case 0x16:			// Performance Tuning Register

    case 0x17:			// Configuration Readback and Extended Control

    case 0x18:			// Signature Generator Control

    case 0x19:			// Signature Generator Result

    case 0x1a:			// Signature Generator Result

    case 0x1b:			// VCLK 0 Denominator & Post

    case 0x1c:			// VCLK 1 Denominator & Post

    case 0x1d:			// VCLK 2 Denominator & Post

    case 0x1e:			// VCLK 3 Denominator & Post

    case 0x1f:			// BIOS Write Enable and MCLK select

	s->sr[reg_index] = reg_value;

#ifdef DEBUG_CIRRUS

	printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",

	       reg_index, reg_value);

#endif

	break;

    default:

#ifdef DEBUG_CIRRUS

	printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,

	       reg_value);

#endif

	break;

    }

    return CIRRUS_HOOK_HANDLED;

}

/***************************************

 *

 *  I/O access at 0x3c6

 *

 ***************************************/

static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)

{

    *reg_value = 0xff;

    if (s->cirrus_hidden_dac_lockindex < 5) {

	if (s->cirrus_hidden_dac_lockindex == 4) {

	    *reg_value = s->cirrus_hidden_dac_data;

	}

	s->cirrus_hidden_dac_lockindex++;

    }

}

static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)

{

    if (s->cirrus_hidden_dac_lockindex == 4) {

	s->cirrus_hidden_dac_data = reg_value;

#ifdef DEBUG_CIRRUS

	printf("cirrus: outport hidden DAC, value %02x\n", reg_value);

#endif

    }

    s->cirrus_hidden_dac_lockindex = 0;

}

/***************************************

 *

 *  I/O access at 0x3c9

 *

 ***************************************/

static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)

{

    if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))

	return CIRRUS_HOOK_NOT_HANDLED;

    if (s->dac_read_index < 0x10) {

	*reg_value =

	    s->cirrus_hidden_palette[s->dac_read_index * 3 +

				     s->dac_sub_index];

    } else {

	*reg_value = 0xff;	/* XXX */

    }

    if (++s->dac_sub_index == 3) {

	s->dac_sub_index = 0;

	s->dac_read_index++;

    }

    return CIRRUS_HOOK_HANDLED;

}

static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)

{

    if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))

	return CIRRUS_HOOK_NOT_HANDLED;

    s->dac_cache[s->dac_sub_index] = reg_value;

    if (++s->dac_sub_index == 3) {

	if (s->dac_read_index < 0x10) {

	    memcpy(&s->cirrus_hidden_palette[s->dac_write_index * 3],

		   s->dac_cache, 3);

	    /* XXX update cursor */

	}

	s->dac_sub_index = 0;

	s->dac_write_index++;

    }

    return CIRRUS_HOOK_HANDLED;

}

/***************************************

 *

 *  I/O access between 0x3ce-0x3cf

 *

 ***************************************/

static int

cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)

{

    switch (reg_index) {

    case 0x02:			// Standard VGA

    case 0x03:			// Standard VGA

    case 0x04:			// Standard VGA

    case 0x06:			// Standard VGA

    case 0x07:			// Standard VGA

    case 0x08:			// Standard VGA

	return CIRRUS_HOOK_NOT_HANDLED;

    case 0x05:			// Standard VGA, Cirrus extended mode

    default:

	break;

    }

    if (reg_index < 0x3a) {

	*reg_value = s->gr[reg_index];

    } else {

#ifdef DEBUG_CIRRUS

	printf("cirrus: inport gr_index %02x\n", reg_index);

#endif

	*reg_value = 0xff;

    }

    return CIRRUS_HOOK_HANDLED;

}

static int

cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)

{

    switch (reg_index) {

    case 0x00:			// Standard VGA, BGCOLOR 0x000000ff

	s->gr[0x00] = reg_value;

	return CIRRUS_HOOK_NOT_HANDLED;

    case 0x01:			// Standard VGA, FGCOLOR 0x000000ff

	s->gr[0x01] = reg_value;

	return CIRRUS_HOOK_NOT_HANDLED;

    case 0x02:			// Standard VGA

    case 0x03:			// Standard VGA

    case 0x04:			// Standard VGA

    case 0x06:			// Standard VGA

    case 0x07:			// Standard VGA

    case 0x08:			// Standard VGA

	return CIRRUS_HOOK_NOT_HANDLED;

    case 0x05:			// Standard VGA, Cirrus extended mode

	s->gr[reg_index] = reg_value & 0x7f;

	break;

    case 0x09:			// bank offset #0

    case 0x0A:			// bank offset #1

    case 0x0B:

	s->gr[reg_index] = reg_value;

	cirrus_update_bank_ptr(s, 0);

	cirrus_update_bank_ptr(s, 1);

	break;

    case 0x10:			// BGCOLOR 0x0000ff00

    case 0x11:			// FGCOLOR 0x0000ff00

    case 0x12:			// BGCOLOR 0x00ff0000

    case 0x13:			// FGCOLOR 0x00ff0000

    case 0x14:			// BGCOLOR 0xff000000

    case 0x15:			// FGCOLOR 0xff000000

    case 0x20:			// BLT WIDTH 0x0000ff

    case 0x22:			// BLT HEIGHT 0x0000ff

    case 0x24:			// BLT DEST PITCH 0x0000ff

    case 0x26:			// BLT SRC PITCH 0x0000ff

    case 0x28:			// BLT DEST ADDR 0x0000ff

    case 0x29:			// BLT DEST ADDR 0x00ff00

    case 0x2c:			// BLT SRC ADDR 0x0000ff

    case 0x2d:			// BLT SRC ADDR 0x00ff00

    case 0x30:			// BLT MODE

    case 0x32:			// RASTER OP

    case 0x34:			// BLT TRANSPARENT COLOR 0x00ff

    case 0x35:			// BLT TRANSPARENT COLOR 0xff00

    case 0x38:			// BLT TRANSPARENT COLOR MASK 0x00ff

    case 0x39:			// BLT TRANSPARENT COLOR MASK 0xff00

	s->gr[reg_index] = reg_value;

	break;

    case 0x21:			// BLT WIDTH 0x001f00

    case 0x23:			// BLT HEIGHT 0x001f00

    case 0x25:			// BLT DEST PITCH 0x001f00

    case 0x27:			// BLT SRC PITCH 0x001f00

	s->gr[reg_index] = reg_value & 0x1f;

	break;

    case 0x2a:			// BLT DEST ADDR 0x3f0000

    case 0x2e:			// BLT SRC ADDR 0x3f0000

	s->gr[reg_index] = reg_value & 0x3f;

	break;

    case 0x31:			// BLT STATUS/START

	cirrus_write_bitblt(s, reg_value);

	break;

    default:

#ifdef DEBUG_CIRRUS

	printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,

	       reg_value);

#endif

	break;

    }

    return CIRRUS_HOOK_HANDLED;

}

/***************************************