root / hw / armv7m_nvic.c @ e83ce550
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1 | 9ee6e8bb | pbrook | /*
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2 | 9ee6e8bb | pbrook | * ARM Nested Vectored Interrupt Controller
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3 | 9ee6e8bb | pbrook | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | 9ee6e8bb | pbrook | * Written by Paul Brook
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6 | 9ee6e8bb | pbrook | *
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7 | 9ee6e8bb | pbrook | * This code is licenced under the GPL.
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8 | 9ee6e8bb | pbrook | *
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9 | 9ee6e8bb | pbrook | * The ARMv7M System controller is fairly tightly tied in with the
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10 | 9ee6e8bb | pbrook | * NVIC. Much of that is also implemented here.
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11 | 9ee6e8bb | pbrook | */
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12 | 9ee6e8bb | pbrook | |
13 | 87ecb68b | pbrook | #include "hw.h" |
14 | 87ecb68b | pbrook | #include "qemu-timer.h" |
15 | 87ecb68b | pbrook | #include "arm-misc.h" |
16 | 9ee6e8bb | pbrook | |
17 | eea589cc | pbrook | /* 32 internal lines (16 used for system exceptions) plus 64 external
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18 | eea589cc | pbrook | interrupt lines. */
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19 | eea589cc | pbrook | #define GIC_NIRQ 96 |
20 | 9ee6e8bb | pbrook | #define NCPU 1 |
21 | 9ee6e8bb | pbrook | #define NVIC 1 |
22 | 9ee6e8bb | pbrook | |
23 | 9ee6e8bb | pbrook | /* Only a single "CPU" interface is present. */
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24 | 9ee6e8bb | pbrook | static inline int |
25 | 9ee6e8bb | pbrook | gic_get_current_cpu(void)
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26 | 9ee6e8bb | pbrook | { |
27 | 9ee6e8bb | pbrook | return 0; |
28 | 9ee6e8bb | pbrook | } |
29 | 9ee6e8bb | pbrook | |
30 | 9ee6e8bb | pbrook | static uint32_t nvic_readl(void *opaque, uint32_t offset); |
31 | 9ee6e8bb | pbrook | static void nvic_writel(void *opaque, uint32_t offset, uint32_t value); |
32 | 9ee6e8bb | pbrook | |
33 | 9ee6e8bb | pbrook | #include "arm_gic.c" |
34 | 9ee6e8bb | pbrook | |
35 | 9ee6e8bb | pbrook | typedef struct { |
36 | 9ee6e8bb | pbrook | struct {
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37 | 9ee6e8bb | pbrook | uint32_t control; |
38 | 9ee6e8bb | pbrook | uint32_t reload; |
39 | 9ee6e8bb | pbrook | int64_t tick; |
40 | 9ee6e8bb | pbrook | QEMUTimer *timer; |
41 | 9ee6e8bb | pbrook | } systick; |
42 | 9ee6e8bb | pbrook | gic_state *gic; |
43 | 9ee6e8bb | pbrook | } nvic_state; |
44 | 9ee6e8bb | pbrook | |
45 | 9ee6e8bb | pbrook | /* qemu timers run at 1GHz. We want something closer to 1MHz. */
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46 | 9ee6e8bb | pbrook | #define SYSTICK_SCALE 1000ULL |
47 | 9ee6e8bb | pbrook | |
48 | 9ee6e8bb | pbrook | #define SYSTICK_ENABLE (1 << 0) |
49 | 9ee6e8bb | pbrook | #define SYSTICK_TICKINT (1 << 1) |
50 | 9ee6e8bb | pbrook | #define SYSTICK_CLKSOURCE (1 << 2) |
51 | 9ee6e8bb | pbrook | #define SYSTICK_COUNTFLAG (1 << 16) |
52 | 9ee6e8bb | pbrook | |
53 | e57ec016 | pbrook | /* Conversion factor from qemu timer to SysTick frequencies. */
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54 | 9ee6e8bb | pbrook | static inline int64_t systick_scale(nvic_state *s) |
55 | 9ee6e8bb | pbrook | { |
56 | 9ee6e8bb | pbrook | if (s->systick.control & SYSTICK_CLKSOURCE)
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57 | e57ec016 | pbrook | return system_clock_scale;
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58 | 9ee6e8bb | pbrook | else
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59 | 9ee6e8bb | pbrook | return 1000; |
60 | 9ee6e8bb | pbrook | } |
61 | 9ee6e8bb | pbrook | |
62 | 9ee6e8bb | pbrook | static void systick_reload(nvic_state *s, int reset) |
63 | 9ee6e8bb | pbrook | { |
64 | 9ee6e8bb | pbrook | if (reset)
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65 | 9ee6e8bb | pbrook | s->systick.tick = qemu_get_clock(vm_clock); |
66 | 9ee6e8bb | pbrook | s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
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67 | 9ee6e8bb | pbrook | qemu_mod_timer(s->systick.timer, s->systick.tick); |
68 | 9ee6e8bb | pbrook | } |
69 | 9ee6e8bb | pbrook | |
70 | 9ee6e8bb | pbrook | static void systick_timer_tick(void * opaque) |
71 | 9ee6e8bb | pbrook | { |
72 | 9ee6e8bb | pbrook | nvic_state *s = (nvic_state *)opaque; |
73 | 9ee6e8bb | pbrook | s->systick.control |= SYSTICK_COUNTFLAG; |
74 | 9ee6e8bb | pbrook | if (s->systick.control & SYSTICK_TICKINT) {
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75 | 9ee6e8bb | pbrook | /* Trigger the interrupt. */
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76 | 9ee6e8bb | pbrook | armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK); |
77 | 9ee6e8bb | pbrook | } |
78 | 9ee6e8bb | pbrook | if (s->systick.reload == 0) { |
79 | 9ee6e8bb | pbrook | s->systick.control &= ~SYSTICK_ENABLE; |
80 | 9ee6e8bb | pbrook | } else {
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81 | 9ee6e8bb | pbrook | systick_reload(s, 0);
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82 | 9ee6e8bb | pbrook | } |
83 | 9ee6e8bb | pbrook | } |
84 | 9ee6e8bb | pbrook | |
85 | 9ee6e8bb | pbrook | /* The external routines use the hardware vector numbering, ie. the first
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86 | 9ee6e8bb | pbrook | IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
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87 | 9ee6e8bb | pbrook | void armv7m_nvic_set_pending(void *opaque, int irq) |
88 | 9ee6e8bb | pbrook | { |
89 | 9ee6e8bb | pbrook | nvic_state *s = (nvic_state *)opaque; |
90 | 9ee6e8bb | pbrook | if (irq >= 16) |
91 | 9ee6e8bb | pbrook | irq += 16;
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92 | 9ee6e8bb | pbrook | gic_set_pending_private(s->gic, 0, irq);
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93 | 9ee6e8bb | pbrook | } |
94 | 9ee6e8bb | pbrook | |
95 | 9ee6e8bb | pbrook | /* Make pending IRQ active. */
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96 | 9ee6e8bb | pbrook | int armv7m_nvic_acknowledge_irq(void *opaque) |
97 | 9ee6e8bb | pbrook | { |
98 | 9ee6e8bb | pbrook | nvic_state *s = (nvic_state *)opaque; |
99 | 9ee6e8bb | pbrook | uint32_t irq; |
100 | 9ee6e8bb | pbrook | |
101 | 9ee6e8bb | pbrook | irq = gic_acknowledge_irq(s->gic, 0);
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102 | 9ee6e8bb | pbrook | if (irq == 1023) |
103 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "Interrupt but no vector\n");
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104 | 9ee6e8bb | pbrook | if (irq >= 32) |
105 | 9ee6e8bb | pbrook | irq -= 16;
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106 | 9ee6e8bb | pbrook | return irq;
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107 | 9ee6e8bb | pbrook | } |
108 | 9ee6e8bb | pbrook | |
109 | 9ee6e8bb | pbrook | void armv7m_nvic_complete_irq(void *opaque, int irq) |
110 | 9ee6e8bb | pbrook | { |
111 | 9ee6e8bb | pbrook | nvic_state *s = (nvic_state *)opaque; |
112 | 9ee6e8bb | pbrook | if (irq >= 16) |
113 | 9ee6e8bb | pbrook | irq += 16;
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114 | 9ee6e8bb | pbrook | gic_complete_irq(s->gic, 0, irq);
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115 | 9ee6e8bb | pbrook | } |
116 | 9ee6e8bb | pbrook | |
117 | 9ee6e8bb | pbrook | static uint32_t nvic_readl(void *opaque, uint32_t offset) |
118 | 9ee6e8bb | pbrook | { |
119 | 9ee6e8bb | pbrook | nvic_state *s = (nvic_state *)opaque; |
120 | 9ee6e8bb | pbrook | uint32_t val; |
121 | 9ee6e8bb | pbrook | int irq;
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122 | 9ee6e8bb | pbrook | |
123 | 9ee6e8bb | pbrook | switch (offset) {
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124 | 9ee6e8bb | pbrook | case 4: /* Interrupt Control Type. */ |
125 | 9ee6e8bb | pbrook | return (GIC_NIRQ / 32) - 1; |
126 | 9ee6e8bb | pbrook | case 0x10: /* SysTick Control and Status. */ |
127 | 9ee6e8bb | pbrook | val = s->systick.control; |
128 | 9ee6e8bb | pbrook | s->systick.control &= ~SYSTICK_COUNTFLAG; |
129 | 9ee6e8bb | pbrook | return val;
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130 | 9ee6e8bb | pbrook | case 0x14: /* SysTick Reload Value. */ |
131 | 9ee6e8bb | pbrook | return s->systick.reload;
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132 | 9ee6e8bb | pbrook | case 0x18: /* SysTick Current Value. */ |
133 | 9ee6e8bb | pbrook | { |
134 | 9ee6e8bb | pbrook | int64_t t; |
135 | 9ee6e8bb | pbrook | if ((s->systick.control & SYSTICK_ENABLE) == 0) |
136 | 9ee6e8bb | pbrook | return 0; |
137 | 9ee6e8bb | pbrook | t = qemu_get_clock(vm_clock); |
138 | 9ee6e8bb | pbrook | if (t >= s->systick.tick)
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139 | 9ee6e8bb | pbrook | return 0; |
140 | 9ee6e8bb | pbrook | val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1; |
141 | 9ee6e8bb | pbrook | /* The interrupt in triggered when the timer reaches zero.
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142 | 9ee6e8bb | pbrook | However the counter is not reloaded until the next clock
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143 | 9ee6e8bb | pbrook | tick. This is a hack to return zero during the first tick. */
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144 | 9ee6e8bb | pbrook | if (val > s->systick.reload)
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145 | 9ee6e8bb | pbrook | val = 0;
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146 | 9ee6e8bb | pbrook | return val;
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147 | 9ee6e8bb | pbrook | } |
148 | 9ee6e8bb | pbrook | case 0x1c: /* SysTick Calibration Value. */ |
149 | 9ee6e8bb | pbrook | return 10000; |
150 | 9ee6e8bb | pbrook | case 0xd00: /* CPUID Base. */ |
151 | 9ee6e8bb | pbrook | return cpu_single_env->cp15.c0_cpuid;
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152 | 9ee6e8bb | pbrook | case 0xd04: /* Interrypt Control State. */ |
153 | 9ee6e8bb | pbrook | /* VECTACTIVE */
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154 | 9ee6e8bb | pbrook | val = s->gic->running_irq[0];
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155 | 9ee6e8bb | pbrook | if (val == 1023) { |
156 | 9ee6e8bb | pbrook | val = 0;
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157 | 9ee6e8bb | pbrook | } else if (val >= 32) { |
158 | 9ee6e8bb | pbrook | val -= 16;
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159 | 9ee6e8bb | pbrook | } |
160 | 9ee6e8bb | pbrook | /* RETTOBASE */
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161 | 9ee6e8bb | pbrook | if (s->gic->running_irq[0] == 1023 |
162 | 9ee6e8bb | pbrook | || s->gic->last_active[s->gic->running_irq[0]][0] == 1023) { |
163 | 9ee6e8bb | pbrook | val |= (1 << 11); |
164 | 9ee6e8bb | pbrook | } |
165 | 9ee6e8bb | pbrook | /* VECTPENDING */
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166 | 9ee6e8bb | pbrook | if (s->gic->current_pending[0] != 1023) |
167 | 9ee6e8bb | pbrook | val |= (s->gic->current_pending[0] << 12); |
168 | 9ee6e8bb | pbrook | /* ISRPENDING */
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169 | 9ee6e8bb | pbrook | for (irq = 32; irq < GIC_NIRQ; irq++) { |
170 | 9ee6e8bb | pbrook | if (s->gic->irq_state[irq].pending) {
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171 | 9ee6e8bb | pbrook | val |= (1 << 22); |
172 | 9ee6e8bb | pbrook | break;
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173 | 9ee6e8bb | pbrook | } |
174 | 9ee6e8bb | pbrook | } |
175 | 9ee6e8bb | pbrook | /* PENDSTSET */
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176 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_SYSTICK].pending)
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177 | 9ee6e8bb | pbrook | val |= (1 << 26); |
178 | 9ee6e8bb | pbrook | /* PENDSVSET */
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179 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_PENDSV].pending)
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180 | 9ee6e8bb | pbrook | val |= (1 << 28); |
181 | 9ee6e8bb | pbrook | /* NMIPENDSET */
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182 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_NMI].pending)
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183 | 9ee6e8bb | pbrook | val |= (1 << 31); |
184 | 9ee6e8bb | pbrook | return val;
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185 | 9ee6e8bb | pbrook | case 0xd08: /* Vector Table Offset. */ |
186 | 9ee6e8bb | pbrook | return cpu_single_env->v7m.vecbase;
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187 | 9ee6e8bb | pbrook | case 0xd0c: /* Application Interrupt/Reset Control. */ |
188 | 9ee6e8bb | pbrook | return 0xfa05000; |
189 | 9ee6e8bb | pbrook | case 0xd10: /* System Control. */ |
190 | 9ee6e8bb | pbrook | /* TODO: Implement SLEEPONEXIT. */
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191 | 9ee6e8bb | pbrook | return 0; |
192 | 9ee6e8bb | pbrook | case 0xd14: /* Configuration Control. */ |
193 | 9ee6e8bb | pbrook | /* TODO: Implement Configuration Control bits. */
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194 | 9ee6e8bb | pbrook | return 0; |
195 | 9ee6e8bb | pbrook | case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */ |
196 | 9ee6e8bb | pbrook | irq = offset - 0xd14;
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197 | 9ee6e8bb | pbrook | val = 0;
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198 | 9ee6e8bb | pbrook | val = s->gic->priority1[irq++][0];
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199 | 9ee6e8bb | pbrook | val = s->gic->priority1[irq++][0] << 8; |
200 | 9ee6e8bb | pbrook | val = s->gic->priority1[irq++][0] << 16; |
201 | 9ee6e8bb | pbrook | val = s->gic->priority1[irq][0] << 24; |
202 | 9ee6e8bb | pbrook | return val;
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203 | 9ee6e8bb | pbrook | case 0xd24: /* System Handler Status. */ |
204 | 9ee6e8bb | pbrook | val = 0;
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205 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0); |
206 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1); |
207 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3); |
208 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7); |
209 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8); |
210 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10); |
211 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11); |
212 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12); |
213 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13); |
214 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14); |
215 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15); |
216 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16); |
217 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17); |
218 | 9ee6e8bb | pbrook | if (s->gic->irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18); |
219 | 9ee6e8bb | pbrook | return val;
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220 | 9ee6e8bb | pbrook | case 0xd28: /* Configurable Fault Status. */ |
221 | 9ee6e8bb | pbrook | /* TODO: Implement Fault Status. */
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222 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, |
223 | 9ee6e8bb | pbrook | "Not implemented: Configurable Fault Status.");
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224 | 9ee6e8bb | pbrook | return 0; |
225 | 9ee6e8bb | pbrook | case 0xd2c: /* Hard Fault Status. */ |
226 | 9ee6e8bb | pbrook | case 0xd30: /* Debug Fault Status. */ |
227 | 9ee6e8bb | pbrook | case 0xd34: /* Mem Manage Address. */ |
228 | 9ee6e8bb | pbrook | case 0xd38: /* Bus Fault Address. */ |
229 | 9ee6e8bb | pbrook | case 0xd3c: /* Aux Fault Status. */ |
230 | 9ee6e8bb | pbrook | /* TODO: Implement fault status registers. */
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231 | 9ee6e8bb | pbrook | goto bad_reg;
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232 | 9ee6e8bb | pbrook | case 0xd40: /* PFR0. */ |
233 | 9ee6e8bb | pbrook | return 0x00000030; |
234 | 9ee6e8bb | pbrook | case 0xd44: /* PRF1. */ |
235 | 9ee6e8bb | pbrook | return 0x00000200; |
236 | 9ee6e8bb | pbrook | case 0xd48: /* DFR0. */ |
237 | 9ee6e8bb | pbrook | return 0x00100000; |
238 | 9ee6e8bb | pbrook | case 0xd4c: /* AFR0. */ |
239 | 9ee6e8bb | pbrook | return 0x00000000; |
240 | 9ee6e8bb | pbrook | case 0xd50: /* MMFR0. */ |
241 | 9ee6e8bb | pbrook | return 0x00000030; |
242 | 9ee6e8bb | pbrook | case 0xd54: /* MMFR1. */ |
243 | 9ee6e8bb | pbrook | return 0x00000000; |
244 | 9ee6e8bb | pbrook | case 0xd58: /* MMFR2. */ |
245 | 9ee6e8bb | pbrook | return 0x00000000; |
246 | 9ee6e8bb | pbrook | case 0xd5c: /* MMFR3. */ |
247 | 9ee6e8bb | pbrook | return 0x00000000; |
248 | 9ee6e8bb | pbrook | case 0xd60: /* ISAR0. */ |
249 | 9ee6e8bb | pbrook | return 0x01141110; |
250 | 9ee6e8bb | pbrook | case 0xd64: /* ISAR1. */ |
251 | 9ee6e8bb | pbrook | return 0x02111000; |
252 | 9ee6e8bb | pbrook | case 0xd68: /* ISAR2. */ |
253 | 9ee6e8bb | pbrook | return 0x21112231; |
254 | 9ee6e8bb | pbrook | case 0xd6c: /* ISAR3. */ |
255 | 9ee6e8bb | pbrook | return 0x01111110; |
256 | 9ee6e8bb | pbrook | case 0xd70: /* ISAR4. */ |
257 | 9ee6e8bb | pbrook | return 0x01310102; |
258 | 9ee6e8bb | pbrook | /* TODO: Implement debug registers. */
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259 | 9ee6e8bb | pbrook | default:
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260 | 9ee6e8bb | pbrook | bad_reg:
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261 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "NVIC: Bad read offset 0x%x\n", offset);
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262 | 9ee6e8bb | pbrook | } |
263 | 9ee6e8bb | pbrook | } |
264 | 9ee6e8bb | pbrook | |
265 | 9ee6e8bb | pbrook | static void nvic_writel(void *opaque, uint32_t offset, uint32_t value) |
266 | 9ee6e8bb | pbrook | { |
267 | 9ee6e8bb | pbrook | nvic_state *s = (nvic_state *)opaque; |
268 | 9ee6e8bb | pbrook | uint32_t oldval; |
269 | 9ee6e8bb | pbrook | switch (offset) {
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270 | 9ee6e8bb | pbrook | case 0x10: /* SysTick Control and Status. */ |
271 | 9ee6e8bb | pbrook | oldval = s->systick.control; |
272 | 9ee6e8bb | pbrook | s->systick.control &= 0xfffffff8;
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273 | 9ee6e8bb | pbrook | s->systick.control |= value & 7;
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274 | 9ee6e8bb | pbrook | if ((oldval ^ value) & SYSTICK_ENABLE) {
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275 | 9ee6e8bb | pbrook | int64_t now = qemu_get_clock(vm_clock); |
276 | 9ee6e8bb | pbrook | if (value & SYSTICK_ENABLE) {
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277 | 9ee6e8bb | pbrook | if (s->systick.tick) {
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278 | 9ee6e8bb | pbrook | s->systick.tick += now; |
279 | 9ee6e8bb | pbrook | qemu_mod_timer(s->systick.timer, s->systick.tick); |
280 | 9ee6e8bb | pbrook | } else {
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281 | 9ee6e8bb | pbrook | systick_reload(s, 1);
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282 | 9ee6e8bb | pbrook | } |
283 | 9ee6e8bb | pbrook | } else {
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284 | 9ee6e8bb | pbrook | qemu_del_timer(s->systick.timer); |
285 | 9ee6e8bb | pbrook | s->systick.tick -= now; |
286 | 9ee6e8bb | pbrook | if (s->systick.tick < 0) |
287 | 9ee6e8bb | pbrook | s->systick.tick = 0;
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288 | 9ee6e8bb | pbrook | } |
289 | 9ee6e8bb | pbrook | } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) { |
290 | 9ee6e8bb | pbrook | /* This is a hack. Force the timer to be reloaded
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291 | 9ee6e8bb | pbrook | when the reference clock is changed. */
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292 | 9ee6e8bb | pbrook | systick_reload(s, 1);
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293 | 9ee6e8bb | pbrook | } |
294 | 9ee6e8bb | pbrook | break;
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295 | 9ee6e8bb | pbrook | case 0x14: /* SysTick Reload Value. */ |
296 | 9ee6e8bb | pbrook | s->systick.reload = value; |
297 | 9ee6e8bb | pbrook | break;
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298 | 9ee6e8bb | pbrook | case 0x18: /* SysTick Current Value. Writes reload the timer. */ |
299 | 9ee6e8bb | pbrook | systick_reload(s, 1);
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300 | 9ee6e8bb | pbrook | s->systick.control &= ~SYSTICK_COUNTFLAG; |
301 | 9ee6e8bb | pbrook | break;
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302 | 9ee6e8bb | pbrook | case 0xd04: /* Interrupt Control State. */ |
303 | 9ee6e8bb | pbrook | if (value & (1 << 31)) { |
304 | 9ee6e8bb | pbrook | armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI); |
305 | 9ee6e8bb | pbrook | } |
306 | 9ee6e8bb | pbrook | if (value & (1 << 28)) { |
307 | 9ee6e8bb | pbrook | armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV); |
308 | 9ee6e8bb | pbrook | } else if (value & (1 << 27)) { |
309 | 9ee6e8bb | pbrook | s->gic->irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
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310 | 9ee6e8bb | pbrook | gic_update(s->gic); |
311 | 9ee6e8bb | pbrook | } |
312 | 9ee6e8bb | pbrook | if (value & (1 << 26)) { |
313 | 9ee6e8bb | pbrook | armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK); |
314 | 9ee6e8bb | pbrook | } else if (value & (1 << 25)) { |
315 | 9ee6e8bb | pbrook | s->gic->irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
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316 | 9ee6e8bb | pbrook | gic_update(s->gic); |
317 | 9ee6e8bb | pbrook | } |
318 | 9ee6e8bb | pbrook | break;
|
319 | 9ee6e8bb | pbrook | case 0xd08: /* Vector Table Offset. */ |
320 | 9ee6e8bb | pbrook | cpu_single_env->v7m.vecbase = value & 0xffffff80;
|
321 | 9ee6e8bb | pbrook | break;
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322 | 9ee6e8bb | pbrook | case 0xd0c: /* Application Interrupt/Reset Control. */ |
323 | 9ee6e8bb | pbrook | if ((value >> 16) == 0x05fa) { |
324 | 9ee6e8bb | pbrook | if (value & 2) { |
325 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "VECTCLRACTIVE not implemented");
|
326 | 9ee6e8bb | pbrook | } |
327 | 9ee6e8bb | pbrook | if (value & 5) { |
328 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "System reset");
|
329 | 9ee6e8bb | pbrook | } |
330 | 9ee6e8bb | pbrook | } |
331 | 9ee6e8bb | pbrook | break;
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332 | 9ee6e8bb | pbrook | case 0xd10: /* System Control. */ |
333 | 9ee6e8bb | pbrook | case 0xd14: /* Configuration Control. */ |
334 | 9ee6e8bb | pbrook | /* TODO: Implement control registers. */
|
335 | 9ee6e8bb | pbrook | goto bad_reg;
|
336 | 9ee6e8bb | pbrook | case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */ |
337 | 9ee6e8bb | pbrook | { |
338 | 9ee6e8bb | pbrook | int irq;
|
339 | 9ee6e8bb | pbrook | irq = offset - 0xd14;
|
340 | 9ee6e8bb | pbrook | s->gic->priority1[irq++][0] = value & 0xff; |
341 | 9ee6e8bb | pbrook | s->gic->priority1[irq++][0] = (value >> 8) & 0xff; |
342 | 9ee6e8bb | pbrook | s->gic->priority1[irq++][0] = (value >> 16) & 0xff; |
343 | 9ee6e8bb | pbrook | s->gic->priority1[irq][0] = (value >> 24) & 0xff; |
344 | 9ee6e8bb | pbrook | gic_update(s->gic); |
345 | 9ee6e8bb | pbrook | } |
346 | 9ee6e8bb | pbrook | break;
|
347 | 9ee6e8bb | pbrook | case 0xd24: /* System Handler Control. */ |
348 | 9ee6e8bb | pbrook | /* TODO: Real hardware allows you to set/clear the active bits
|
349 | 9ee6e8bb | pbrook | under some circumstances. We don't implement this. */
|
350 | 9ee6e8bb | pbrook | s->gic->irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; |
351 | 9ee6e8bb | pbrook | s->gic->irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; |
352 | 9ee6e8bb | pbrook | s->gic->irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0; |
353 | 9ee6e8bb | pbrook | break;
|
354 | 9ee6e8bb | pbrook | case 0xd28: /* Configurable Fault Status. */ |
355 | 9ee6e8bb | pbrook | case 0xd2c: /* Hard Fault Status. */ |
356 | 9ee6e8bb | pbrook | case 0xd30: /* Debug Fault Status. */ |
357 | 9ee6e8bb | pbrook | case 0xd34: /* Mem Manage Address. */ |
358 | 9ee6e8bb | pbrook | case 0xd38: /* Bus Fault Address. */ |
359 | 9ee6e8bb | pbrook | case 0xd3c: /* Aux Fault Status. */ |
360 | 9ee6e8bb | pbrook | goto bad_reg;
|
361 | 9ee6e8bb | pbrook | default:
|
362 | 9ee6e8bb | pbrook | bad_reg:
|
363 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "NVIC: Bad write offset 0x%x\n", offset);
|
364 | 9ee6e8bb | pbrook | } |
365 | 9ee6e8bb | pbrook | } |
366 | 9ee6e8bb | pbrook | |
367 | 23e39294 | pbrook | static void nvic_save(QEMUFile *f, void *opaque) |
368 | 23e39294 | pbrook | { |
369 | 23e39294 | pbrook | nvic_state *s = (nvic_state *)opaque; |
370 | 23e39294 | pbrook | |
371 | 23e39294 | pbrook | qemu_put_be32(f, s->systick.control); |
372 | 23e39294 | pbrook | qemu_put_be32(f, s->systick.reload); |
373 | 23e39294 | pbrook | qemu_put_be64(f, s->systick.tick); |
374 | 23e39294 | pbrook | qemu_put_timer(f, s->systick.timer); |
375 | 23e39294 | pbrook | } |
376 | 23e39294 | pbrook | |
377 | 23e39294 | pbrook | static int nvic_load(QEMUFile *f, void *opaque, int version_id) |
378 | 23e39294 | pbrook | { |
379 | 23e39294 | pbrook | nvic_state *s = (nvic_state *)opaque; |
380 | 23e39294 | pbrook | |
381 | 23e39294 | pbrook | if (version_id != 1) |
382 | 23e39294 | pbrook | return -EINVAL;
|
383 | 23e39294 | pbrook | |
384 | 23e39294 | pbrook | s->systick.control = qemu_get_be32(f); |
385 | 23e39294 | pbrook | s->systick.reload = qemu_get_be32(f); |
386 | 23e39294 | pbrook | s->systick.tick = qemu_get_be64(f); |
387 | 23e39294 | pbrook | qemu_get_timer(f, s->systick.timer); |
388 | 23e39294 | pbrook | |
389 | 23e39294 | pbrook | return 0; |
390 | 23e39294 | pbrook | } |
391 | 23e39294 | pbrook | |
392 | 9ee6e8bb | pbrook | qemu_irq *armv7m_nvic_init(CPUState *env) |
393 | 9ee6e8bb | pbrook | { |
394 | 9ee6e8bb | pbrook | nvic_state *s; |
395 | 9ee6e8bb | pbrook | qemu_irq *parent; |
396 | 9ee6e8bb | pbrook | |
397 | 9ee6e8bb | pbrook | parent = arm_pic_init_cpu(env); |
398 | 9ee6e8bb | pbrook | s = (nvic_state *)qemu_mallocz(sizeof(nvic_state));
|
399 | 9ee6e8bb | pbrook | s->gic = gic_init(0xe000e000, &parent[ARM_PIC_CPU_IRQ]);
|
400 | 9ee6e8bb | pbrook | s->gic->nvic = s; |
401 | 9ee6e8bb | pbrook | s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s); |
402 | 9ee6e8bb | pbrook | if (env->v7m.nvic)
|
403 | 9ee6e8bb | pbrook | cpu_abort(env, "CPU can only have one NVIC\n");
|
404 | 9ee6e8bb | pbrook | env->v7m.nvic = s; |
405 | 23e39294 | pbrook | register_savevm("armv7m_nvic", -1, 1, nvic_save, nvic_load, s); |
406 | 9ee6e8bb | pbrook | return s->gic->in;
|
407 | 9ee6e8bb | pbrook | } |