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1 | 942ac052 | balrog | /*
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2 | 942ac052 | balrog | * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
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3 | 942ac052 | balrog | * USB2.0 OTG compliant core used in various chips.
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4 | 942ac052 | balrog | *
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5 | 942ac052 | balrog | * Copyright (C) 2008 Nokia Corporation
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6 | 942ac052 | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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7 | 942ac052 | balrog | *
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8 | 942ac052 | balrog | * This program is free software; you can redistribute it and/or
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9 | 942ac052 | balrog | * modify it under the terms of the GNU General Public License as
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10 | 942ac052 | balrog | * published by the Free Software Foundation; either version 2 or
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11 | 942ac052 | balrog | * (at your option) version 3 of the License.
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12 | 942ac052 | balrog | *
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13 | 942ac052 | balrog | * This program is distributed in the hope that it will be useful,
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14 | 942ac052 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | 942ac052 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 | 942ac052 | balrog | * GNU General Public License for more details.
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17 | 942ac052 | balrog | *
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18 | 942ac052 | balrog | * You should have received a copy of the GNU General Public License
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19 | 942ac052 | balrog | * along with this program; if not, write to the Free Software
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20 | 942ac052 | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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21 | 942ac052 | balrog | * MA 02111-1307 USA
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22 | 942ac052 | balrog | *
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23 | 942ac052 | balrog | * Only host-mode and non-DMA accesses are currently supported.
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24 | 942ac052 | balrog | */
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25 | 942ac052 | balrog | #include "qemu-common.h" |
26 | 942ac052 | balrog | #include "qemu-timer.h" |
27 | 942ac052 | balrog | #include "usb.h" |
28 | 942ac052 | balrog | #include "irq.h" |
29 | 942ac052 | balrog | |
30 | 942ac052 | balrog | /* Common USB registers */
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31 | 942ac052 | balrog | #define MUSB_HDRC_FADDR 0x00 /* 8-bit */ |
32 | 942ac052 | balrog | #define MUSB_HDRC_POWER 0x01 /* 8-bit */ |
33 | 942ac052 | balrog | |
34 | 942ac052 | balrog | #define MUSB_HDRC_INTRTX 0x02 /* 16-bit */ |
35 | 942ac052 | balrog | #define MUSB_HDRC_INTRRX 0x04 |
36 | 942ac052 | balrog | #define MUSB_HDRC_INTRTXE 0x06 |
37 | 942ac052 | balrog | #define MUSB_HDRC_INTRRXE 0x08 |
38 | 942ac052 | balrog | #define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */ |
39 | 942ac052 | balrog | #define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */ |
40 | 942ac052 | balrog | #define MUSB_HDRC_FRAME 0x0c /* 16-bit */ |
41 | 942ac052 | balrog | #define MUSB_HDRC_INDEX 0x0e /* 8 bit */ |
42 | 942ac052 | balrog | #define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */ |
43 | 942ac052 | balrog | |
44 | 942ac052 | balrog | /* Per-EP registers in indexed mode */
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45 | 942ac052 | balrog | #define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */ |
46 | 942ac052 | balrog | |
47 | 942ac052 | balrog | /* EP FIFOs */
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48 | 942ac052 | balrog | #define MUSB_HDRC_FIFO 0x20 |
49 | 942ac052 | balrog | |
50 | 942ac052 | balrog | /* Additional Control Registers */
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51 | 942ac052 | balrog | #define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */ |
52 | 942ac052 | balrog | |
53 | 942ac052 | balrog | /* These are indexed */
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54 | 942ac052 | balrog | #define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */ |
55 | 942ac052 | balrog | #define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */ |
56 | 942ac052 | balrog | #define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */ |
57 | 942ac052 | balrog | #define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */ |
58 | 942ac052 | balrog | |
59 | 942ac052 | balrog | /* Some more registers */
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60 | 942ac052 | balrog | #define MUSB_HDRC_VCTRL 0x68 /* 8 bit */ |
61 | 942ac052 | balrog | #define MUSB_HDRC_HWVERS 0x6c /* 8 bit */ |
62 | 942ac052 | balrog | |
63 | 942ac052 | balrog | /* Added in HDRC 1.9(?) & MHDRC 1.4 */
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64 | 942ac052 | balrog | /* ULPI pass-through */
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65 | 942ac052 | balrog | #define MUSB_HDRC_ULPI_VBUSCTL 0x70 |
66 | 942ac052 | balrog | #define MUSB_HDRC_ULPI_REGDATA 0x74 |
67 | 942ac052 | balrog | #define MUSB_HDRC_ULPI_REGADDR 0x75 |
68 | 942ac052 | balrog | #define MUSB_HDRC_ULPI_REGCTL 0x76 |
69 | 942ac052 | balrog | |
70 | 942ac052 | balrog | /* Extended config & PHY control */
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71 | 942ac052 | balrog | #define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */ |
72 | 942ac052 | balrog | #define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */ |
73 | 942ac052 | balrog | #define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */ |
74 | 942ac052 | balrog | #define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */ |
75 | 942ac052 | balrog | #define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */ |
76 | 942ac052 | balrog | #define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */ |
77 | 942ac052 | balrog | #define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */ |
78 | 942ac052 | balrog | |
79 | 942ac052 | balrog | /* Per-EP BUSCTL registers */
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80 | 942ac052 | balrog | #define MUSB_HDRC_BUSCTL 0x80 |
81 | 942ac052 | balrog | |
82 | 942ac052 | balrog | /* Per-EP registers in flat mode */
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83 | 942ac052 | balrog | #define MUSB_HDRC_EP 0x100 |
84 | 942ac052 | balrog | |
85 | 942ac052 | balrog | /* offsets to registers in flat model */
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86 | 942ac052 | balrog | #define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */ |
87 | 942ac052 | balrog | #define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */ |
88 | 942ac052 | balrog | #define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */ |
89 | 942ac052 | balrog | #define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */ |
90 | 942ac052 | balrog | #define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */ |
91 | 942ac052 | balrog | #define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */ |
92 | 942ac052 | balrog | #define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */ |
93 | 942ac052 | balrog | #define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */ |
94 | 942ac052 | balrog | #define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */ |
95 | 942ac052 | balrog | #define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */ |
96 | 942ac052 | balrog | #define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */ |
97 | 942ac052 | balrog | #define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */ |
98 | 942ac052 | balrog | #define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */ |
99 | 942ac052 | balrog | #define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */ |
100 | 942ac052 | balrog | #define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */ |
101 | 942ac052 | balrog | |
102 | 942ac052 | balrog | /* "Bus control" registers */
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103 | 942ac052 | balrog | #define MUSB_HDRC_TXFUNCADDR 0x00 |
104 | 942ac052 | balrog | #define MUSB_HDRC_TXHUBADDR 0x02 |
105 | 942ac052 | balrog | #define MUSB_HDRC_TXHUBPORT 0x03 |
106 | 942ac052 | balrog | |
107 | 942ac052 | balrog | #define MUSB_HDRC_RXFUNCADDR 0x04 |
108 | 942ac052 | balrog | #define MUSB_HDRC_RXHUBADDR 0x06 |
109 | 942ac052 | balrog | #define MUSB_HDRC_RXHUBPORT 0x07 |
110 | 942ac052 | balrog | |
111 | 942ac052 | balrog | /*
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112 | 942ac052 | balrog | * MUSBHDRC Register bit masks
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113 | 942ac052 | balrog | */
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114 | 942ac052 | balrog | |
115 | 942ac052 | balrog | /* POWER */
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116 | 942ac052 | balrog | #define MGC_M_POWER_ISOUPDATE 0x80 |
117 | 942ac052 | balrog | #define MGC_M_POWER_SOFTCONN 0x40 |
118 | 942ac052 | balrog | #define MGC_M_POWER_HSENAB 0x20 |
119 | 942ac052 | balrog | #define MGC_M_POWER_HSMODE 0x10 |
120 | 942ac052 | balrog | #define MGC_M_POWER_RESET 0x08 |
121 | 942ac052 | balrog | #define MGC_M_POWER_RESUME 0x04 |
122 | 942ac052 | balrog | #define MGC_M_POWER_SUSPENDM 0x02 |
123 | 942ac052 | balrog | #define MGC_M_POWER_ENSUSPEND 0x01 |
124 | 942ac052 | balrog | |
125 | 942ac052 | balrog | /* INTRUSB */
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126 | 942ac052 | balrog | #define MGC_M_INTR_SUSPEND 0x01 |
127 | 942ac052 | balrog | #define MGC_M_INTR_RESUME 0x02 |
128 | 942ac052 | balrog | #define MGC_M_INTR_RESET 0x04 |
129 | 942ac052 | balrog | #define MGC_M_INTR_BABBLE 0x04 |
130 | 942ac052 | balrog | #define MGC_M_INTR_SOF 0x08 |
131 | 942ac052 | balrog | #define MGC_M_INTR_CONNECT 0x10 |
132 | 942ac052 | balrog | #define MGC_M_INTR_DISCONNECT 0x20 |
133 | 942ac052 | balrog | #define MGC_M_INTR_SESSREQ 0x40 |
134 | 942ac052 | balrog | #define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */ |
135 | 942ac052 | balrog | #define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */ |
136 | 942ac052 | balrog | |
137 | 942ac052 | balrog | /* DEVCTL */
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138 | 942ac052 | balrog | #define MGC_M_DEVCTL_BDEVICE 0x80 |
139 | 942ac052 | balrog | #define MGC_M_DEVCTL_FSDEV 0x40 |
140 | 942ac052 | balrog | #define MGC_M_DEVCTL_LSDEV 0x20 |
141 | 942ac052 | balrog | #define MGC_M_DEVCTL_VBUS 0x18 |
142 | 942ac052 | balrog | #define MGC_S_DEVCTL_VBUS 3 |
143 | 942ac052 | balrog | #define MGC_M_DEVCTL_HM 0x04 |
144 | 942ac052 | balrog | #define MGC_M_DEVCTL_HR 0x02 |
145 | 942ac052 | balrog | #define MGC_M_DEVCTL_SESSION 0x01 |
146 | 942ac052 | balrog | |
147 | 942ac052 | balrog | /* TESTMODE */
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148 | 942ac052 | balrog | #define MGC_M_TEST_FORCE_HOST 0x80 |
149 | 942ac052 | balrog | #define MGC_M_TEST_FIFO_ACCESS 0x40 |
150 | 942ac052 | balrog | #define MGC_M_TEST_FORCE_FS 0x20 |
151 | 942ac052 | balrog | #define MGC_M_TEST_FORCE_HS 0x10 |
152 | 942ac052 | balrog | #define MGC_M_TEST_PACKET 0x08 |
153 | 942ac052 | balrog | #define MGC_M_TEST_K 0x04 |
154 | 942ac052 | balrog | #define MGC_M_TEST_J 0x02 |
155 | 942ac052 | balrog | #define MGC_M_TEST_SE0_NAK 0x01 |
156 | 942ac052 | balrog | |
157 | 942ac052 | balrog | /* CSR0 */
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158 | 942ac052 | balrog | #define MGC_M_CSR0_FLUSHFIFO 0x0100 |
159 | 942ac052 | balrog | #define MGC_M_CSR0_TXPKTRDY 0x0002 |
160 | 942ac052 | balrog | #define MGC_M_CSR0_RXPKTRDY 0x0001 |
161 | 942ac052 | balrog | |
162 | 942ac052 | balrog | /* CSR0 in Peripheral mode */
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163 | 942ac052 | balrog | #define MGC_M_CSR0_P_SVDSETUPEND 0x0080 |
164 | 942ac052 | balrog | #define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040 |
165 | 942ac052 | balrog | #define MGC_M_CSR0_P_SENDSTALL 0x0020 |
166 | 942ac052 | balrog | #define MGC_M_CSR0_P_SETUPEND 0x0010 |
167 | 942ac052 | balrog | #define MGC_M_CSR0_P_DATAEND 0x0008 |
168 | 942ac052 | balrog | #define MGC_M_CSR0_P_SENTSTALL 0x0004 |
169 | 942ac052 | balrog | |
170 | 942ac052 | balrog | /* CSR0 in Host mode */
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171 | 942ac052 | balrog | #define MGC_M_CSR0_H_NO_PING 0x0800 |
172 | 942ac052 | balrog | #define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */ |
173 | 942ac052 | balrog | #define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */ |
174 | 942ac052 | balrog | #define MGC_M_CSR0_H_NAKTIMEOUT 0x0080 |
175 | 942ac052 | balrog | #define MGC_M_CSR0_H_STATUSPKT 0x0040 |
176 | 942ac052 | balrog | #define MGC_M_CSR0_H_REQPKT 0x0020 |
177 | 942ac052 | balrog | #define MGC_M_CSR0_H_ERROR 0x0010 |
178 | 942ac052 | balrog | #define MGC_M_CSR0_H_SETUPPKT 0x0008 |
179 | 942ac052 | balrog | #define MGC_M_CSR0_H_RXSTALL 0x0004 |
180 | 942ac052 | balrog | |
181 | 942ac052 | balrog | /* CONFIGDATA */
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182 | 942ac052 | balrog | #define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */ |
183 | 942ac052 | balrog | #define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */ |
184 | 942ac052 | balrog | #define MGC_M_CONFIGDATA_BIGENDIAN 0x20 |
185 | 942ac052 | balrog | #define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ |
186 | 942ac052 | balrog | #define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ |
187 | 942ac052 | balrog | #define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */ |
188 | 942ac052 | balrog | #define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ |
189 | 942ac052 | balrog | #define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */ |
190 | 942ac052 | balrog | |
191 | 942ac052 | balrog | /* TXCSR in Peripheral and Host mode */
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192 | 942ac052 | balrog | #define MGC_M_TXCSR_AUTOSET 0x8000 |
193 | 942ac052 | balrog | #define MGC_M_TXCSR_ISO 0x4000 |
194 | 942ac052 | balrog | #define MGC_M_TXCSR_MODE 0x2000 |
195 | 942ac052 | balrog | #define MGC_M_TXCSR_DMAENAB 0x1000 |
196 | 942ac052 | balrog | #define MGC_M_TXCSR_FRCDATATOG 0x0800 |
197 | 942ac052 | balrog | #define MGC_M_TXCSR_DMAMODE 0x0400 |
198 | 942ac052 | balrog | #define MGC_M_TXCSR_CLRDATATOG 0x0040 |
199 | 942ac052 | balrog | #define MGC_M_TXCSR_FLUSHFIFO 0x0008 |
200 | 942ac052 | balrog | #define MGC_M_TXCSR_FIFONOTEMPTY 0x0002 |
201 | 942ac052 | balrog | #define MGC_M_TXCSR_TXPKTRDY 0x0001 |
202 | 942ac052 | balrog | |
203 | 942ac052 | balrog | /* TXCSR in Peripheral mode */
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204 | 942ac052 | balrog | #define MGC_M_TXCSR_P_INCOMPTX 0x0080 |
205 | 942ac052 | balrog | #define MGC_M_TXCSR_P_SENTSTALL 0x0020 |
206 | 942ac052 | balrog | #define MGC_M_TXCSR_P_SENDSTALL 0x0010 |
207 | 942ac052 | balrog | #define MGC_M_TXCSR_P_UNDERRUN 0x0004 |
208 | 942ac052 | balrog | |
209 | 942ac052 | balrog | /* TXCSR in Host mode */
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210 | 942ac052 | balrog | #define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200 |
211 | 942ac052 | balrog | #define MGC_M_TXCSR_H_DATATOGGLE 0x0100 |
212 | 942ac052 | balrog | #define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080 |
213 | 942ac052 | balrog | #define MGC_M_TXCSR_H_RXSTALL 0x0020 |
214 | 942ac052 | balrog | #define MGC_M_TXCSR_H_ERROR 0x0004 |
215 | 942ac052 | balrog | |
216 | 942ac052 | balrog | /* RXCSR in Peripheral and Host mode */
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217 | 942ac052 | balrog | #define MGC_M_RXCSR_AUTOCLEAR 0x8000 |
218 | 942ac052 | balrog | #define MGC_M_RXCSR_DMAENAB 0x2000 |
219 | 942ac052 | balrog | #define MGC_M_RXCSR_DISNYET 0x1000 |
220 | 942ac052 | balrog | #define MGC_M_RXCSR_DMAMODE 0x0800 |
221 | 942ac052 | balrog | #define MGC_M_RXCSR_INCOMPRX 0x0100 |
222 | 942ac052 | balrog | #define MGC_M_RXCSR_CLRDATATOG 0x0080 |
223 | 942ac052 | balrog | #define MGC_M_RXCSR_FLUSHFIFO 0x0010 |
224 | 942ac052 | balrog | #define MGC_M_RXCSR_DATAERROR 0x0008 |
225 | 942ac052 | balrog | #define MGC_M_RXCSR_FIFOFULL 0x0002 |
226 | 942ac052 | balrog | #define MGC_M_RXCSR_RXPKTRDY 0x0001 |
227 | 942ac052 | balrog | |
228 | 942ac052 | balrog | /* RXCSR in Peripheral mode */
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229 | 942ac052 | balrog | #define MGC_M_RXCSR_P_ISO 0x4000 |
230 | 942ac052 | balrog | #define MGC_M_RXCSR_P_SENTSTALL 0x0040 |
231 | 942ac052 | balrog | #define MGC_M_RXCSR_P_SENDSTALL 0x0020 |
232 | 942ac052 | balrog | #define MGC_M_RXCSR_P_OVERRUN 0x0004 |
233 | 942ac052 | balrog | |
234 | 942ac052 | balrog | /* RXCSR in Host mode */
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235 | 942ac052 | balrog | #define MGC_M_RXCSR_H_AUTOREQ 0x4000 |
236 | 942ac052 | balrog | #define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400 |
237 | 942ac052 | balrog | #define MGC_M_RXCSR_H_DATATOGGLE 0x0200 |
238 | 942ac052 | balrog | #define MGC_M_RXCSR_H_RXSTALL 0x0040 |
239 | 942ac052 | balrog | #define MGC_M_RXCSR_H_REQPKT 0x0020 |
240 | 942ac052 | balrog | #define MGC_M_RXCSR_H_ERROR 0x0004 |
241 | 942ac052 | balrog | |
242 | 942ac052 | balrog | /* HUBADDR */
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243 | 942ac052 | balrog | #define MGC_M_HUBADDR_MULTI_TT 0x80 |
244 | 942ac052 | balrog | |
245 | 942ac052 | balrog | /* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
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246 | 942ac052 | balrog | #define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02 |
247 | 942ac052 | balrog | #define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01 |
248 | 942ac052 | balrog | #define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08 |
249 | 942ac052 | balrog | #define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04 |
250 | 942ac052 | balrog | #define MGC_M_ULPI_REGCTL_COMPLETE 0x02 |
251 | 942ac052 | balrog | #define MGC_M_ULPI_REGCTL_REG 0x01 |
252 | 942ac052 | balrog | |
253 | 942ac052 | balrog | static void musb_attach(USBPort *port, USBDevice *dev); |
254 | 942ac052 | balrog | |
255 | 942ac052 | balrog | struct musb_s {
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256 | 942ac052 | balrog | qemu_irq *irqs; |
257 | 942ac052 | balrog | USBPort port; |
258 | 942ac052 | balrog | |
259 | 942ac052 | balrog | int idx;
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260 | 942ac052 | balrog | uint8_t devctl; |
261 | 942ac052 | balrog | uint8_t power; |
262 | 942ac052 | balrog | uint8_t faddr; |
263 | 942ac052 | balrog | |
264 | 942ac052 | balrog | uint8_t intr; |
265 | 942ac052 | balrog | uint8_t mask; |
266 | 942ac052 | balrog | uint16_t tx_intr; |
267 | 942ac052 | balrog | uint16_t tx_mask; |
268 | 942ac052 | balrog | uint16_t rx_intr; |
269 | 942ac052 | balrog | uint16_t rx_mask; |
270 | 942ac052 | balrog | |
271 | 942ac052 | balrog | int setup_len;
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272 | 942ac052 | balrog | int session;
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273 | 942ac052 | balrog | |
274 | 942ac052 | balrog | uint32_t buf[0x2000];
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275 | 942ac052 | balrog | |
276 | 942ac052 | balrog | struct musb_ep_s {
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277 | 942ac052 | balrog | uint16_t faddr[2];
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278 | 942ac052 | balrog | uint8_t haddr[2];
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279 | 942ac052 | balrog | uint8_t hport[2];
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280 | 942ac052 | balrog | uint16_t csr[2];
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281 | 942ac052 | balrog | uint16_t maxp[2];
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282 | 942ac052 | balrog | uint16_t rxcount; |
283 | 942ac052 | balrog | uint8_t type[2];
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284 | 942ac052 | balrog | uint8_t interval[2];
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285 | 942ac052 | balrog | uint8_t config; |
286 | 942ac052 | balrog | uint8_t fifosize; |
287 | 942ac052 | balrog | int timeout[2]; /* Always in microframes */ |
288 | 942ac052 | balrog | |
289 | 942ac052 | balrog | uint32_t *buf[2];
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290 | 942ac052 | balrog | int fifolen[2]; |
291 | 942ac052 | balrog | int fifostart[2]; |
292 | 942ac052 | balrog | int fifoaddr[2]; |
293 | 942ac052 | balrog | USBPacket packey[2];
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294 | 942ac052 | balrog | int status[2]; |
295 | 942ac052 | balrog | int ext_size[2]; |
296 | 942ac052 | balrog | |
297 | 942ac052 | balrog | /* For callbacks' use */
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298 | 942ac052 | balrog | int epnum;
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299 | 942ac052 | balrog | int interrupt[2]; |
300 | 942ac052 | balrog | struct musb_s *musb;
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301 | 942ac052 | balrog | USBCallback *delayed_cb[2];
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302 | 942ac052 | balrog | QEMUTimer *intv_timer[2];
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303 | 942ac052 | balrog | /* Duplicating the world since 2008!... probably we should have 32
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304 | 942ac052 | balrog | * logical, single endpoints instead. */
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305 | 942ac052 | balrog | } ep[16];
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306 | 942ac052 | balrog | } *musb_init(qemu_irq *irqs) |
307 | 942ac052 | balrog | { |
308 | 942ac052 | balrog | struct musb_s *s = qemu_mallocz(sizeof(*s)); |
309 | 942ac052 | balrog | int i;
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310 | 942ac052 | balrog | |
311 | 942ac052 | balrog | s->irqs = irqs; |
312 | 942ac052 | balrog | |
313 | 942ac052 | balrog | s->faddr = 0x00;
|
314 | 942ac052 | balrog | s->power = MGC_M_POWER_HSENAB; |
315 | 942ac052 | balrog | s->tx_intr = 0x0000;
|
316 | 942ac052 | balrog | s->rx_intr = 0x0000;
|
317 | 942ac052 | balrog | s->tx_mask = 0xffff;
|
318 | 942ac052 | balrog | s->rx_mask = 0xffff;
|
319 | 942ac052 | balrog | s->intr = 0x00;
|
320 | 942ac052 | balrog | s->mask = 0x06;
|
321 | 942ac052 | balrog | s->idx = 0;
|
322 | 942ac052 | balrog | |
323 | 942ac052 | balrog | /* TODO: _DW */
|
324 | 942ac052 | balrog | s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
|
325 | 942ac052 | balrog | for (i = 0; i < 16; i ++) { |
326 | 942ac052 | balrog | s->ep[i].fifosize = 64;
|
327 | 942ac052 | balrog | s->ep[i].maxp[0] = 0x40; |
328 | 942ac052 | balrog | s->ep[i].maxp[1] = 0x40; |
329 | 942ac052 | balrog | s->ep[i].musb = s; |
330 | 942ac052 | balrog | s->ep[i].epnum = i; |
331 | 942ac052 | balrog | } |
332 | 942ac052 | balrog | |
333 | 942ac052 | balrog | qemu_register_usb_port(&s->port, s, 0, musb_attach);
|
334 | 942ac052 | balrog | |
335 | 942ac052 | balrog | return s;
|
336 | 942ac052 | balrog | } |
337 | 942ac052 | balrog | |
338 | 942ac052 | balrog | static void musb_vbus_set(struct musb_s *s, int level) |
339 | 942ac052 | balrog | { |
340 | 942ac052 | balrog | if (level)
|
341 | 942ac052 | balrog | s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
|
342 | 942ac052 | balrog | else
|
343 | 942ac052 | balrog | s->devctl &= ~MGC_M_DEVCTL_VBUS; |
344 | 942ac052 | balrog | |
345 | 942ac052 | balrog | qemu_set_irq(s->irqs[musb_set_vbus], level); |
346 | 942ac052 | balrog | } |
347 | 942ac052 | balrog | |
348 | 942ac052 | balrog | static void musb_intr_set(struct musb_s *s, int line, int level) |
349 | 942ac052 | balrog | { |
350 | 942ac052 | balrog | if (!level) {
|
351 | 942ac052 | balrog | s->intr &= ~(1 << line);
|
352 | 942ac052 | balrog | qemu_irq_lower(s->irqs[line]); |
353 | 942ac052 | balrog | } else if (s->mask & (1 << line)) { |
354 | 942ac052 | balrog | s->intr |= 1 << line;
|
355 | 942ac052 | balrog | qemu_irq_raise(s->irqs[line]); |
356 | 942ac052 | balrog | } |
357 | 942ac052 | balrog | } |
358 | 942ac052 | balrog | |
359 | 942ac052 | balrog | static void musb_tx_intr_set(struct musb_s *s, int line, int level) |
360 | 942ac052 | balrog | { |
361 | 942ac052 | balrog | if (!level) {
|
362 | 942ac052 | balrog | s->tx_intr &= ~(1 << line);
|
363 | 942ac052 | balrog | if (!s->tx_intr)
|
364 | 942ac052 | balrog | qemu_irq_lower(s->irqs[musb_irq_tx]); |
365 | 942ac052 | balrog | } else if (s->tx_mask & (1 << line)) { |
366 | 942ac052 | balrog | s->tx_intr |= 1 << line;
|
367 | 942ac052 | balrog | qemu_irq_raise(s->irqs[musb_irq_tx]); |
368 | 942ac052 | balrog | } |
369 | 942ac052 | balrog | } |
370 | 942ac052 | balrog | |
371 | 942ac052 | balrog | static void musb_rx_intr_set(struct musb_s *s, int line, int level) |
372 | 942ac052 | balrog | { |
373 | 942ac052 | balrog | if (line) {
|
374 | 942ac052 | balrog | if (!level) {
|
375 | 942ac052 | balrog | s->rx_intr &= ~(1 << line);
|
376 | 942ac052 | balrog | if (!s->rx_intr)
|
377 | 942ac052 | balrog | qemu_irq_lower(s->irqs[musb_irq_rx]); |
378 | 942ac052 | balrog | } else if (s->rx_mask & (1 << line)) { |
379 | 942ac052 | balrog | s->rx_intr |= 1 << line;
|
380 | 942ac052 | balrog | qemu_irq_raise(s->irqs[musb_irq_rx]); |
381 | 942ac052 | balrog | } |
382 | 942ac052 | balrog | } else
|
383 | 942ac052 | balrog | musb_tx_intr_set(s, line, level); |
384 | 942ac052 | balrog | } |
385 | 942ac052 | balrog | |
386 | 942ac052 | balrog | uint32_t musb_core_intr_get(struct musb_s *s)
|
387 | 942ac052 | balrog | { |
388 | 942ac052 | balrog | return (s->rx_intr << 15) | s->tx_intr; |
389 | 942ac052 | balrog | } |
390 | 942ac052 | balrog | |
391 | 942ac052 | balrog | void musb_core_intr_clear(struct musb_s *s, uint32_t mask) |
392 | 942ac052 | balrog | { |
393 | 942ac052 | balrog | if (s->rx_intr) {
|
394 | 942ac052 | balrog | s->rx_intr &= mask >> 15;
|
395 | 942ac052 | balrog | if (!s->rx_intr)
|
396 | 942ac052 | balrog | qemu_irq_lower(s->irqs[musb_irq_rx]); |
397 | 942ac052 | balrog | } |
398 | 942ac052 | balrog | |
399 | 942ac052 | balrog | if (s->tx_intr) {
|
400 | 942ac052 | balrog | s->tx_intr &= mask & 0xffff;
|
401 | 942ac052 | balrog | if (!s->tx_intr)
|
402 | 942ac052 | balrog | qemu_irq_lower(s->irqs[musb_irq_tx]); |
403 | 942ac052 | balrog | } |
404 | 942ac052 | balrog | } |
405 | 942ac052 | balrog | |
406 | 942ac052 | balrog | void musb_set_size(struct musb_s *s, int epnum, int size, int is_tx) |
407 | 942ac052 | balrog | { |
408 | 942ac052 | balrog | s->ep[epnum].ext_size[!is_tx] = size; |
409 | 942ac052 | balrog | s->ep[epnum].fifostart[0] = 0; |
410 | 942ac052 | balrog | s->ep[epnum].fifostart[1] = 0; |
411 | 942ac052 | balrog | s->ep[epnum].fifolen[0] = 0; |
412 | 942ac052 | balrog | s->ep[epnum].fifolen[1] = 0; |
413 | 942ac052 | balrog | } |
414 | 942ac052 | balrog | |
415 | 942ac052 | balrog | static void musb_session_update(struct musb_s *s, int prev_dev, int prev_sess) |
416 | 942ac052 | balrog | { |
417 | 942ac052 | balrog | int detect_prev = prev_dev && prev_sess;
|
418 | 942ac052 | balrog | int detect = !!s->port.dev && s->session;
|
419 | 942ac052 | balrog | |
420 | 942ac052 | balrog | if (detect && !detect_prev) {
|
421 | 942ac052 | balrog | /* Let's skip the ID pin sense and VBUS sense formalities and
|
422 | 942ac052 | balrog | * and signal a successful SRP directly. This should work at least
|
423 | 942ac052 | balrog | * for the Linux driver stack. */
|
424 | 942ac052 | balrog | musb_intr_set(s, musb_irq_connect, 1);
|
425 | 942ac052 | balrog | |
426 | 942ac052 | balrog | if (s->port.dev->speed == USB_SPEED_LOW) {
|
427 | 942ac052 | balrog | s->devctl &= ~MGC_M_DEVCTL_FSDEV; |
428 | 942ac052 | balrog | s->devctl |= MGC_M_DEVCTL_LSDEV; |
429 | 942ac052 | balrog | } else {
|
430 | 942ac052 | balrog | s->devctl |= MGC_M_DEVCTL_FSDEV; |
431 | 942ac052 | balrog | s->devctl &= ~MGC_M_DEVCTL_LSDEV; |
432 | 942ac052 | balrog | } |
433 | 942ac052 | balrog | |
434 | 942ac052 | balrog | /* A-mode? */
|
435 | 942ac052 | balrog | s->devctl &= ~MGC_M_DEVCTL_BDEVICE; |
436 | 942ac052 | balrog | |
437 | 942ac052 | balrog | /* Host-mode bit? */
|
438 | 942ac052 | balrog | s->devctl |= MGC_M_DEVCTL_HM; |
439 | 942ac052 | balrog | #if 1 |
440 | 942ac052 | balrog | musb_vbus_set(s, 1);
|
441 | 942ac052 | balrog | #endif
|
442 | 942ac052 | balrog | } else if (!detect && detect_prev) { |
443 | 942ac052 | balrog | #if 1 |
444 | 942ac052 | balrog | musb_vbus_set(s, 0);
|
445 | 942ac052 | balrog | #endif
|
446 | 942ac052 | balrog | } |
447 | 942ac052 | balrog | } |
448 | 942ac052 | balrog | |
449 | 942ac052 | balrog | /* Attach or detach a device on our only port. */
|
450 | 942ac052 | balrog | static void musb_attach(USBPort *port, USBDevice *dev) |
451 | 942ac052 | balrog | { |
452 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) port->opaque; |
453 | 942ac052 | balrog | USBDevice *curr; |
454 | 942ac052 | balrog | |
455 | 942ac052 | balrog | port = &s->port; |
456 | 942ac052 | balrog | curr = port->dev; |
457 | 942ac052 | balrog | |
458 | 942ac052 | balrog | if (dev) {
|
459 | 942ac052 | balrog | if (curr) {
|
460 | 942ac052 | balrog | usb_attach(port, NULL);
|
461 | 942ac052 | balrog | /* TODO: signal some interrupts */
|
462 | 942ac052 | balrog | } |
463 | 942ac052 | balrog | |
464 | 942ac052 | balrog | musb_intr_set(s, musb_irq_vbus_request, 1);
|
465 | 942ac052 | balrog | |
466 | 942ac052 | balrog | /* Send the attach message to device */
|
467 | 942ac052 | balrog | usb_send_msg(dev, USB_MSG_ATTACH); |
468 | 942ac052 | balrog | } else if (curr) { |
469 | 942ac052 | balrog | /* Send the detach message */
|
470 | 942ac052 | balrog | usb_send_msg(curr, USB_MSG_DETACH); |
471 | 942ac052 | balrog | |
472 | 942ac052 | balrog | musb_intr_set(s, musb_irq_disconnect, 1);
|
473 | 942ac052 | balrog | } |
474 | 942ac052 | balrog | |
475 | 942ac052 | balrog | port->dev = dev; |
476 | 942ac052 | balrog | |
477 | 942ac052 | balrog | musb_session_update(s, !!curr, s->session); |
478 | 942ac052 | balrog | } |
479 | 942ac052 | balrog | |
480 | 942ac052 | balrog | static inline void musb_cb_tick0(void *opaque) |
481 | 942ac052 | balrog | { |
482 | 942ac052 | balrog | struct musb_ep_s *ep = (struct musb_ep_s *) opaque; |
483 | 942ac052 | balrog | |
484 | 942ac052 | balrog | ep->delayed_cb[0](&ep->packey[0], opaque); |
485 | 942ac052 | balrog | } |
486 | 942ac052 | balrog | |
487 | 942ac052 | balrog | static inline void musb_cb_tick1(void *opaque) |
488 | 942ac052 | balrog | { |
489 | 942ac052 | balrog | struct musb_ep_s *ep = (struct musb_ep_s *) opaque; |
490 | 942ac052 | balrog | |
491 | 942ac052 | balrog | ep->delayed_cb[1](&ep->packey[1], opaque); |
492 | 942ac052 | balrog | } |
493 | 942ac052 | balrog | |
494 | 942ac052 | balrog | #define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
|
495 | 942ac052 | balrog | |
496 | 942ac052 | balrog | static inline void musb_schedule_cb(USBPacket *packey, void *opaque, int dir) |
497 | 942ac052 | balrog | { |
498 | 942ac052 | balrog | struct musb_ep_s *ep = (struct musb_ep_s *) opaque; |
499 | 942ac052 | balrog | int timeout = 0; |
500 | 942ac052 | balrog | |
501 | 942ac052 | balrog | if (ep->status[dir] == USB_RET_NAK)
|
502 | 942ac052 | balrog | timeout = ep->timeout[dir]; |
503 | 942ac052 | balrog | else if (ep->interrupt[dir]) |
504 | 942ac052 | balrog | timeout = 8;
|
505 | 942ac052 | balrog | else
|
506 | 942ac052 | balrog | return musb_cb_tick(opaque);
|
507 | 942ac052 | balrog | |
508 | 942ac052 | balrog | if (!ep->intv_timer[dir])
|
509 | 942ac052 | balrog | ep->intv_timer[dir] = qemu_new_timer(vm_clock, musb_cb_tick, opaque); |
510 | 942ac052 | balrog | |
511 | 942ac052 | balrog | qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock(vm_clock) + |
512 | 942ac052 | balrog | muldiv64(timeout, ticks_per_sec, 8000));
|
513 | 942ac052 | balrog | } |
514 | 942ac052 | balrog | |
515 | 942ac052 | balrog | static void musb_schedule0_cb(USBPacket *packey, void *opaque) |
516 | 942ac052 | balrog | { |
517 | 942ac052 | balrog | return musb_schedule_cb(packey, opaque, 0); |
518 | 942ac052 | balrog | } |
519 | 942ac052 | balrog | |
520 | 942ac052 | balrog | static void musb_schedule1_cb(USBPacket *packey, void *opaque) |
521 | 942ac052 | balrog | { |
522 | 942ac052 | balrog | return musb_schedule_cb(packey, opaque, 1); |
523 | 942ac052 | balrog | } |
524 | 942ac052 | balrog | |
525 | 942ac052 | balrog | static int musb_timeout(int ttype, int speed, int val) |
526 | 942ac052 | balrog | { |
527 | 942ac052 | balrog | #if 1 |
528 | 942ac052 | balrog | return val << 3; |
529 | 942ac052 | balrog | #endif
|
530 | 942ac052 | balrog | |
531 | 942ac052 | balrog | switch (ttype) {
|
532 | 942ac052 | balrog | case USB_ENDPOINT_XFER_CONTROL:
|
533 | 942ac052 | balrog | if (val < 2) |
534 | 942ac052 | balrog | return 0; |
535 | 942ac052 | balrog | else if (speed == USB_SPEED_HIGH) |
536 | 942ac052 | balrog | return 1 << (val - 1); |
537 | 942ac052 | balrog | else
|
538 | 942ac052 | balrog | return 8 << (val - 1); |
539 | 942ac052 | balrog | |
540 | 942ac052 | balrog | case USB_ENDPOINT_XFER_INT:
|
541 | 942ac052 | balrog | if (speed == USB_SPEED_HIGH)
|
542 | 942ac052 | balrog | if (val < 2) |
543 | 942ac052 | balrog | return 0; |
544 | 942ac052 | balrog | else
|
545 | 942ac052 | balrog | return 1 << (val - 1); |
546 | 942ac052 | balrog | else
|
547 | 942ac052 | balrog | return val << 3; |
548 | 942ac052 | balrog | |
549 | 942ac052 | balrog | case USB_ENDPOINT_XFER_BULK:
|
550 | 942ac052 | balrog | case USB_ENDPOINT_XFER_ISOC:
|
551 | 942ac052 | balrog | if (val < 2) |
552 | 942ac052 | balrog | return 0; |
553 | 942ac052 | balrog | else if (speed == USB_SPEED_HIGH) |
554 | 942ac052 | balrog | return 1 << (val - 1); |
555 | 942ac052 | balrog | else
|
556 | 942ac052 | balrog | return 8 << (val - 1); |
557 | 942ac052 | balrog | /* TODO: what with low-speed Bulk and Isochronous? */
|
558 | 942ac052 | balrog | } |
559 | 942ac052 | balrog | |
560 | 942ac052 | balrog | cpu_abort(cpu_single_env, "bad interval\n");
|
561 | 942ac052 | balrog | } |
562 | 942ac052 | balrog | |
563 | 942ac052 | balrog | static inline void musb_packet(struct musb_s *s, struct musb_ep_s *ep, |
564 | 942ac052 | balrog | int epnum, int pid, int len, USBCallback cb, int dir) |
565 | 942ac052 | balrog | { |
566 | 942ac052 | balrog | int ret;
|
567 | 942ac052 | balrog | int idx = epnum && dir;
|
568 | 942ac052 | balrog | int ttype;
|
569 | 942ac052 | balrog | |
570 | 942ac052 | balrog | /* ep->type[0,1] contains:
|
571 | 942ac052 | balrog | * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
|
572 | 942ac052 | balrog | * in bits 5:4 the transfer type (BULK / INT)
|
573 | 942ac052 | balrog | * in bits 3:0 the EP num
|
574 | 942ac052 | balrog | */
|
575 | 942ac052 | balrog | ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0; |
576 | 942ac052 | balrog | |
577 | 942ac052 | balrog | ep->timeout[dir] = musb_timeout(ttype, |
578 | 942ac052 | balrog | ep->type[idx] >> 6, ep->interval[idx]);
|
579 | 942ac052 | balrog | ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT; |
580 | 942ac052 | balrog | ep->delayed_cb[dir] = cb; |
581 | 942ac052 | balrog | cb = dir ? musb_schedule1_cb : musb_schedule0_cb; |
582 | 942ac052 | balrog | |
583 | 942ac052 | balrog | ep->packey[dir].pid = pid; |
584 | 942ac052 | balrog | /* A wild guess on the FADDR semantics... */
|
585 | 942ac052 | balrog | ep->packey[dir].devaddr = ep->faddr[idx]; |
586 | 942ac052 | balrog | ep->packey[dir].devep = ep->type[idx] & 0xf;
|
587 | 942ac052 | balrog | ep->packey[dir].data = (void *) ep->buf[idx];
|
588 | 942ac052 | balrog | ep->packey[dir].len = len; |
589 | 942ac052 | balrog | ep->packey[dir].complete_cb = cb; |
590 | 942ac052 | balrog | ep->packey[dir].complete_opaque = ep; |
591 | 942ac052 | balrog | |
592 | 942ac052 | balrog | if (s->port.dev)
|
593 | 942ac052 | balrog | ret = s->port.dev->handle_packet(s->port.dev, &ep->packey[dir]); |
594 | 942ac052 | balrog | else
|
595 | 942ac052 | balrog | ret = USB_RET_NODEV; |
596 | 942ac052 | balrog | |
597 | 942ac052 | balrog | if (ret == USB_RET_ASYNC) {
|
598 | 942ac052 | balrog | ep->status[dir] = len; |
599 | 942ac052 | balrog | return;
|
600 | 942ac052 | balrog | } |
601 | 942ac052 | balrog | |
602 | 942ac052 | balrog | ep->status[dir] = ret; |
603 | 942ac052 | balrog | usb_packet_complete(&ep->packey[dir]); |
604 | 942ac052 | balrog | } |
605 | 942ac052 | balrog | |
606 | 942ac052 | balrog | static void musb_tx_packet_complete(USBPacket *packey, void *opaque) |
607 | 942ac052 | balrog | { |
608 | 942ac052 | balrog | /* Unfortunately we can't use packey->devep because that's the remote
|
609 | 942ac052 | balrog | * endpoint number and may be different than our local. */
|
610 | 942ac052 | balrog | struct musb_ep_s *ep = (struct musb_ep_s *) opaque; |
611 | 942ac052 | balrog | int epnum = ep->epnum;
|
612 | 942ac052 | balrog | struct musb_s *s = ep->musb;
|
613 | 942ac052 | balrog | |
614 | 942ac052 | balrog | ep->fifostart[0] = 0; |
615 | 942ac052 | balrog | ep->fifolen[0] = 0; |
616 | 942ac052 | balrog | #ifdef CLEAR_NAK
|
617 | 942ac052 | balrog | if (ep->status[0] != USB_RET_NAK) { |
618 | 942ac052 | balrog | #endif
|
619 | 942ac052 | balrog | if (epnum)
|
620 | 942ac052 | balrog | ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
|
621 | 942ac052 | balrog | else
|
622 | 942ac052 | balrog | ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
|
623 | 942ac052 | balrog | #ifdef CLEAR_NAK
|
624 | 942ac052 | balrog | } |
625 | 942ac052 | balrog | #endif
|
626 | 942ac052 | balrog | |
627 | 942ac052 | balrog | /* Clear all of the error bits first */
|
628 | 942ac052 | balrog | if (epnum)
|
629 | 942ac052 | balrog | ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
|
630 | 942ac052 | balrog | MGC_M_TXCSR_H_NAKTIMEOUT); |
631 | 942ac052 | balrog | else
|
632 | 942ac052 | balrog | ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
|
633 | 942ac052 | balrog | MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING); |
634 | 942ac052 | balrog | |
635 | 942ac052 | balrog | if (ep->status[0] == USB_RET_STALL) { |
636 | 942ac052 | balrog | /* Command not supported by target! */
|
637 | 942ac052 | balrog | ep->status[0] = 0; |
638 | 942ac052 | balrog | |
639 | 942ac052 | balrog | if (epnum)
|
640 | 942ac052 | balrog | ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
|
641 | 942ac052 | balrog | else
|
642 | 942ac052 | balrog | ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
|
643 | 942ac052 | balrog | } |
644 | 942ac052 | balrog | |
645 | 942ac052 | balrog | if (ep->status[0] == USB_RET_NAK) { |
646 | 942ac052 | balrog | ep->status[0] = 0; |
647 | 942ac052 | balrog | |
648 | 942ac052 | balrog | /* NAK timeouts are only generated in Bulk transfers and
|
649 | 942ac052 | balrog | * Data-errors in Isochronous. */
|
650 | 942ac052 | balrog | if (ep->interrupt[0]) { |
651 | 942ac052 | balrog | return;
|
652 | 942ac052 | balrog | } |
653 | 942ac052 | balrog | |
654 | 942ac052 | balrog | if (epnum)
|
655 | 942ac052 | balrog | ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
|
656 | 942ac052 | balrog | else
|
657 | 942ac052 | balrog | ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
|
658 | 942ac052 | balrog | } |
659 | 942ac052 | balrog | |
660 | 942ac052 | balrog | if (ep->status[0] < 0) { |
661 | 942ac052 | balrog | if (ep->status[0] == USB_RET_BABBLE) |
662 | 942ac052 | balrog | musb_intr_set(s, musb_irq_rst_babble, 1);
|
663 | 942ac052 | balrog | |
664 | 942ac052 | balrog | /* Pretend we've tried three times already and failed (in
|
665 | 942ac052 | balrog | * case of USB_TOKEN_SETUP). */
|
666 | 942ac052 | balrog | if (epnum)
|
667 | 942ac052 | balrog | ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
|
668 | 942ac052 | balrog | else
|
669 | 942ac052 | balrog | ep->csr[0] |= MGC_M_CSR0_H_ERROR;
|
670 | 942ac052 | balrog | |
671 | 942ac052 | balrog | musb_tx_intr_set(s, epnum, 1);
|
672 | 942ac052 | balrog | return;
|
673 | 942ac052 | balrog | } |
674 | 942ac052 | balrog | /* TODO: check len for over/underruns of an OUT packet? */
|
675 | 942ac052 | balrog | |
676 | 942ac052 | balrog | #ifdef SETUPLEN_HACK
|
677 | 942ac052 | balrog | if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP) |
678 | 942ac052 | balrog | s->setup_len = ep->packey[0].data[6]; |
679 | 942ac052 | balrog | #endif
|
680 | 942ac052 | balrog | |
681 | 942ac052 | balrog | /* In DMA mode: if no error, assert DMA request for this EP,
|
682 | 942ac052 | balrog | * and skip the interrupt. */
|
683 | 942ac052 | balrog | musb_tx_intr_set(s, epnum, 1);
|
684 | 942ac052 | balrog | } |
685 | 942ac052 | balrog | |
686 | 942ac052 | balrog | static void musb_rx_packet_complete(USBPacket *packey, void *opaque) |
687 | 942ac052 | balrog | { |
688 | 942ac052 | balrog | /* Unfortunately we can't use packey->devep because that's the remote
|
689 | 942ac052 | balrog | * endpoint number and may be different than our local. */
|
690 | 942ac052 | balrog | struct musb_ep_s *ep = (struct musb_ep_s *) opaque; |
691 | 942ac052 | balrog | int epnum = ep->epnum;
|
692 | 942ac052 | balrog | struct musb_s *s = ep->musb;
|
693 | 942ac052 | balrog | |
694 | 942ac052 | balrog | ep->fifostart[1] = 0; |
695 | 942ac052 | balrog | ep->fifolen[1] = 0; |
696 | 942ac052 | balrog | |
697 | 942ac052 | balrog | #ifdef CLEAR_NAK
|
698 | 942ac052 | balrog | if (ep->status[1] != USB_RET_NAK) { |
699 | 942ac052 | balrog | #endif
|
700 | 942ac052 | balrog | ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
|
701 | 942ac052 | balrog | if (!epnum)
|
702 | 942ac052 | balrog | ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
|
703 | 942ac052 | balrog | #ifdef CLEAR_NAK
|
704 | 942ac052 | balrog | } |
705 | 942ac052 | balrog | #endif
|
706 | 942ac052 | balrog | |
707 | 942ac052 | balrog | /* Clear all of the imaginable error bits first */
|
708 | 942ac052 | balrog | ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
|
709 | 942ac052 | balrog | MGC_M_RXCSR_DATAERROR); |
710 | 942ac052 | balrog | if (!epnum)
|
711 | 942ac052 | balrog | ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
|
712 | 942ac052 | balrog | MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING); |
713 | 942ac052 | balrog | |
714 | 942ac052 | balrog | if (ep->status[1] == USB_RET_STALL) { |
715 | 942ac052 | balrog | ep->status[1] = 0; |
716 | 942ac052 | balrog | packey->len = 0;
|
717 | 942ac052 | balrog | |
718 | 942ac052 | balrog | ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
|
719 | 942ac052 | balrog | if (!epnum)
|
720 | 942ac052 | balrog | ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
|
721 | 942ac052 | balrog | } |
722 | 942ac052 | balrog | |
723 | 942ac052 | balrog | if (ep->status[1] == USB_RET_NAK) { |
724 | 942ac052 | balrog | ep->status[1] = 0; |
725 | 942ac052 | balrog | |
726 | 942ac052 | balrog | /* NAK timeouts are only generated in Bulk transfers and
|
727 | 942ac052 | balrog | * Data-errors in Isochronous. */
|
728 | 942ac052 | balrog | if (ep->interrupt[1]) |
729 | 942ac052 | balrog | return musb_packet(s, ep, epnum, USB_TOKEN_IN,
|
730 | 942ac052 | balrog | packey->len, musb_rx_packet_complete, 1);
|
731 | 942ac052 | balrog | |
732 | 942ac052 | balrog | ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
|
733 | 942ac052 | balrog | if (!epnum)
|
734 | 942ac052 | balrog | ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
|
735 | 942ac052 | balrog | } |
736 | 942ac052 | balrog | |
737 | 942ac052 | balrog | if (ep->status[1] < 0) { |
738 | 942ac052 | balrog | if (ep->status[1] == USB_RET_BABBLE) { |
739 | 942ac052 | balrog | musb_intr_set(s, musb_irq_rst_babble, 1);
|
740 | 942ac052 | balrog | return;
|
741 | 942ac052 | balrog | } |
742 | 942ac052 | balrog | |
743 | 942ac052 | balrog | /* Pretend we've tried three times already and failed (in
|
744 | 942ac052 | balrog | * case of a control transfer). */
|
745 | 942ac052 | balrog | ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
|
746 | 942ac052 | balrog | if (!epnum)
|
747 | 942ac052 | balrog | ep->csr[0] |= MGC_M_CSR0_H_ERROR;
|
748 | 942ac052 | balrog | |
749 | 942ac052 | balrog | musb_rx_intr_set(s, epnum, 1);
|
750 | 942ac052 | balrog | return;
|
751 | 942ac052 | balrog | } |
752 | 942ac052 | balrog | /* TODO: check len for over/underruns of an OUT packet? */
|
753 | 942ac052 | balrog | /* TODO: perhaps make use of e->ext_size[1] here. */
|
754 | 942ac052 | balrog | |
755 | 942ac052 | balrog | packey->len = ep->status[1];
|
756 | 942ac052 | balrog | |
757 | 942ac052 | balrog | if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) { |
758 | 942ac052 | balrog | ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
|
759 | 942ac052 | balrog | if (!epnum)
|
760 | 942ac052 | balrog | ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
|
761 | 942ac052 | balrog | |
762 | 942ac052 | balrog | ep->rxcount = packey->len; /* XXX: MIN(packey->len, ep->maxp[1]); */
|
763 | 942ac052 | balrog | /* In DMA mode: assert DMA request for this EP */
|
764 | 942ac052 | balrog | } |
765 | 942ac052 | balrog | |
766 | 942ac052 | balrog | /* Only if DMA has not been asserted */
|
767 | 942ac052 | balrog | musb_rx_intr_set(s, epnum, 1);
|
768 | 942ac052 | balrog | } |
769 | 942ac052 | balrog | |
770 | 942ac052 | balrog | static void musb_tx_rdy(struct musb_s *s, int epnum) |
771 | 942ac052 | balrog | { |
772 | 942ac052 | balrog | struct musb_ep_s *ep = s->ep + epnum;
|
773 | 942ac052 | balrog | int pid;
|
774 | 942ac052 | balrog | int total, valid = 0; |
775 | 942ac052 | balrog | |
776 | 942ac052 | balrog | ep->fifostart[0] += ep->fifolen[0]; |
777 | 942ac052 | balrog | ep->fifolen[0] = 0; |
778 | 942ac052 | balrog | |
779 | 942ac052 | balrog | /* XXX: how's the total size of the packet retrieved exactly in
|
780 | 942ac052 | balrog | * the generic case? */
|
781 | 942ac052 | balrog | total = ep->maxp[0] & 0x3ff; |
782 | 942ac052 | balrog | |
783 | 942ac052 | balrog | if (ep->ext_size[0]) { |
784 | 942ac052 | balrog | total = ep->ext_size[0];
|
785 | 942ac052 | balrog | ep->ext_size[0] = 0; |
786 | 942ac052 | balrog | valid = 1;
|
787 | 942ac052 | balrog | } |
788 | 942ac052 | balrog | |
789 | 942ac052 | balrog | /* If the packet is not fully ready yet, wait for a next segment. */
|
790 | 942ac052 | balrog | if (epnum && (ep->fifostart[0] << 2) < total) |
791 | 942ac052 | balrog | return;
|
792 | 942ac052 | balrog | |
793 | 942ac052 | balrog | if (!valid)
|
794 | 942ac052 | balrog | total = ep->fifostart[0] << 2; |
795 | 942ac052 | balrog | |
796 | 942ac052 | balrog | pid = USB_TOKEN_OUT; |
797 | 942ac052 | balrog | if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) { |
798 | 942ac052 | balrog | pid = USB_TOKEN_SETUP; |
799 | 942ac052 | balrog | if (total != 8) |
800 | 942ac052 | balrog | printf("%s: illegal SETUPPKT length of %i bytes\n",
|
801 | 942ac052 | balrog | __FUNCTION__, total); |
802 | 942ac052 | balrog | /* Controller should retry SETUP packets three times on errors
|
803 | 942ac052 | balrog | * but it doesn't make sense for us to do that. */
|
804 | 942ac052 | balrog | } |
805 | 942ac052 | balrog | |
806 | 942ac052 | balrog | return musb_packet(s, ep, epnum, pid,
|
807 | 942ac052 | balrog | total, musb_tx_packet_complete, 0);
|
808 | 942ac052 | balrog | } |
809 | 942ac052 | balrog | |
810 | 942ac052 | balrog | static void musb_rx_req(struct musb_s *s, int epnum) |
811 | 942ac052 | balrog | { |
812 | 942ac052 | balrog | struct musb_ep_s *ep = s->ep + epnum;
|
813 | 942ac052 | balrog | int total;
|
814 | 942ac052 | balrog | |
815 | 942ac052 | balrog | /* If we already have a packet, which didn't fit into the
|
816 | 942ac052 | balrog | * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
|
817 | 942ac052 | balrog | if (ep->packey[1].pid == USB_TOKEN_IN && ep->status[1] >= 0 && |
818 | 942ac052 | balrog | (ep->fifostart[1] << 2) + ep->rxcount < |
819 | 942ac052 | balrog | ep->packey[1].len) {
|
820 | 942ac052 | balrog | ep->fifostart[1] += ep->rxcount >> 2; |
821 | 942ac052 | balrog | ep->fifolen[1] = 0; |
822 | 942ac052 | balrog | |
823 | 942ac052 | balrog | ep->rxcount = MIN(ep->packey[0].len - (ep->fifostart[1] << 2), |
824 | 942ac052 | balrog | ep->maxp[1]);
|
825 | 942ac052 | balrog | |
826 | 942ac052 | balrog | ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
|
827 | 942ac052 | balrog | if (!epnum)
|
828 | 942ac052 | balrog | ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
|
829 | 942ac052 | balrog | |
830 | 942ac052 | balrog | /* Clear all of the error bits first */
|
831 | 942ac052 | balrog | ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
|
832 | 942ac052 | balrog | MGC_M_RXCSR_DATAERROR); |
833 | 942ac052 | balrog | if (!epnum)
|
834 | 942ac052 | balrog | ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
|
835 | 942ac052 | balrog | MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING); |
836 | 942ac052 | balrog | |
837 | 942ac052 | balrog | ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
|
838 | 942ac052 | balrog | if (!epnum)
|
839 | 942ac052 | balrog | ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
|
840 | 942ac052 | balrog | musb_rx_intr_set(s, epnum, 1);
|
841 | 942ac052 | balrog | return;
|
842 | 942ac052 | balrog | } |
843 | 942ac052 | balrog | |
844 | 942ac052 | balrog | /* The driver sets maxp[1] to 64 or less because it knows the hardware
|
845 | 942ac052 | balrog | * FIFO is this deep. Bigger packets get split in
|
846 | 942ac052 | balrog | * usb_generic_handle_packet but we can also do the splitting locally
|
847 | 942ac052 | balrog | * for performance. It turns out we can also have a bigger FIFO and
|
848 | 942ac052 | balrog | * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
|
849 | 942ac052 | balrog | * OK with single packets of even 32KB and we avoid splitting, however
|
850 | 942ac052 | balrog | * usb_msd.c sometimes sends a packet bigger than what Linux expects
|
851 | 942ac052 | balrog | * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
|
852 | 942ac052 | balrog | * hides this overrun from Linux. Up to 4096 everything is fine
|
853 | 942ac052 | balrog | * though. Currently this is disabled.
|
854 | 942ac052 | balrog | *
|
855 | 942ac052 | balrog | * XXX: mind ep->fifosize. */
|
856 | 942ac052 | balrog | total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf)); |
857 | 942ac052 | balrog | |
858 | 942ac052 | balrog | #ifdef SETUPLEN_HACK
|
859 | 942ac052 | balrog | /* Why should *we* do that instead of Linux? */
|
860 | 942ac052 | balrog | if (!epnum) {
|
861 | 942ac052 | balrog | if (ep->packey[0].devaddr == 2) |
862 | 942ac052 | balrog | total = MIN(s->setup_len, 8);
|
863 | 942ac052 | balrog | else
|
864 | 942ac052 | balrog | total = MIN(s->setup_len, 64);
|
865 | 942ac052 | balrog | s->setup_len -= total; |
866 | 942ac052 | balrog | } |
867 | 942ac052 | balrog | #endif
|
868 | 942ac052 | balrog | |
869 | 942ac052 | balrog | return musb_packet(s, ep, epnum, USB_TOKEN_IN,
|
870 | 942ac052 | balrog | total, musb_rx_packet_complete, 1);
|
871 | 942ac052 | balrog | } |
872 | 942ac052 | balrog | |
873 | 942ac052 | balrog | static void musb_ep_frame_cancel(struct musb_ep_s *ep, int dir) |
874 | 942ac052 | balrog | { |
875 | 942ac052 | balrog | if (ep->intv_timer[dir])
|
876 | 942ac052 | balrog | qemu_del_timer(ep->intv_timer[dir]); |
877 | 942ac052 | balrog | } |
878 | 942ac052 | balrog | |
879 | 942ac052 | balrog | /* Bus control */
|
880 | 942ac052 | balrog | static uint8_t musb_busctl_readb(void *opaque, int ep, int addr) |
881 | 942ac052 | balrog | { |
882 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
883 | 942ac052 | balrog | |
884 | 942ac052 | balrog | switch (addr) {
|
885 | 942ac052 | balrog | /* For USB2.0 HS hubs only */
|
886 | 942ac052 | balrog | case MUSB_HDRC_TXHUBADDR:
|
887 | 942ac052 | balrog | return s->ep[ep].haddr[0]; |
888 | 942ac052 | balrog | case MUSB_HDRC_TXHUBPORT:
|
889 | 942ac052 | balrog | return s->ep[ep].hport[0]; |
890 | 942ac052 | balrog | case MUSB_HDRC_RXHUBADDR:
|
891 | 942ac052 | balrog | return s->ep[ep].haddr[1]; |
892 | 942ac052 | balrog | case MUSB_HDRC_RXHUBPORT:
|
893 | 942ac052 | balrog | return s->ep[ep].hport[1]; |
894 | 942ac052 | balrog | |
895 | 942ac052 | balrog | default:
|
896 | 942ac052 | balrog | printf("%s: unknown register at %02x\n", __FUNCTION__, addr);
|
897 | 942ac052 | balrog | return 0x00; |
898 | 942ac052 | balrog | }; |
899 | 942ac052 | balrog | } |
900 | 942ac052 | balrog | |
901 | 942ac052 | balrog | static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value) |
902 | 942ac052 | balrog | { |
903 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
904 | 942ac052 | balrog | |
905 | 942ac052 | balrog | switch (addr) {
|
906 | 942ac052 | balrog | case MUSB_HDRC_TXHUBADDR:
|
907 | 942ac052 | balrog | s->ep[ep].haddr[0] = value;
|
908 | 942ac052 | balrog | break;
|
909 | 942ac052 | balrog | case MUSB_HDRC_TXHUBPORT:
|
910 | 942ac052 | balrog | s->ep[ep].hport[0] = value;
|
911 | 942ac052 | balrog | break;
|
912 | 942ac052 | balrog | case MUSB_HDRC_RXHUBADDR:
|
913 | 942ac052 | balrog | s->ep[ep].haddr[1] = value;
|
914 | 942ac052 | balrog | break;
|
915 | 942ac052 | balrog | case MUSB_HDRC_RXHUBPORT:
|
916 | 942ac052 | balrog | s->ep[ep].hport[1] = value;
|
917 | 942ac052 | balrog | break;
|
918 | 942ac052 | balrog | |
919 | 942ac052 | balrog | default:
|
920 | 942ac052 | balrog | printf("%s: unknown register at %02x\n", __FUNCTION__, addr);
|
921 | 942ac052 | balrog | }; |
922 | 942ac052 | balrog | } |
923 | 942ac052 | balrog | |
924 | 942ac052 | balrog | static uint16_t musb_busctl_readh(void *opaque, int ep, int addr) |
925 | 942ac052 | balrog | { |
926 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
927 | 942ac052 | balrog | |
928 | 942ac052 | balrog | switch (addr) {
|
929 | 942ac052 | balrog | case MUSB_HDRC_TXFUNCADDR:
|
930 | 942ac052 | balrog | return s->ep[ep].faddr[0]; |
931 | 942ac052 | balrog | case MUSB_HDRC_RXFUNCADDR:
|
932 | 942ac052 | balrog | return s->ep[ep].faddr[1]; |
933 | 942ac052 | balrog | |
934 | 942ac052 | balrog | default:
|
935 | 942ac052 | balrog | return musb_busctl_readb(s, ep, addr) |
|
936 | 942ac052 | balrog | (musb_busctl_readb(s, ep, addr | 1) << 8); |
937 | 942ac052 | balrog | }; |
938 | 942ac052 | balrog | } |
939 | 942ac052 | balrog | |
940 | 942ac052 | balrog | static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value) |
941 | 942ac052 | balrog | { |
942 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
943 | 942ac052 | balrog | |
944 | 942ac052 | balrog | switch (addr) {
|
945 | 942ac052 | balrog | case MUSB_HDRC_TXFUNCADDR:
|
946 | 942ac052 | balrog | s->ep[ep].faddr[0] = value;
|
947 | 942ac052 | balrog | break;
|
948 | 942ac052 | balrog | case MUSB_HDRC_RXFUNCADDR:
|
949 | 942ac052 | balrog | s->ep[ep].faddr[1] = value;
|
950 | 942ac052 | balrog | break;
|
951 | 942ac052 | balrog | |
952 | 942ac052 | balrog | default:
|
953 | 942ac052 | balrog | musb_busctl_writeb(s, ep, addr, value & 0xff);
|
954 | 942ac052 | balrog | musb_busctl_writeb(s, ep, addr | 1, value >> 8); |
955 | 942ac052 | balrog | }; |
956 | 942ac052 | balrog | } |
957 | 942ac052 | balrog | |
958 | 942ac052 | balrog | /* Endpoint control */
|
959 | 942ac052 | balrog | static uint8_t musb_ep_readb(void *opaque, int ep, int addr) |
960 | 942ac052 | balrog | { |
961 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
962 | 942ac052 | balrog | |
963 | 942ac052 | balrog | switch (addr) {
|
964 | 942ac052 | balrog | case MUSB_HDRC_TXTYPE:
|
965 | 942ac052 | balrog | return s->ep[ep].type[0]; |
966 | 942ac052 | balrog | case MUSB_HDRC_TXINTERVAL:
|
967 | 942ac052 | balrog | return s->ep[ep].interval[0]; |
968 | 942ac052 | balrog | case MUSB_HDRC_RXTYPE:
|
969 | 942ac052 | balrog | return s->ep[ep].type[1]; |
970 | 942ac052 | balrog | case MUSB_HDRC_RXINTERVAL:
|
971 | 942ac052 | balrog | return s->ep[ep].interval[1]; |
972 | 942ac052 | balrog | case (MUSB_HDRC_FIFOSIZE & ~1): |
973 | 942ac052 | balrog | return 0x00; |
974 | 942ac052 | balrog | case MUSB_HDRC_FIFOSIZE:
|
975 | 942ac052 | balrog | return ep ? s->ep[ep].fifosize : s->ep[ep].config;
|
976 | 942ac052 | balrog | |
977 | 942ac052 | balrog | default:
|
978 | 942ac052 | balrog | printf("%s: unknown register at %02x\n", __FUNCTION__, addr);
|
979 | 942ac052 | balrog | return 0x00; |
980 | 942ac052 | balrog | }; |
981 | 942ac052 | balrog | } |
982 | 942ac052 | balrog | |
983 | 942ac052 | balrog | static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value) |
984 | 942ac052 | balrog | { |
985 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
986 | 942ac052 | balrog | |
987 | 942ac052 | balrog | switch (addr) {
|
988 | 942ac052 | balrog | case MUSB_HDRC_TXTYPE:
|
989 | 942ac052 | balrog | s->ep[ep].type[0] = value;
|
990 | 942ac052 | balrog | break;
|
991 | 942ac052 | balrog | case MUSB_HDRC_TXINTERVAL:
|
992 | 942ac052 | balrog | s->ep[ep].interval[0] = value;
|
993 | 942ac052 | balrog | musb_ep_frame_cancel(&s->ep[ep], 0);
|
994 | 942ac052 | balrog | break;
|
995 | 942ac052 | balrog | case MUSB_HDRC_RXTYPE:
|
996 | 942ac052 | balrog | s->ep[ep].type[1] = value;
|
997 | 942ac052 | balrog | break;
|
998 | 942ac052 | balrog | case MUSB_HDRC_RXINTERVAL:
|
999 | 942ac052 | balrog | s->ep[ep].interval[1] = value;
|
1000 | 942ac052 | balrog | musb_ep_frame_cancel(&s->ep[ep], 1);
|
1001 | 942ac052 | balrog | break;
|
1002 | 942ac052 | balrog | case (MUSB_HDRC_FIFOSIZE & ~1): |
1003 | 942ac052 | balrog | break;
|
1004 | 942ac052 | balrog | case MUSB_HDRC_FIFOSIZE:
|
1005 | 942ac052 | balrog | printf("%s: somebody messes with fifosize (now %i bytes)\n",
|
1006 | 942ac052 | balrog | __FUNCTION__, value); |
1007 | 942ac052 | balrog | s->ep[ep].fifosize = value; |
1008 | 942ac052 | balrog | break;
|
1009 | 942ac052 | balrog | |
1010 | 942ac052 | balrog | default:
|
1011 | 942ac052 | balrog | printf("%s: unknown register at %02x\n", __FUNCTION__, addr);
|
1012 | 942ac052 | balrog | }; |
1013 | 942ac052 | balrog | } |
1014 | 942ac052 | balrog | |
1015 | 942ac052 | balrog | static uint16_t musb_ep_readh(void *opaque, int ep, int addr) |
1016 | 942ac052 | balrog | { |
1017 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
1018 | 942ac052 | balrog | uint16_t ret; |
1019 | 942ac052 | balrog | |
1020 | 942ac052 | balrog | switch (addr) {
|
1021 | 942ac052 | balrog | case MUSB_HDRC_TXMAXP:
|
1022 | 942ac052 | balrog | return s->ep[ep].maxp[0]; |
1023 | 942ac052 | balrog | case MUSB_HDRC_TXCSR:
|
1024 | 942ac052 | balrog | return s->ep[ep].csr[0]; |
1025 | 942ac052 | balrog | case MUSB_HDRC_RXMAXP:
|
1026 | 942ac052 | balrog | return s->ep[ep].maxp[1]; |
1027 | 942ac052 | balrog | case MUSB_HDRC_RXCSR:
|
1028 | 942ac052 | balrog | ret = s->ep[ep].csr[1];
|
1029 | 942ac052 | balrog | |
1030 | 942ac052 | balrog | /* TODO: This and other bits probably depend on
|
1031 | 942ac052 | balrog | * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
|
1032 | 942ac052 | balrog | if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR) |
1033 | 942ac052 | balrog | s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
|
1034 | 942ac052 | balrog | |
1035 | 942ac052 | balrog | return ret;
|
1036 | 942ac052 | balrog | case MUSB_HDRC_RXCOUNT:
|
1037 | 942ac052 | balrog | return s->ep[ep].rxcount;
|
1038 | 942ac052 | balrog | |
1039 | 942ac052 | balrog | default:
|
1040 | 942ac052 | balrog | return musb_ep_readb(s, ep, addr) |
|
1041 | 942ac052 | balrog | (musb_ep_readb(s, ep, addr | 1) << 8); |
1042 | 942ac052 | balrog | }; |
1043 | 942ac052 | balrog | } |
1044 | 942ac052 | balrog | |
1045 | 942ac052 | balrog | static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value) |
1046 | 942ac052 | balrog | { |
1047 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
1048 | 942ac052 | balrog | |
1049 | 942ac052 | balrog | switch (addr) {
|
1050 | 942ac052 | balrog | case MUSB_HDRC_TXMAXP:
|
1051 | 942ac052 | balrog | s->ep[ep].maxp[0] = value;
|
1052 | 942ac052 | balrog | break;
|
1053 | 942ac052 | balrog | case MUSB_HDRC_TXCSR:
|
1054 | 942ac052 | balrog | if (ep) {
|
1055 | 942ac052 | balrog | s->ep[ep].csr[0] &= value & 0xa6; |
1056 | 942ac052 | balrog | s->ep[ep].csr[0] |= value & 0xff59; |
1057 | 942ac052 | balrog | } else {
|
1058 | 942ac052 | balrog | s->ep[ep].csr[0] &= value & 0x85; |
1059 | 942ac052 | balrog | s->ep[ep].csr[0] |= value & 0xf7a; |
1060 | 942ac052 | balrog | } |
1061 | 942ac052 | balrog | |
1062 | 942ac052 | balrog | musb_ep_frame_cancel(&s->ep[ep], 0);
|
1063 | 942ac052 | balrog | |
1064 | 942ac052 | balrog | if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
|
1065 | 942ac052 | balrog | (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) { |
1066 | 942ac052 | balrog | s->ep[ep].fifolen[0] = 0; |
1067 | 942ac052 | balrog | s->ep[ep].fifostart[0] = 0; |
1068 | 942ac052 | balrog | if (ep)
|
1069 | 942ac052 | balrog | s->ep[ep].csr[0] &=
|
1070 | 942ac052 | balrog | ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY); |
1071 | 942ac052 | balrog | else
|
1072 | 942ac052 | balrog | s->ep[ep].csr[0] &=
|
1073 | 942ac052 | balrog | ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY); |
1074 | 942ac052 | balrog | } |
1075 | 942ac052 | balrog | if (
|
1076 | 942ac052 | balrog | (ep && |
1077 | 942ac052 | balrog | #ifdef CLEAR_NAK
|
1078 | 942ac052 | balrog | (value & MGC_M_TXCSR_TXPKTRDY) && |
1079 | 942ac052 | balrog | !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) || |
1080 | 942ac052 | balrog | #else
|
1081 | 942ac052 | balrog | (value & MGC_M_TXCSR_TXPKTRDY)) || |
1082 | 942ac052 | balrog | #endif
|
1083 | 942ac052 | balrog | (!ep && |
1084 | 942ac052 | balrog | #ifdef CLEAR_NAK
|
1085 | 942ac052 | balrog | (value & MGC_M_CSR0_TXPKTRDY) && |
1086 | 942ac052 | balrog | !(value & MGC_M_CSR0_H_NAKTIMEOUT))) |
1087 | 942ac052 | balrog | #else
|
1088 | 942ac052 | balrog | (value & MGC_M_CSR0_TXPKTRDY))) |
1089 | 942ac052 | balrog | #endif
|
1090 | 942ac052 | balrog | musb_tx_rdy(s, ep); |
1091 | 942ac052 | balrog | if (!ep &&
|
1092 | 942ac052 | balrog | (value & MGC_M_CSR0_H_REQPKT) && |
1093 | 942ac052 | balrog | #ifdef CLEAR_NAK
|
1094 | 942ac052 | balrog | !(value & (MGC_M_CSR0_H_NAKTIMEOUT | |
1095 | 942ac052 | balrog | MGC_M_CSR0_RXPKTRDY))) |
1096 | 942ac052 | balrog | #else
|
1097 | 942ac052 | balrog | !(value & MGC_M_CSR0_RXPKTRDY)) |
1098 | 942ac052 | balrog | #endif
|
1099 | 942ac052 | balrog | musb_rx_req(s, ep); |
1100 | 942ac052 | balrog | break;
|
1101 | 942ac052 | balrog | |
1102 | 942ac052 | balrog | case MUSB_HDRC_RXMAXP:
|
1103 | 942ac052 | balrog | s->ep[ep].maxp[1] = value;
|
1104 | 942ac052 | balrog | break;
|
1105 | 942ac052 | balrog | case MUSB_HDRC_RXCSR:
|
1106 | 942ac052 | balrog | /* (DMA mode only) */
|
1107 | 942ac052 | balrog | if (
|
1108 | 942ac052 | balrog | (value & MGC_M_RXCSR_H_AUTOREQ) && |
1109 | 942ac052 | balrog | !(value & MGC_M_RXCSR_RXPKTRDY) && |
1110 | 942ac052 | balrog | (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
|
1111 | 942ac052 | balrog | value |= MGC_M_RXCSR_H_REQPKT; |
1112 | 942ac052 | balrog | |
1113 | 942ac052 | balrog | s->ep[ep].csr[1] &= 0x102 | (value & 0x4d); |
1114 | 942ac052 | balrog | s->ep[ep].csr[1] |= value & 0xfeb0; |
1115 | 942ac052 | balrog | |
1116 | 942ac052 | balrog | musb_ep_frame_cancel(&s->ep[ep], 1);
|
1117 | 942ac052 | balrog | |
1118 | 942ac052 | balrog | if (value & MGC_M_RXCSR_FLUSHFIFO) {
|
1119 | 942ac052 | balrog | s->ep[ep].fifolen[1] = 0; |
1120 | 942ac052 | balrog | s->ep[ep].fifostart[1] = 0; |
1121 | 942ac052 | balrog | s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
|
1122 | 942ac052 | balrog | /* If double buffering and we have two packets ready, flush
|
1123 | 942ac052 | balrog | * only the first one and set up the fifo at the second packet. */
|
1124 | 942ac052 | balrog | } |
1125 | 942ac052 | balrog | #ifdef CLEAR_NAK
|
1126 | 942ac052 | balrog | if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
|
1127 | 942ac052 | balrog | #else
|
1128 | 942ac052 | balrog | if (value & MGC_M_RXCSR_H_REQPKT)
|
1129 | 942ac052 | balrog | #endif
|
1130 | 942ac052 | balrog | musb_rx_req(s, ep); |
1131 | 942ac052 | balrog | break;
|
1132 | 942ac052 | balrog | case MUSB_HDRC_RXCOUNT:
|
1133 | 942ac052 | balrog | s->ep[ep].rxcount = value; |
1134 | 942ac052 | balrog | break;
|
1135 | 942ac052 | balrog | |
1136 | 942ac052 | balrog | default:
|
1137 | 942ac052 | balrog | musb_ep_writeb(s, ep, addr, value & 0xff);
|
1138 | 942ac052 | balrog | musb_ep_writeb(s, ep, addr | 1, value >> 8); |
1139 | 942ac052 | balrog | }; |
1140 | 942ac052 | balrog | } |
1141 | 942ac052 | balrog | |
1142 | 942ac052 | balrog | /* Generic control */
|
1143 | 942ac052 | balrog | static uint32_t musb_readb(void *opaque, target_phys_addr_t addr) |
1144 | 942ac052 | balrog | { |
1145 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
1146 | 942ac052 | balrog | int ep, i;
|
1147 | 942ac052 | balrog | uint8_t ret; |
1148 | 942ac052 | balrog | |
1149 | 942ac052 | balrog | switch (addr) {
|
1150 | 942ac052 | balrog | case MUSB_HDRC_FADDR:
|
1151 | 942ac052 | balrog | return s->faddr;
|
1152 | 942ac052 | balrog | case MUSB_HDRC_POWER:
|
1153 | 942ac052 | balrog | return s->power;
|
1154 | 942ac052 | balrog | case MUSB_HDRC_INTRUSB:
|
1155 | 942ac052 | balrog | ret = s->intr; |
1156 | 942ac052 | balrog | for (i = 0; i < sizeof(ret) * 8; i ++) |
1157 | 942ac052 | balrog | if (ret & (1 << i)) |
1158 | 942ac052 | balrog | musb_intr_set(s, i, 0);
|
1159 | 942ac052 | balrog | return ret;
|
1160 | 942ac052 | balrog | case MUSB_HDRC_INTRUSBE:
|
1161 | 942ac052 | balrog | return s->mask;
|
1162 | 942ac052 | balrog | case MUSB_HDRC_INDEX:
|
1163 | 942ac052 | balrog | return s->idx;
|
1164 | 942ac052 | balrog | case MUSB_HDRC_TESTMODE:
|
1165 | 942ac052 | balrog | return 0x00; |
1166 | 942ac052 | balrog | |
1167 | 942ac052 | balrog | case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf): |
1168 | 942ac052 | balrog | return musb_ep_readb(s, s->idx, addr & 0xf); |
1169 | 942ac052 | balrog | |
1170 | 942ac052 | balrog | case MUSB_HDRC_DEVCTL:
|
1171 | 942ac052 | balrog | return s->devctl;
|
1172 | 942ac052 | balrog | |
1173 | 942ac052 | balrog | case MUSB_HDRC_TXFIFOSZ:
|
1174 | 942ac052 | balrog | case MUSB_HDRC_RXFIFOSZ:
|
1175 | 942ac052 | balrog | case MUSB_HDRC_VCTRL:
|
1176 | 942ac052 | balrog | /* TODO */
|
1177 | 942ac052 | balrog | return 0x00; |
1178 | 942ac052 | balrog | |
1179 | 942ac052 | balrog | case MUSB_HDRC_HWVERS:
|
1180 | 942ac052 | balrog | return (1 << 10) | 400; |
1181 | 942ac052 | balrog | |
1182 | 942ac052 | balrog | case (MUSB_HDRC_VCTRL | 1): |
1183 | 942ac052 | balrog | case (MUSB_HDRC_HWVERS | 1): |
1184 | 942ac052 | balrog | case (MUSB_HDRC_DEVCTL | 1): |
1185 | 942ac052 | balrog | return 0x00; |
1186 | 942ac052 | balrog | |
1187 | 942ac052 | balrog | case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f): |
1188 | 942ac052 | balrog | ep = (addr >> 3) & 0xf; |
1189 | 942ac052 | balrog | return musb_busctl_readb(s, ep, addr & 0x7); |
1190 | 942ac052 | balrog | |
1191 | 942ac052 | balrog | case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff): |
1192 | 942ac052 | balrog | ep = (addr >> 4) & 0xf; |
1193 | 942ac052 | balrog | return musb_ep_readb(s, ep, addr & 0xf); |
1194 | 942ac052 | balrog | |
1195 | 942ac052 | balrog | default:
|
1196 | 942ac052 | balrog | printf("%s: unknown register at %02x\n", __FUNCTION__, (int) addr); |
1197 | 942ac052 | balrog | return 0x00; |
1198 | 942ac052 | balrog | }; |
1199 | 942ac052 | balrog | } |
1200 | 942ac052 | balrog | |
1201 | 942ac052 | balrog | static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
1202 | 942ac052 | balrog | { |
1203 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
1204 | 942ac052 | balrog | int ep;
|
1205 | 942ac052 | balrog | |
1206 | 942ac052 | balrog | switch (addr) {
|
1207 | 942ac052 | balrog | case MUSB_HDRC_FADDR:
|
1208 | 942ac052 | balrog | s->faddr = value & 0x7f;
|
1209 | 942ac052 | balrog | break;
|
1210 | 942ac052 | balrog | case MUSB_HDRC_POWER:
|
1211 | 942ac052 | balrog | s->power = (value & 0xef) | (s->power & 0x10); |
1212 | 942ac052 | balrog | /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
|
1213 | 942ac052 | balrog | if ((value & MGC_M_POWER_RESET) && s->port.dev) {
|
1214 | 942ac052 | balrog | usb_send_msg(s->port.dev, USB_MSG_RESET); |
1215 | 942ac052 | balrog | /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
|
1216 | 942ac052 | balrog | if ((value & MGC_M_POWER_HSENAB) &&
|
1217 | 942ac052 | balrog | s->port.dev->speed == USB_SPEED_HIGH) |
1218 | 942ac052 | balrog | s->power |= MGC_M_POWER_HSMODE; /* Success */
|
1219 | 942ac052 | balrog | /* Restart frame counting. */
|
1220 | 942ac052 | balrog | } |
1221 | 942ac052 | balrog | if (value & MGC_M_POWER_SUSPENDM) {
|
1222 | 942ac052 | balrog | /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
|
1223 | 942ac052 | balrog | * is set, also go into low power mode. Frame counting stops. */
|
1224 | 942ac052 | balrog | /* XXX: Cleared when the interrupt register is read */
|
1225 | 942ac052 | balrog | } |
1226 | 942ac052 | balrog | if (value & MGC_M_POWER_RESUME) {
|
1227 | 942ac052 | balrog | /* Wait 20ms and signal resuming on the bus. Frame counting
|
1228 | 942ac052 | balrog | * restarts. */
|
1229 | 942ac052 | balrog | } |
1230 | 942ac052 | balrog | break;
|
1231 | 942ac052 | balrog | case MUSB_HDRC_INTRUSB:
|
1232 | 942ac052 | balrog | break;
|
1233 | 942ac052 | balrog | case MUSB_HDRC_INTRUSBE:
|
1234 | 942ac052 | balrog | s->mask = value & 0xff;
|
1235 | 942ac052 | balrog | break;
|
1236 | 942ac052 | balrog | case MUSB_HDRC_INDEX:
|
1237 | 942ac052 | balrog | s->idx = value & 0xf;
|
1238 | 942ac052 | balrog | break;
|
1239 | 942ac052 | balrog | case MUSB_HDRC_TESTMODE:
|
1240 | 942ac052 | balrog | break;
|
1241 | 942ac052 | balrog | |
1242 | 942ac052 | balrog | case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf): |
1243 | 942ac052 | balrog | musb_ep_writeb(s, s->idx, addr & 0xf, value);
|
1244 | 942ac052 | balrog | break;
|
1245 | 942ac052 | balrog | |
1246 | 942ac052 | balrog | case MUSB_HDRC_DEVCTL:
|
1247 | 942ac052 | balrog | s->session = !!(value & MGC_M_DEVCTL_SESSION); |
1248 | 942ac052 | balrog | musb_session_update(s, |
1249 | 942ac052 | balrog | !!s->port.dev, |
1250 | 942ac052 | balrog | !!(s->devctl & MGC_M_DEVCTL_SESSION)); |
1251 | 942ac052 | balrog | |
1252 | 942ac052 | balrog | /* It seems this is the only R/W bit in this register? */
|
1253 | 942ac052 | balrog | s->devctl &= ~MGC_M_DEVCTL_SESSION; |
1254 | 942ac052 | balrog | s->devctl |= value & MGC_M_DEVCTL_SESSION; |
1255 | 942ac052 | balrog | break;
|
1256 | 942ac052 | balrog | |
1257 | 942ac052 | balrog | case MUSB_HDRC_TXFIFOSZ:
|
1258 | 942ac052 | balrog | case MUSB_HDRC_RXFIFOSZ:
|
1259 | 942ac052 | balrog | case MUSB_HDRC_VCTRL:
|
1260 | 942ac052 | balrog | /* TODO */
|
1261 | 942ac052 | balrog | break;
|
1262 | 942ac052 | balrog | |
1263 | 942ac052 | balrog | case (MUSB_HDRC_VCTRL | 1): |
1264 | 942ac052 | balrog | case (MUSB_HDRC_DEVCTL | 1): |
1265 | 942ac052 | balrog | break;
|
1266 | 942ac052 | balrog | |
1267 | 942ac052 | balrog | case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f): |
1268 | 942ac052 | balrog | ep = (addr >> 3) & 0xf; |
1269 | 942ac052 | balrog | musb_busctl_writeb(s, ep, addr & 0x7, value);
|
1270 | 942ac052 | balrog | break;
|
1271 | 942ac052 | balrog | |
1272 | 942ac052 | balrog | case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff): |
1273 | 942ac052 | balrog | ep = (addr >> 4) & 0xf; |
1274 | 942ac052 | balrog | musb_ep_writeb(s, ep, addr & 0xf, value);
|
1275 | 942ac052 | balrog | break;
|
1276 | 942ac052 | balrog | |
1277 | 942ac052 | balrog | default:
|
1278 | 942ac052 | balrog | printf("%s: unknown register at %02x\n", __FUNCTION__, (int) addr); |
1279 | 942ac052 | balrog | }; |
1280 | 942ac052 | balrog | } |
1281 | 942ac052 | balrog | |
1282 | 942ac052 | balrog | static uint32_t musb_readh(void *opaque, target_phys_addr_t addr) |
1283 | 942ac052 | balrog | { |
1284 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
1285 | 942ac052 | balrog | int ep, i;
|
1286 | 942ac052 | balrog | uint16_t ret; |
1287 | 942ac052 | balrog | |
1288 | 942ac052 | balrog | switch (addr) {
|
1289 | 942ac052 | balrog | case MUSB_HDRC_INTRTX:
|
1290 | 942ac052 | balrog | ret = s->tx_intr; |
1291 | 942ac052 | balrog | /* Auto clear */
|
1292 | 942ac052 | balrog | for (i = 0; i < sizeof(ret) * 8; i ++) |
1293 | 942ac052 | balrog | if (ret & (1 << i)) |
1294 | 942ac052 | balrog | musb_tx_intr_set(s, i, 0);
|
1295 | 942ac052 | balrog | return ret;
|
1296 | 942ac052 | balrog | case MUSB_HDRC_INTRRX:
|
1297 | 942ac052 | balrog | ret = s->rx_intr; |
1298 | 942ac052 | balrog | /* Auto clear */
|
1299 | 942ac052 | balrog | for (i = 0; i < sizeof(ret) * 8; i ++) |
1300 | 942ac052 | balrog | if (ret & (1 << i)) |
1301 | 942ac052 | balrog | musb_rx_intr_set(s, i, 0);
|
1302 | 942ac052 | balrog | return ret;
|
1303 | 942ac052 | balrog | case MUSB_HDRC_INTRTXE:
|
1304 | 942ac052 | balrog | return s->tx_mask;
|
1305 | 942ac052 | balrog | case MUSB_HDRC_INTRRXE:
|
1306 | 942ac052 | balrog | return s->rx_mask;
|
1307 | 942ac052 | balrog | |
1308 | 942ac052 | balrog | case MUSB_HDRC_FRAME:
|
1309 | 942ac052 | balrog | /* TODO */
|
1310 | 942ac052 | balrog | return 0x0000; |
1311 | 942ac052 | balrog | case MUSB_HDRC_TXFIFOADDR:
|
1312 | 942ac052 | balrog | return s->ep[s->idx].fifoaddr[0]; |
1313 | 942ac052 | balrog | case MUSB_HDRC_RXFIFOADDR:
|
1314 | 942ac052 | balrog | return s->ep[s->idx].fifoaddr[1]; |
1315 | 942ac052 | balrog | |
1316 | 942ac052 | balrog | case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf): |
1317 | 942ac052 | balrog | return musb_ep_readh(s, s->idx, addr & 0xf); |
1318 | 942ac052 | balrog | |
1319 | 942ac052 | balrog | case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f): |
1320 | 942ac052 | balrog | ep = (addr >> 3) & 0xf; |
1321 | 942ac052 | balrog | return musb_busctl_readh(s, ep, addr & 0x7); |
1322 | 942ac052 | balrog | |
1323 | 942ac052 | balrog | case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff): |
1324 | 942ac052 | balrog | ep = (addr >> 4) & 0xf; |
1325 | 942ac052 | balrog | return musb_ep_readh(s, ep, addr & 0xf); |
1326 | 942ac052 | balrog | |
1327 | 942ac052 | balrog | default:
|
1328 | 942ac052 | balrog | return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8); |
1329 | 942ac052 | balrog | }; |
1330 | 942ac052 | balrog | } |
1331 | 942ac052 | balrog | |
1332 | 942ac052 | balrog | static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) |
1333 | 942ac052 | balrog | { |
1334 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
1335 | 942ac052 | balrog | int ep;
|
1336 | 942ac052 | balrog | |
1337 | 942ac052 | balrog | switch (addr) {
|
1338 | 942ac052 | balrog | case MUSB_HDRC_INTRTXE:
|
1339 | 942ac052 | balrog | s->tx_mask = value; |
1340 | 942ac052 | balrog | /* XXX: the masks seem to apply on the raising edge like with
|
1341 | 942ac052 | balrog | * edge-triggered interrupts, thus no need to update. I may be
|
1342 | 942ac052 | balrog | * wrong though. */
|
1343 | 942ac052 | balrog | break;
|
1344 | 942ac052 | balrog | case MUSB_HDRC_INTRRXE:
|
1345 | 942ac052 | balrog | s->rx_mask = value; |
1346 | 942ac052 | balrog | break;
|
1347 | 942ac052 | balrog | |
1348 | 942ac052 | balrog | case MUSB_HDRC_FRAME:
|
1349 | 942ac052 | balrog | /* TODO */
|
1350 | 942ac052 | balrog | break;
|
1351 | 942ac052 | balrog | case MUSB_HDRC_TXFIFOADDR:
|
1352 | 942ac052 | balrog | s->ep[s->idx].fifoaddr[0] = value;
|
1353 | 942ac052 | balrog | s->ep[s->idx].buf[0] =
|
1354 | 942ac052 | balrog | s->buf + ((value << 1) & (sizeof(s->buf) / 4 - 1)); |
1355 | 942ac052 | balrog | break;
|
1356 | 942ac052 | balrog | case MUSB_HDRC_RXFIFOADDR:
|
1357 | 942ac052 | balrog | s->ep[s->idx].fifoaddr[1] = value;
|
1358 | 942ac052 | balrog | s->ep[s->idx].buf[1] =
|
1359 | 942ac052 | balrog | s->buf + ((value << 1) & (sizeof(s->buf) / 4 - 1)); |
1360 | 942ac052 | balrog | break;
|
1361 | 942ac052 | balrog | |
1362 | 942ac052 | balrog | case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf): |
1363 | 942ac052 | balrog | musb_ep_writeh(s, s->idx, addr & 0xf, value);
|
1364 | 942ac052 | balrog | break;
|
1365 | 942ac052 | balrog | |
1366 | 942ac052 | balrog | case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f): |
1367 | 942ac052 | balrog | ep = (addr >> 3) & 0xf; |
1368 | 942ac052 | balrog | musb_busctl_writeh(s, ep, addr & 0x7, value);
|
1369 | 942ac052 | balrog | break;
|
1370 | 942ac052 | balrog | |
1371 | 942ac052 | balrog | case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff): |
1372 | 942ac052 | balrog | ep = (addr >> 4) & 0xf; |
1373 | 942ac052 | balrog | musb_ep_writeh(s, ep, addr & 0xf, value);
|
1374 | 942ac052 | balrog | break;
|
1375 | 942ac052 | balrog | |
1376 | 942ac052 | balrog | default:
|
1377 | 942ac052 | balrog | musb_writeb(s, addr, value & 0xff);
|
1378 | 942ac052 | balrog | musb_writeb(s, addr | 1, value >> 8); |
1379 | 942ac052 | balrog | }; |
1380 | 942ac052 | balrog | } |
1381 | 942ac052 | balrog | |
1382 | 942ac052 | balrog | static uint32_t musb_readw(void *opaque, target_phys_addr_t addr) |
1383 | 942ac052 | balrog | { |
1384 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
1385 | 942ac052 | balrog | struct musb_ep_s *ep;
|
1386 | 942ac052 | balrog | int epnum;
|
1387 | 942ac052 | balrog | |
1388 | 942ac052 | balrog | switch (addr) {
|
1389 | 942ac052 | balrog | case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f): |
1390 | 942ac052 | balrog | epnum = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf; |
1391 | 942ac052 | balrog | ep = s->ep + epnum; |
1392 | 942ac052 | balrog | |
1393 | 942ac052 | balrog | if (ep->fifolen[1] >= 16) { |
1394 | 942ac052 | balrog | /* We have a FIFO underrun */
|
1395 | 942ac052 | balrog | printf("%s: EP%i FIFO is now empty, stop reading\n",
|
1396 | 942ac052 | balrog | __FUNCTION__, epnum); |
1397 | 942ac052 | balrog | return 0x00000000; |
1398 | 942ac052 | balrog | } |
1399 | 942ac052 | balrog | /* In DMA mode clear RXPKTRDY and set REQPKT automatically
|
1400 | 942ac052 | balrog | * (if AUTOREQ is set) */
|
1401 | 942ac052 | balrog | |
1402 | 942ac052 | balrog | ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
|
1403 | 942ac052 | balrog | return ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++]; |
1404 | 942ac052 | balrog | |
1405 | 942ac052 | balrog | default:
|
1406 | 942ac052 | balrog | printf("%s: unknown register at %02x\n", __FUNCTION__, (int) addr); |
1407 | 942ac052 | balrog | return 0x00000000; |
1408 | 942ac052 | balrog | }; |
1409 | 942ac052 | balrog | } |
1410 | 942ac052 | balrog | |
1411 | 942ac052 | balrog | static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value) |
1412 | 942ac052 | balrog | { |
1413 | 942ac052 | balrog | struct musb_s *s = (struct musb_s *) opaque; |
1414 | 942ac052 | balrog | struct musb_ep_s *ep;
|
1415 | 942ac052 | balrog | int epnum;
|
1416 | 942ac052 | balrog | |
1417 | 942ac052 | balrog | switch (addr) {
|
1418 | 942ac052 | balrog | case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f): |
1419 | 942ac052 | balrog | epnum = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf; |
1420 | 942ac052 | balrog | ep = s->ep + epnum; |
1421 | 942ac052 | balrog | |
1422 | 942ac052 | balrog | if (ep->fifolen[0] >= 16) { |
1423 | 942ac052 | balrog | /* We have a FIFO overrun */
|
1424 | 942ac052 | balrog | printf("%s: EP%i FIFO exceeded 64 bytes, stop feeding data\n",
|
1425 | 942ac052 | balrog | __FUNCTION__, epnum); |
1426 | 942ac052 | balrog | break;
|
1427 | 942ac052 | balrog | } |
1428 | 942ac052 | balrog | |
1429 | 942ac052 | balrog | ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value; |
1430 | 942ac052 | balrog | if (epnum)
|
1431 | 942ac052 | balrog | ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
|
1432 | 942ac052 | balrog | break;
|
1433 | 942ac052 | balrog | |
1434 | 942ac052 | balrog | default:
|
1435 | 942ac052 | balrog | printf("%s: unknown register at %02x\n", __FUNCTION__, (int) addr); |
1436 | 942ac052 | balrog | }; |
1437 | 942ac052 | balrog | } |
1438 | 942ac052 | balrog | |
1439 | 942ac052 | balrog | CPUReadMemoryFunc *musb_read[] = { |
1440 | 942ac052 | balrog | musb_readb, |
1441 | 942ac052 | balrog | musb_readh, |
1442 | 942ac052 | balrog | musb_readw, |
1443 | 942ac052 | balrog | }; |
1444 | 942ac052 | balrog | |
1445 | 942ac052 | balrog | CPUWriteMemoryFunc *musb_write[] = { |
1446 | 942ac052 | balrog | musb_writeb, |
1447 | 942ac052 | balrog | musb_writeh, |
1448 | 942ac052 | balrog | musb_writew, |
1449 | 942ac052 | balrog | }; |