root / target-mips / TODO @ e83ce550
History | View | Annotate | Download (2.2 kB)
1 | 2c52c816 | ths | Unsolved issues/bugs in the mips/mipsel backend |
---|---|---|---|
2 | 2c52c816 | ths | ----------------------------------------------- |
3 | 2c52c816 | ths | |
4 | 15dcf5aa | ths | General |
5 | 15dcf5aa | ths | ------- |
6 | d0f48074 | ths | - Unimplemented ASEs: |
7 | d0f48074 | ths | - MIPS16 |
8 | d0f48074 | ths | - MDMX |
9 | d0f48074 | ths | - SmartMIPS |
10 | d0f48074 | ths | - DSP r1 |
11 | d0f48074 | ths | - DSP r2 |
12 | d0f48074 | ths | - MT ASE only partially implemented and not functional |
13 | d0f48074 | ths | - Shadow register support only partially implemented, |
14 | d0f48074 | ths | lacks set switching on interrupt/exception. |
15 | d0f48074 | ths | - 34K ITC not implemented. |
16 | d0f48074 | ths | - A general lack of documentation, especially for technical internals. |
17 | d0f48074 | ths | Existing documentation is x86-centric. |
18 | d0f48074 | ths | - Reverse endianness bit not implemented |
19 | d0f48074 | ths | - The TLB emulation is very inefficient: |
20 | d0f48074 | ths | Qemu's softmmu implements a x86-style MMU, with separate entries |
21 | d0f48074 | ths | for read/write/execute, a TLB index which is just a modulo of the |
22 | d0f48074 | ths | virtual address, and a set of TLBs for each user/kernel/supervisor |
23 | d0f48074 | ths | MMU mode. |
24 | d0f48074 | ths | MIPS has a single entry for read/write/execute and only one MMU mode. |
25 | d0f48074 | ths | But it is fully associative with randomized entry indices, and uses |
26 | d0f48074 | ths | up to 256 ASID tags as additional matching criterion (which roughly |
27 | d0f48074 | ths | equates to 256 MMU modes). It also has a global flag which causes |
28 | d0f48074 | ths | entries to match regardless of ASID. |
29 | d0f48074 | ths | To cope with these differences, Qemu currently flushes the TLB at |
30 | d0f48074 | ths | each ASID change. Using the MMU modes to implement ASIDs hinges on |
31 | d0f48074 | ths | implementing the global bit efficiently. |
32 | bec19c09 | ths | - save/restore of the CPU state is not implemented (see machine.c). |
33 | 2681b45a | ths | - Improve cpu state handling: |
34 | 2681b45a | ths | Step 1) Collect all the TC state in a single struct, so we need only |
35 | ebbd0ffd | ths | a single global pointer for the active TC. |
36 | 2681b45a | ths | Step 2) Use only a single TC context as working context, and copy the |
37 | 2681b45a | ths | contexts on TC switch. Likewise for FPU contexts. |
38 | 2c52c816 | ths | |
39 | 15dcf5aa | ths | MIPS64 |
40 | 15dcf5aa | ths | ------ |
41 | 540635ba | ths | - Userland emulation (both n32 and n64) not functional. |
42 | 15dcf5aa | ths | |
43 | 15dcf5aa | ths | "Generic" 4Kc system emulation |
44 | 15dcf5aa | ths | ------------------------------ |
45 | ebbd0ffd | ths | - Doesn't correspond to any real hardware. Should be removed some day, |
46 | ebbd0ffd | ths | U-Boot is the last remaining user. |
47 | 15dcf5aa | ths | |
48 | 509b8ab2 | ths | PICA 61 system emulation |
49 | 509b8ab2 | ths | ------------------------ |
50 | 509b8ab2 | ths | - No framebuffer support yet. |
51 | 509b8ab2 | ths | |
52 | 15dcf5aa | ths | MALTA system emulation |
53 | 15dcf5aa | ths | ---------------------- |
54 | 2c52c816 | ths | - We fake firmware support instead of doing the real thing |
55 | ebbd0ffd | ths | - Real firmware (YAMON) falls over when trying to init RAM, presumably |
56 | ebbd0ffd | ths | due to lacking system controller emulation. |
57 | 0300e3fa | ths | - Bonito system controller not implemented |
58 | 0300e3fa | ths | - MSC1 system controller not implemented |