root / hw / ppc405_uc.c @ e927bb00
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/*
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* QEMU PowerPC 405 embedded processors emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
|
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "ppc.h" |
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#include "ppc405.h" |
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#include "pc.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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|
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extern int loglevel; |
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extern FILE *logfile;
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|
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#define DEBUG_OPBA
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#define DEBUG_SDRAM
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#define DEBUG_GPIO
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#define DEBUG_SERIAL
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#define DEBUG_OCM
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//#define DEBUG_I2C
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#define DEBUG_GPT
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#define DEBUG_MAL
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#define DEBUG_CLOCKS
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//#define DEBUG_CLOCKS_LL
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|
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ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
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uint32_t flags) |
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{
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ram_addr_t bdloc; |
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int i, n;
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|
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/* We put the bd structure at the top of memory */
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if (bd->bi_memsize >= 0x01000000UL) |
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bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); |
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else
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bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); |
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stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
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stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
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stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
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stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
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stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
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stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
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stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
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stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
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stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
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for (i = 0; i < 6; i++) |
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stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
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stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
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stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
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stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
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stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
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for (i = 0; i < 4; i++) |
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stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
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for (i = 0; i < 32; i++) |
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stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
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stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
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stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
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for (i = 0; i < 6; i++) |
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stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
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n = 0x6A;
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if (flags & 0x00000001) { |
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for (i = 0; i < 6; i++) |
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stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]); |
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} |
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stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq); |
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n += 4;
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for (i = 0; i < 2; i++) { |
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stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]); |
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n += 4;
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} |
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return bdloc;
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} |
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|
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/*****************************************************************************/
|
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/* Shared peripherals */
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|
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/*****************************************************************************/
|
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/* Peripheral local bus arbitrer */
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enum {
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PLB0_BESR = 0x084,
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PLB0_BEAR = 0x086,
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PLB0_ACR = 0x087,
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}; |
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|
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typedef struct ppc4xx_plb_t ppc4xx_plb_t; |
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struct ppc4xx_plb_t {
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uint32_t acr; |
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uint32_t bear; |
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uint32_t besr; |
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}; |
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|
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static target_ulong dcr_read_plb (void *opaque, int dcrn) |
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{
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ppc4xx_plb_t *plb; |
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target_ulong ret; |
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plb = opaque; |
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switch (dcrn) {
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case PLB0_ACR:
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ret = plb->acr; |
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break;
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case PLB0_BEAR:
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ret = plb->bear; |
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break;
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case PLB0_BESR:
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ret = plb->besr; |
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break;
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default:
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/* Avoid gcc warning */
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ret = 0;
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break;
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} |
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return ret;
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} |
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|
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static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) |
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{
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ppc4xx_plb_t *plb; |
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plb = opaque; |
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switch (dcrn) {
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case PLB0_ACR:
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/* We don't care about the actual parameters written as
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* we don't manage any priorities on the bus
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*/
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plb->acr = val & 0xF8000000;
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break;
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case PLB0_BEAR:
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/* Read only */
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break;
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case PLB0_BESR:
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/* Write-clear */
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plb->besr &= ~val; |
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break;
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} |
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} |
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|
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static void ppc4xx_plb_reset (void *opaque) |
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{
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ppc4xx_plb_t *plb; |
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plb = opaque; |
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plb->acr = 0x00000000;
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plb->bear = 0x00000000;
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plb->besr = 0x00000000;
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} |
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|
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void ppc4xx_plb_init (CPUState *env)
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{
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ppc4xx_plb_t *plb; |
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|
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plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
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if (plb != NULL) { |
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ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
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ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); |
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ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); |
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ppc4xx_plb_reset(plb); |
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qemu_register_reset(ppc4xx_plb_reset, plb); |
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} |
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} |
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|
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/*****************************************************************************/
|
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/* PLB to OPB bridge */
|
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enum {
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POB0_BESR0 = 0x0A0,
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POB0_BESR1 = 0x0A2,
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POB0_BEAR = 0x0A4,
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}; |
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|
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typedef struct ppc4xx_pob_t ppc4xx_pob_t; |
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struct ppc4xx_pob_t {
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uint32_t bear; |
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uint32_t besr[2];
|
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}; |
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|
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static target_ulong dcr_read_pob (void *opaque, int dcrn) |
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{
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ppc4xx_pob_t *pob; |
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target_ulong ret; |
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|
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pob = opaque; |
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switch (dcrn) {
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case POB0_BEAR:
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ret = pob->bear; |
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break;
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case POB0_BESR0:
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case POB0_BESR1:
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ret = pob->besr[dcrn - POB0_BESR0]; |
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break;
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default:
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/* Avoid gcc warning */
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ret = 0;
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break;
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} |
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|
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return ret;
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} |
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|
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static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) |
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{
|
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ppc4xx_pob_t *pob; |
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|
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pob = opaque; |
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switch (dcrn) {
|
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case POB0_BEAR:
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/* Read only */
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break;
|
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case POB0_BESR0:
|
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case POB0_BESR1:
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/* Write-clear */
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pob->besr[dcrn - POB0_BESR0] &= ~val; |
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break;
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} |
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} |
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|
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static void ppc4xx_pob_reset (void *opaque) |
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{
|
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ppc4xx_pob_t *pob; |
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|
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pob = opaque; |
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/* No error */
|
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pob->bear = 0x00000000;
|
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pob->besr[0] = 0x0000000; |
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pob->besr[1] = 0x0000000; |
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} |
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|
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void ppc4xx_pob_init (CPUState *env)
|
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{
|
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ppc4xx_pob_t *pob; |
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|
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pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
|
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if (pob != NULL) { |
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ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
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ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); |
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ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); |
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qemu_register_reset(ppc4xx_pob_reset, pob); |
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ppc4xx_pob_reset(env); |
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} |
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} |
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|
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/*****************************************************************************/
|
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/* OPB arbitrer */
|
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typedef struct ppc4xx_opba_t ppc4xx_opba_t; |
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struct ppc4xx_opba_t {
|
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target_phys_addr_t base; |
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uint8_t cr; |
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uint8_t pr; |
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}; |
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|
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static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) |
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{
|
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ppc4xx_opba_t *opba; |
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uint32_t ret; |
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|
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX "\n", __func__, addr); |
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#endif
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opba = opaque; |
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switch (addr - opba->base) {
|
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case 0x00: |
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ret = opba->cr; |
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break;
|
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case 0x01: |
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ret = opba->pr; |
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break;
|
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default:
|
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ret = 0x00;
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break;
|
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} |
| 291 |
|
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return ret;
|
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} |
| 294 |
|
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static void opba_writeb (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
| 297 |
{
|
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ppc4xx_opba_t *opba; |
| 299 |
|
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#ifdef DEBUG_OPBA
|
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 302 |
#endif
|
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opba = opaque; |
| 304 |
switch (addr - opba->base) {
|
| 305 |
case 0x00: |
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opba->cr = value & 0xF8;
|
| 307 |
break;
|
| 308 |
case 0x01: |
| 309 |
opba->pr = value & 0xFF;
|
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break;
|
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default:
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break;
|
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} |
| 314 |
} |
| 315 |
|
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static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) |
| 317 |
{
|
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uint32_t ret; |
| 319 |
|
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#ifdef DEBUG_OPBA
|
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printf("%s: addr " PADDRX "\n", __func__, addr); |
| 322 |
#endif
|
| 323 |
ret = opba_readb(opaque, addr) << 8;
|
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ret |= opba_readb(opaque, addr + 1);
|
| 325 |
|
| 326 |
return ret;
|
| 327 |
} |
| 328 |
|
| 329 |
static void opba_writew (void *opaque, |
| 330 |
target_phys_addr_t addr, uint32_t value) |
| 331 |
{
|
| 332 |
#ifdef DEBUG_OPBA
|
| 333 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 334 |
#endif
|
| 335 |
opba_writeb(opaque, addr, value >> 8);
|
| 336 |
opba_writeb(opaque, addr + 1, value);
|
| 337 |
} |
| 338 |
|
| 339 |
static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) |
| 340 |
{
|
| 341 |
uint32_t ret; |
| 342 |
|
| 343 |
#ifdef DEBUG_OPBA
|
| 344 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
| 345 |
#endif
|
| 346 |
ret = opba_readb(opaque, addr) << 24;
|
| 347 |
ret |= opba_readb(opaque, addr + 1) << 16; |
| 348 |
|
| 349 |
return ret;
|
| 350 |
} |
| 351 |
|
| 352 |
static void opba_writel (void *opaque, |
| 353 |
target_phys_addr_t addr, uint32_t value) |
| 354 |
{
|
| 355 |
#ifdef DEBUG_OPBA
|
| 356 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 357 |
#endif
|
| 358 |
opba_writeb(opaque, addr, value >> 24);
|
| 359 |
opba_writeb(opaque, addr + 1, value >> 16); |
| 360 |
} |
| 361 |
|
| 362 |
static CPUReadMemoryFunc *opba_read[] = {
|
| 363 |
&opba_readb, |
| 364 |
&opba_readw, |
| 365 |
&opba_readl, |
| 366 |
}; |
| 367 |
|
| 368 |
static CPUWriteMemoryFunc *opba_write[] = {
|
| 369 |
&opba_writeb, |
| 370 |
&opba_writew, |
| 371 |
&opba_writel, |
| 372 |
}; |
| 373 |
|
| 374 |
static void ppc4xx_opba_reset (void *opaque) |
| 375 |
{
|
| 376 |
ppc4xx_opba_t *opba; |
| 377 |
|
| 378 |
opba = opaque; |
| 379 |
opba->cr = 0x00; /* No dynamic priorities - park disabled */ |
| 380 |
opba->pr = 0x11;
|
| 381 |
} |
| 382 |
|
| 383 |
void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
| 384 |
target_phys_addr_t offset) |
| 385 |
{
|
| 386 |
ppc4xx_opba_t *opba; |
| 387 |
|
| 388 |
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
|
| 389 |
if (opba != NULL) { |
| 390 |
opba->base = offset; |
| 391 |
#ifdef DEBUG_OPBA
|
| 392 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
| 393 |
#endif
|
| 394 |
ppc4xx_mmio_register(env, mmio, offset, 0x002,
|
| 395 |
opba_read, opba_write, opba); |
| 396 |
qemu_register_reset(ppc4xx_opba_reset, opba); |
| 397 |
ppc4xx_opba_reset(opba); |
| 398 |
} |
| 399 |
} |
| 400 |
|
| 401 |
/*****************************************************************************/
|
| 402 |
/* Code decompression controller */
|
| 403 |
/* XXX: TODO */
|
| 404 |
|
| 405 |
/*****************************************************************************/
|
| 406 |
/* SDRAM controller */
|
| 407 |
typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; |
| 408 |
struct ppc4xx_sdram_t {
|
| 409 |
uint32_t addr; |
| 410 |
int nbanks;
|
| 411 |
target_phys_addr_t ram_bases[4];
|
| 412 |
target_phys_addr_t ram_sizes[4];
|
| 413 |
uint32_t besr0; |
| 414 |
uint32_t besr1; |
| 415 |
uint32_t bear; |
| 416 |
uint32_t cfg; |
| 417 |
uint32_t status; |
| 418 |
uint32_t rtr; |
| 419 |
uint32_t pmit; |
| 420 |
uint32_t bcr[4];
|
| 421 |
uint32_t tr; |
| 422 |
uint32_t ecccfg; |
| 423 |
uint32_t eccesr; |
| 424 |
qemu_irq irq; |
| 425 |
}; |
| 426 |
|
| 427 |
enum {
|
| 428 |
SDRAM0_CFGADDR = 0x010,
|
| 429 |
SDRAM0_CFGDATA = 0x011,
|
| 430 |
}; |
| 431 |
|
| 432 |
/* XXX: TOFIX: some patches have made this code become inconsistent:
|
| 433 |
* there are type inconsistencies, mixing target_phys_addr_t, target_ulong
|
| 434 |
* and uint32_t
|
| 435 |
*/
|
| 436 |
static uint32_t sdram_bcr (target_phys_addr_t ram_base,
|
| 437 |
target_phys_addr_t ram_size) |
| 438 |
{
|
| 439 |
uint32_t bcr; |
| 440 |
|
| 441 |
switch (ram_size) {
|
| 442 |
case (4 * 1024 * 1024): |
| 443 |
bcr = 0x00000000;
|
| 444 |
break;
|
| 445 |
case (8 * 1024 * 1024): |
| 446 |
bcr = 0x00020000;
|
| 447 |
break;
|
| 448 |
case (16 * 1024 * 1024): |
| 449 |
bcr = 0x00040000;
|
| 450 |
break;
|
| 451 |
case (32 * 1024 * 1024): |
| 452 |
bcr = 0x00060000;
|
| 453 |
break;
|
| 454 |
case (64 * 1024 * 1024): |
| 455 |
bcr = 0x00080000;
|
| 456 |
break;
|
| 457 |
case (128 * 1024 * 1024): |
| 458 |
bcr = 0x000A0000;
|
| 459 |
break;
|
| 460 |
case (256 * 1024 * 1024): |
| 461 |
bcr = 0x000C0000;
|
| 462 |
break;
|
| 463 |
default:
|
| 464 |
printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size); |
| 465 |
return 0x00000000; |
| 466 |
} |
| 467 |
bcr |= ram_base & 0xFF800000;
|
| 468 |
bcr |= 1;
|
| 469 |
|
| 470 |
return bcr;
|
| 471 |
} |
| 472 |
|
| 473 |
static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
|
| 474 |
{
|
| 475 |
return bcr & 0xFF800000; |
| 476 |
} |
| 477 |
|
| 478 |
static target_ulong sdram_size (uint32_t bcr)
|
| 479 |
{
|
| 480 |
target_ulong size; |
| 481 |
int sh;
|
| 482 |
|
| 483 |
sh = (bcr >> 17) & 0x7; |
| 484 |
if (sh == 7) |
| 485 |
size = -1;
|
| 486 |
else
|
| 487 |
size = (4 * 1024 * 1024) << sh; |
| 488 |
|
| 489 |
return size;
|
| 490 |
} |
| 491 |
|
| 492 |
static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) |
| 493 |
{
|
| 494 |
if (*bcrp & 0x00000001) { |
| 495 |
/* Unmap RAM */
|
| 496 |
#ifdef DEBUG_SDRAM
|
| 497 |
printf("%s: unmap RAM area " PADDRX " " ADDRX "\n", |
| 498 |
__func__, sdram_base(*bcrp), sdram_size(*bcrp)); |
| 499 |
#endif
|
| 500 |
cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), |
| 501 |
IO_MEM_UNASSIGNED); |
| 502 |
} |
| 503 |
*bcrp = bcr & 0xFFDEE001;
|
| 504 |
if (enabled && (bcr & 0x00000001)) { |
| 505 |
#ifdef DEBUG_SDRAM
|
| 506 |
printf("%s: Map RAM area " PADDRX " " ADDRX "\n", |
| 507 |
__func__, sdram_base(bcr), sdram_size(bcr)); |
| 508 |
#endif
|
| 509 |
cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), |
| 510 |
sdram_base(bcr) | IO_MEM_RAM); |
| 511 |
} |
| 512 |
} |
| 513 |
|
| 514 |
static void sdram_map_bcr (ppc4xx_sdram_t *sdram) |
| 515 |
{
|
| 516 |
int i;
|
| 517 |
|
| 518 |
for (i = 0; i < sdram->nbanks; i++) { |
| 519 |
if (sdram->ram_sizes[i] != 0) { |
| 520 |
sdram_set_bcr(&sdram->bcr[i], |
| 521 |
sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), |
| 522 |
1);
|
| 523 |
} else {
|
| 524 |
sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0); |
| 525 |
} |
| 526 |
} |
| 527 |
} |
| 528 |
|
| 529 |
static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) |
| 530 |
{
|
| 531 |
int i;
|
| 532 |
|
| 533 |
for (i = 0; i < sdram->nbanks; i++) { |
| 534 |
#ifdef DEBUG_SDRAM
|
| 535 |
printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n", |
| 536 |
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
| 537 |
#endif
|
| 538 |
cpu_register_physical_memory(sdram_base(sdram->bcr[i]), |
| 539 |
sdram_size(sdram->bcr[i]), |
| 540 |
IO_MEM_UNASSIGNED); |
| 541 |
} |
| 542 |
} |
| 543 |
|
| 544 |
static target_ulong dcr_read_sdram (void *opaque, int dcrn) |
| 545 |
{
|
| 546 |
ppc4xx_sdram_t *sdram; |
| 547 |
target_ulong ret; |
| 548 |
|
| 549 |
sdram = opaque; |
| 550 |
switch (dcrn) {
|
| 551 |
case SDRAM0_CFGADDR:
|
| 552 |
ret = sdram->addr; |
| 553 |
break;
|
| 554 |
case SDRAM0_CFGDATA:
|
| 555 |
switch (sdram->addr) {
|
| 556 |
case 0x00: /* SDRAM_BESR0 */ |
| 557 |
ret = sdram->besr0; |
| 558 |
break;
|
| 559 |
case 0x08: /* SDRAM_BESR1 */ |
| 560 |
ret = sdram->besr1; |
| 561 |
break;
|
| 562 |
case 0x10: /* SDRAM_BEAR */ |
| 563 |
ret = sdram->bear; |
| 564 |
break;
|
| 565 |
case 0x20: /* SDRAM_CFG */ |
| 566 |
ret = sdram->cfg; |
| 567 |
break;
|
| 568 |
case 0x24: /* SDRAM_STATUS */ |
| 569 |
ret = sdram->status; |
| 570 |
break;
|
| 571 |
case 0x30: /* SDRAM_RTR */ |
| 572 |
ret = sdram->rtr; |
| 573 |
break;
|
| 574 |
case 0x34: /* SDRAM_PMIT */ |
| 575 |
ret = sdram->pmit; |
| 576 |
break;
|
| 577 |
case 0x40: /* SDRAM_B0CR */ |
| 578 |
ret = sdram->bcr[0];
|
| 579 |
break;
|
| 580 |
case 0x44: /* SDRAM_B1CR */ |
| 581 |
ret = sdram->bcr[1];
|
| 582 |
break;
|
| 583 |
case 0x48: /* SDRAM_B2CR */ |
| 584 |
ret = sdram->bcr[2];
|
| 585 |
break;
|
| 586 |
case 0x4C: /* SDRAM_B3CR */ |
| 587 |
ret = sdram->bcr[3];
|
| 588 |
break;
|
| 589 |
case 0x80: /* SDRAM_TR */ |
| 590 |
ret = -1; /* ? */ |
| 591 |
break;
|
| 592 |
case 0x94: /* SDRAM_ECCCFG */ |
| 593 |
ret = sdram->ecccfg; |
| 594 |
break;
|
| 595 |
case 0x98: /* SDRAM_ECCESR */ |
| 596 |
ret = sdram->eccesr; |
| 597 |
break;
|
| 598 |
default: /* Error */ |
| 599 |
ret = -1;
|
| 600 |
break;
|
| 601 |
} |
| 602 |
break;
|
| 603 |
default:
|
| 604 |
/* Avoid gcc warning */
|
| 605 |
ret = 0x00000000;
|
| 606 |
break;
|
| 607 |
} |
| 608 |
|
| 609 |
return ret;
|
| 610 |
} |
| 611 |
|
| 612 |
static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val) |
| 613 |
{
|
| 614 |
ppc4xx_sdram_t *sdram; |
| 615 |
|
| 616 |
sdram = opaque; |
| 617 |
switch (dcrn) {
|
| 618 |
case SDRAM0_CFGADDR:
|
| 619 |
sdram->addr = val; |
| 620 |
break;
|
| 621 |
case SDRAM0_CFGDATA:
|
| 622 |
switch (sdram->addr) {
|
| 623 |
case 0x00: /* SDRAM_BESR0 */ |
| 624 |
sdram->besr0 &= ~val; |
| 625 |
break;
|
| 626 |
case 0x08: /* SDRAM_BESR1 */ |
| 627 |
sdram->besr1 &= ~val; |
| 628 |
break;
|
| 629 |
case 0x10: /* SDRAM_BEAR */ |
| 630 |
sdram->bear = val; |
| 631 |
break;
|
| 632 |
case 0x20: /* SDRAM_CFG */ |
| 633 |
val &= 0xFFE00000;
|
| 634 |
if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { |
| 635 |
#ifdef DEBUG_SDRAM
|
| 636 |
printf("%s: enable SDRAM controller\n", __func__);
|
| 637 |
#endif
|
| 638 |
/* validate all RAM mappings */
|
| 639 |
sdram_map_bcr(sdram); |
| 640 |
sdram->status &= ~0x80000000;
|
| 641 |
} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { |
| 642 |
#ifdef DEBUG_SDRAM
|
| 643 |
printf("%s: disable SDRAM controller\n", __func__);
|
| 644 |
#endif
|
| 645 |
/* invalidate all RAM mappings */
|
| 646 |
sdram_unmap_bcr(sdram); |
| 647 |
sdram->status |= 0x80000000;
|
| 648 |
} |
| 649 |
if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) |
| 650 |
sdram->status |= 0x40000000;
|
| 651 |
else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) |
| 652 |
sdram->status &= ~0x40000000;
|
| 653 |
sdram->cfg = val; |
| 654 |
break;
|
| 655 |
case 0x24: /* SDRAM_STATUS */ |
| 656 |
/* Read-only register */
|
| 657 |
break;
|
| 658 |
case 0x30: /* SDRAM_RTR */ |
| 659 |
sdram->rtr = val & 0x3FF80000;
|
| 660 |
break;
|
| 661 |
case 0x34: /* SDRAM_PMIT */ |
| 662 |
sdram->pmit = (val & 0xF8000000) | 0x07C00000; |
| 663 |
break;
|
| 664 |
case 0x40: /* SDRAM_B0CR */ |
| 665 |
sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000); |
| 666 |
break;
|
| 667 |
case 0x44: /* SDRAM_B1CR */ |
| 668 |
sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000); |
| 669 |
break;
|
| 670 |
case 0x48: /* SDRAM_B2CR */ |
| 671 |
sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000); |
| 672 |
break;
|
| 673 |
case 0x4C: /* SDRAM_B3CR */ |
| 674 |
sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000); |
| 675 |
break;
|
| 676 |
case 0x80: /* SDRAM_TR */ |
| 677 |
sdram->tr = val & 0x018FC01F;
|
| 678 |
break;
|
| 679 |
case 0x94: /* SDRAM_ECCCFG */ |
| 680 |
sdram->ecccfg = val & 0x00F00000;
|
| 681 |
break;
|
| 682 |
case 0x98: /* SDRAM_ECCESR */ |
| 683 |
val &= 0xFFF0F000;
|
| 684 |
if (sdram->eccesr == 0 && val != 0) |
| 685 |
qemu_irq_raise(sdram->irq); |
| 686 |
else if (sdram->eccesr != 0 && val == 0) |
| 687 |
qemu_irq_lower(sdram->irq); |
| 688 |
sdram->eccesr = val; |
| 689 |
break;
|
| 690 |
default: /* Error */ |
| 691 |
break;
|
| 692 |
} |
| 693 |
break;
|
| 694 |
} |
| 695 |
} |
| 696 |
|
| 697 |
static void sdram_reset (void *opaque) |
| 698 |
{
|
| 699 |
ppc4xx_sdram_t *sdram; |
| 700 |
|
| 701 |
sdram = opaque; |
| 702 |
sdram->addr = 0x00000000;
|
| 703 |
sdram->bear = 0x00000000;
|
| 704 |
sdram->besr0 = 0x00000000; /* No error */ |
| 705 |
sdram->besr1 = 0x00000000; /* No error */ |
| 706 |
sdram->cfg = 0x00000000;
|
| 707 |
sdram->ecccfg = 0x00000000; /* No ECC */ |
| 708 |
sdram->eccesr = 0x00000000; /* No error */ |
| 709 |
sdram->pmit = 0x07C00000;
|
| 710 |
sdram->rtr = 0x05F00000;
|
| 711 |
sdram->tr = 0x00854009;
|
| 712 |
/* We pre-initialize RAM banks */
|
| 713 |
sdram->status = 0x00000000;
|
| 714 |
sdram->cfg = 0x00800000;
|
| 715 |
sdram_unmap_bcr(sdram); |
| 716 |
} |
| 717 |
|
| 718 |
void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
| 719 |
target_phys_addr_t *ram_bases, |
| 720 |
target_phys_addr_t *ram_sizes, |
| 721 |
int do_init)
|
| 722 |
{
|
| 723 |
ppc4xx_sdram_t *sdram; |
| 724 |
|
| 725 |
sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
|
| 726 |
if (sdram != NULL) { |
| 727 |
sdram->irq = irq; |
| 728 |
sdram->nbanks = nbanks; |
| 729 |
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); |
| 730 |
memcpy(sdram->ram_bases, ram_bases, |
| 731 |
nbanks * sizeof(target_phys_addr_t));
|
| 732 |
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); |
| 733 |
memcpy(sdram->ram_sizes, ram_sizes, |
| 734 |
nbanks * sizeof(target_phys_addr_t));
|
| 735 |
sdram_reset(sdram); |
| 736 |
qemu_register_reset(&sdram_reset, sdram); |
| 737 |
ppc_dcr_register(env, SDRAM0_CFGADDR, |
| 738 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
| 739 |
ppc_dcr_register(env, SDRAM0_CFGDATA, |
| 740 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
| 741 |
if (do_init)
|
| 742 |
sdram_map_bcr(sdram); |
| 743 |
} |
| 744 |
} |
| 745 |
|
| 746 |
/*****************************************************************************/
|
| 747 |
/* Peripheral controller */
|
| 748 |
typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; |
| 749 |
struct ppc4xx_ebc_t {
|
| 750 |
uint32_t addr; |
| 751 |
uint32_t bcr[8];
|
| 752 |
uint32_t bap[8];
|
| 753 |
uint32_t bear; |
| 754 |
uint32_t besr0; |
| 755 |
uint32_t besr1; |
| 756 |
uint32_t cfg; |
| 757 |
}; |
| 758 |
|
| 759 |
enum {
|
| 760 |
EBC0_CFGADDR = 0x012,
|
| 761 |
EBC0_CFGDATA = 0x013,
|
| 762 |
}; |
| 763 |
|
| 764 |
static target_ulong dcr_read_ebc (void *opaque, int dcrn) |
| 765 |
{
|
| 766 |
ppc4xx_ebc_t *ebc; |
| 767 |
target_ulong ret; |
| 768 |
|
| 769 |
ebc = opaque; |
| 770 |
switch (dcrn) {
|
| 771 |
case EBC0_CFGADDR:
|
| 772 |
ret = ebc->addr; |
| 773 |
break;
|
| 774 |
case EBC0_CFGDATA:
|
| 775 |
switch (ebc->addr) {
|
| 776 |
case 0x00: /* B0CR */ |
| 777 |
ret = ebc->bcr[0];
|
| 778 |
break;
|
| 779 |
case 0x01: /* B1CR */ |
| 780 |
ret = ebc->bcr[1];
|
| 781 |
break;
|
| 782 |
case 0x02: /* B2CR */ |
| 783 |
ret = ebc->bcr[2];
|
| 784 |
break;
|
| 785 |
case 0x03: /* B3CR */ |
| 786 |
ret = ebc->bcr[3];
|
| 787 |
break;
|
| 788 |
case 0x04: /* B4CR */ |
| 789 |
ret = ebc->bcr[4];
|
| 790 |
break;
|
| 791 |
case 0x05: /* B5CR */ |
| 792 |
ret = ebc->bcr[5];
|
| 793 |
break;
|
| 794 |
case 0x06: /* B6CR */ |
| 795 |
ret = ebc->bcr[6];
|
| 796 |
break;
|
| 797 |
case 0x07: /* B7CR */ |
| 798 |
ret = ebc->bcr[7];
|
| 799 |
break;
|
| 800 |
case 0x10: /* B0AP */ |
| 801 |
ret = ebc->bap[0];
|
| 802 |
break;
|
| 803 |
case 0x11: /* B1AP */ |
| 804 |
ret = ebc->bap[1];
|
| 805 |
break;
|
| 806 |
case 0x12: /* B2AP */ |
| 807 |
ret = ebc->bap[2];
|
| 808 |
break;
|
| 809 |
case 0x13: /* B3AP */ |
| 810 |
ret = ebc->bap[3];
|
| 811 |
break;
|
| 812 |
case 0x14: /* B4AP */ |
| 813 |
ret = ebc->bap[4];
|
| 814 |
break;
|
| 815 |
case 0x15: /* B5AP */ |
| 816 |
ret = ebc->bap[5];
|
| 817 |
break;
|
| 818 |
case 0x16: /* B6AP */ |
| 819 |
ret = ebc->bap[6];
|
| 820 |
break;
|
| 821 |
case 0x17: /* B7AP */ |
| 822 |
ret = ebc->bap[7];
|
| 823 |
break;
|
| 824 |
case 0x20: /* BEAR */ |
| 825 |
ret = ebc->bear; |
| 826 |
break;
|
| 827 |
case 0x21: /* BESR0 */ |
| 828 |
ret = ebc->besr0; |
| 829 |
break;
|
| 830 |
case 0x22: /* BESR1 */ |
| 831 |
ret = ebc->besr1; |
| 832 |
break;
|
| 833 |
case 0x23: /* CFG */ |
| 834 |
ret = ebc->cfg; |
| 835 |
break;
|
| 836 |
default:
|
| 837 |
ret = 0x00000000;
|
| 838 |
break;
|
| 839 |
} |
| 840 |
default:
|
| 841 |
ret = 0x00000000;
|
| 842 |
break;
|
| 843 |
} |
| 844 |
|
| 845 |
return ret;
|
| 846 |
} |
| 847 |
|
| 848 |
static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) |
| 849 |
{
|
| 850 |
ppc4xx_ebc_t *ebc; |
| 851 |
|
| 852 |
ebc = opaque; |
| 853 |
switch (dcrn) {
|
| 854 |
case EBC0_CFGADDR:
|
| 855 |
ebc->addr = val; |
| 856 |
break;
|
| 857 |
case EBC0_CFGDATA:
|
| 858 |
switch (ebc->addr) {
|
| 859 |
case 0x00: /* B0CR */ |
| 860 |
break;
|
| 861 |
case 0x01: /* B1CR */ |
| 862 |
break;
|
| 863 |
case 0x02: /* B2CR */ |
| 864 |
break;
|
| 865 |
case 0x03: /* B3CR */ |
| 866 |
break;
|
| 867 |
case 0x04: /* B4CR */ |
| 868 |
break;
|
| 869 |
case 0x05: /* B5CR */ |
| 870 |
break;
|
| 871 |
case 0x06: /* B6CR */ |
| 872 |
break;
|
| 873 |
case 0x07: /* B7CR */ |
| 874 |
break;
|
| 875 |
case 0x10: /* B0AP */ |
| 876 |
break;
|
| 877 |
case 0x11: /* B1AP */ |
| 878 |
break;
|
| 879 |
case 0x12: /* B2AP */ |
| 880 |
break;
|
| 881 |
case 0x13: /* B3AP */ |
| 882 |
break;
|
| 883 |
case 0x14: /* B4AP */ |
| 884 |
break;
|
| 885 |
case 0x15: /* B5AP */ |
| 886 |
break;
|
| 887 |
case 0x16: /* B6AP */ |
| 888 |
break;
|
| 889 |
case 0x17: /* B7AP */ |
| 890 |
break;
|
| 891 |
case 0x20: /* BEAR */ |
| 892 |
break;
|
| 893 |
case 0x21: /* BESR0 */ |
| 894 |
break;
|
| 895 |
case 0x22: /* BESR1 */ |
| 896 |
break;
|
| 897 |
case 0x23: /* CFG */ |
| 898 |
break;
|
| 899 |
default:
|
| 900 |
break;
|
| 901 |
} |
| 902 |
break;
|
| 903 |
default:
|
| 904 |
break;
|
| 905 |
} |
| 906 |
} |
| 907 |
|
| 908 |
static void ebc_reset (void *opaque) |
| 909 |
{
|
| 910 |
ppc4xx_ebc_t *ebc; |
| 911 |
int i;
|
| 912 |
|
| 913 |
ebc = opaque; |
| 914 |
ebc->addr = 0x00000000;
|
| 915 |
ebc->bap[0] = 0x7F8FFE80; |
| 916 |
ebc->bcr[0] = 0xFFE28000; |
| 917 |
for (i = 0; i < 8; i++) { |
| 918 |
ebc->bap[i] = 0x00000000;
|
| 919 |
ebc->bcr[i] = 0x00000000;
|
| 920 |
} |
| 921 |
ebc->besr0 = 0x00000000;
|
| 922 |
ebc->besr1 = 0x00000000;
|
| 923 |
ebc->cfg = 0x80400000;
|
| 924 |
} |
| 925 |
|
| 926 |
void ppc405_ebc_init (CPUState *env)
|
| 927 |
{
|
| 928 |
ppc4xx_ebc_t *ebc; |
| 929 |
|
| 930 |
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
|
| 931 |
if (ebc != NULL) { |
| 932 |
ebc_reset(ebc); |
| 933 |
qemu_register_reset(&ebc_reset, ebc); |
| 934 |
ppc_dcr_register(env, EBC0_CFGADDR, |
| 935 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
| 936 |
ppc_dcr_register(env, EBC0_CFGDATA, |
| 937 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
| 938 |
} |
| 939 |
} |
| 940 |
|
| 941 |
/*****************************************************************************/
|
| 942 |
/* DMA controller */
|
| 943 |
enum {
|
| 944 |
DMA0_CR0 = 0x100,
|
| 945 |
DMA0_CT0 = 0x101,
|
| 946 |
DMA0_DA0 = 0x102,
|
| 947 |
DMA0_SA0 = 0x103,
|
| 948 |
DMA0_SG0 = 0x104,
|
| 949 |
DMA0_CR1 = 0x108,
|
| 950 |
DMA0_CT1 = 0x109,
|
| 951 |
DMA0_DA1 = 0x10A,
|
| 952 |
DMA0_SA1 = 0x10B,
|
| 953 |
DMA0_SG1 = 0x10C,
|
| 954 |
DMA0_CR2 = 0x110,
|
| 955 |
DMA0_CT2 = 0x111,
|
| 956 |
DMA0_DA2 = 0x112,
|
| 957 |
DMA0_SA2 = 0x113,
|
| 958 |
DMA0_SG2 = 0x114,
|
| 959 |
DMA0_CR3 = 0x118,
|
| 960 |
DMA0_CT3 = 0x119,
|
| 961 |
DMA0_DA3 = 0x11A,
|
| 962 |
DMA0_SA3 = 0x11B,
|
| 963 |
DMA0_SG3 = 0x11C,
|
| 964 |
DMA0_SR = 0x120,
|
| 965 |
DMA0_SGC = 0x123,
|
| 966 |
DMA0_SLP = 0x125,
|
| 967 |
DMA0_POL = 0x126,
|
| 968 |
}; |
| 969 |
|
| 970 |
typedef struct ppc405_dma_t ppc405_dma_t; |
| 971 |
struct ppc405_dma_t {
|
| 972 |
qemu_irq irqs[4];
|
| 973 |
uint32_t cr[4];
|
| 974 |
uint32_t ct[4];
|
| 975 |
uint32_t da[4];
|
| 976 |
uint32_t sa[4];
|
| 977 |
uint32_t sg[4];
|
| 978 |
uint32_t sr; |
| 979 |
uint32_t sgc; |
| 980 |
uint32_t slp; |
| 981 |
uint32_t pol; |
| 982 |
}; |
| 983 |
|
| 984 |
static target_ulong dcr_read_dma (void *opaque, int dcrn) |
| 985 |
{
|
| 986 |
ppc405_dma_t *dma; |
| 987 |
|
| 988 |
dma = opaque; |
| 989 |
|
| 990 |
return 0; |
| 991 |
} |
| 992 |
|
| 993 |
static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) |
| 994 |
{
|
| 995 |
ppc405_dma_t *dma; |
| 996 |
|
| 997 |
dma = opaque; |
| 998 |
} |
| 999 |
|
| 1000 |
static void ppc405_dma_reset (void *opaque) |
| 1001 |
{
|
| 1002 |
ppc405_dma_t *dma; |
| 1003 |
int i;
|
| 1004 |
|
| 1005 |
dma = opaque; |
| 1006 |
for (i = 0; i < 4; i++) { |
| 1007 |
dma->cr[i] = 0x00000000;
|
| 1008 |
dma->ct[i] = 0x00000000;
|
| 1009 |
dma->da[i] = 0x00000000;
|
| 1010 |
dma->sa[i] = 0x00000000;
|
| 1011 |
dma->sg[i] = 0x00000000;
|
| 1012 |
} |
| 1013 |
dma->sr = 0x00000000;
|
| 1014 |
dma->sgc = 0x00000000;
|
| 1015 |
dma->slp = 0x7C000000;
|
| 1016 |
dma->pol = 0x00000000;
|
| 1017 |
} |
| 1018 |
|
| 1019 |
void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]) |
| 1020 |
{
|
| 1021 |
ppc405_dma_t *dma; |
| 1022 |
|
| 1023 |
dma = qemu_mallocz(sizeof(ppc405_dma_t));
|
| 1024 |
if (dma != NULL) { |
| 1025 |
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
| 1026 |
ppc405_dma_reset(dma); |
| 1027 |
qemu_register_reset(&ppc405_dma_reset, dma); |
| 1028 |
ppc_dcr_register(env, DMA0_CR0, |
| 1029 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1030 |
ppc_dcr_register(env, DMA0_CT0, |
| 1031 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1032 |
ppc_dcr_register(env, DMA0_DA0, |
| 1033 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1034 |
ppc_dcr_register(env, DMA0_SA0, |
| 1035 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1036 |
ppc_dcr_register(env, DMA0_SG0, |
| 1037 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1038 |
ppc_dcr_register(env, DMA0_CR1, |
| 1039 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1040 |
ppc_dcr_register(env, DMA0_CT1, |
| 1041 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1042 |
ppc_dcr_register(env, DMA0_DA1, |
| 1043 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1044 |
ppc_dcr_register(env, DMA0_SA1, |
| 1045 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1046 |
ppc_dcr_register(env, DMA0_SG1, |
| 1047 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1048 |
ppc_dcr_register(env, DMA0_CR2, |
| 1049 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1050 |
ppc_dcr_register(env, DMA0_CT2, |
| 1051 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1052 |
ppc_dcr_register(env, DMA0_DA2, |
| 1053 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1054 |
ppc_dcr_register(env, DMA0_SA2, |
| 1055 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1056 |
ppc_dcr_register(env, DMA0_SG2, |
| 1057 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1058 |
ppc_dcr_register(env, DMA0_CR3, |
| 1059 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1060 |
ppc_dcr_register(env, DMA0_CT3, |
| 1061 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1062 |
ppc_dcr_register(env, DMA0_DA3, |
| 1063 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1064 |
ppc_dcr_register(env, DMA0_SA3, |
| 1065 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1066 |
ppc_dcr_register(env, DMA0_SG3, |
| 1067 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1068 |
ppc_dcr_register(env, DMA0_SR, |
| 1069 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1070 |
ppc_dcr_register(env, DMA0_SGC, |
| 1071 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1072 |
ppc_dcr_register(env, DMA0_SLP, |
| 1073 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1074 |
ppc_dcr_register(env, DMA0_POL, |
| 1075 |
dma, &dcr_read_dma, &dcr_write_dma); |
| 1076 |
} |
| 1077 |
} |
| 1078 |
|
| 1079 |
/*****************************************************************************/
|
| 1080 |
/* GPIO */
|
| 1081 |
typedef struct ppc405_gpio_t ppc405_gpio_t; |
| 1082 |
struct ppc405_gpio_t {
|
| 1083 |
target_phys_addr_t base; |
| 1084 |
uint32_t or; |
| 1085 |
uint32_t tcr; |
| 1086 |
uint32_t osrh; |
| 1087 |
uint32_t osrl; |
| 1088 |
uint32_t tsrh; |
| 1089 |
uint32_t tsrl; |
| 1090 |
uint32_t odr; |
| 1091 |
uint32_t ir; |
| 1092 |
uint32_t rr1; |
| 1093 |
uint32_t isr1h; |
| 1094 |
uint32_t isr1l; |
| 1095 |
}; |
| 1096 |
|
| 1097 |
static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) |
| 1098 |
{
|
| 1099 |
ppc405_gpio_t *gpio; |
| 1100 |
|
| 1101 |
gpio = opaque; |
| 1102 |
#ifdef DEBUG_GPIO
|
| 1103 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1104 |
#endif
|
| 1105 |
|
| 1106 |
return 0; |
| 1107 |
} |
| 1108 |
|
| 1109 |
static void ppc405_gpio_writeb (void *opaque, |
| 1110 |
target_phys_addr_t addr, uint32_t value) |
| 1111 |
{
|
| 1112 |
ppc405_gpio_t *gpio; |
| 1113 |
|
| 1114 |
gpio = opaque; |
| 1115 |
#ifdef DEBUG_GPIO
|
| 1116 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1117 |
#endif
|
| 1118 |
} |
| 1119 |
|
| 1120 |
static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) |
| 1121 |
{
|
| 1122 |
ppc405_gpio_t *gpio; |
| 1123 |
|
| 1124 |
gpio = opaque; |
| 1125 |
#ifdef DEBUG_GPIO
|
| 1126 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1127 |
#endif
|
| 1128 |
|
| 1129 |
return 0; |
| 1130 |
} |
| 1131 |
|
| 1132 |
static void ppc405_gpio_writew (void *opaque, |
| 1133 |
target_phys_addr_t addr, uint32_t value) |
| 1134 |
{
|
| 1135 |
ppc405_gpio_t *gpio; |
| 1136 |
|
| 1137 |
gpio = opaque; |
| 1138 |
#ifdef DEBUG_GPIO
|
| 1139 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1140 |
#endif
|
| 1141 |
} |
| 1142 |
|
| 1143 |
static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) |
| 1144 |
{
|
| 1145 |
ppc405_gpio_t *gpio; |
| 1146 |
|
| 1147 |
gpio = opaque; |
| 1148 |
#ifdef DEBUG_GPIO
|
| 1149 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1150 |
#endif
|
| 1151 |
|
| 1152 |
return 0; |
| 1153 |
} |
| 1154 |
|
| 1155 |
static void ppc405_gpio_writel (void *opaque, |
| 1156 |
target_phys_addr_t addr, uint32_t value) |
| 1157 |
{
|
| 1158 |
ppc405_gpio_t *gpio; |
| 1159 |
|
| 1160 |
gpio = opaque; |
| 1161 |
#ifdef DEBUG_GPIO
|
| 1162 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1163 |
#endif
|
| 1164 |
} |
| 1165 |
|
| 1166 |
static CPUReadMemoryFunc *ppc405_gpio_read[] = {
|
| 1167 |
&ppc405_gpio_readb, |
| 1168 |
&ppc405_gpio_readw, |
| 1169 |
&ppc405_gpio_readl, |
| 1170 |
}; |
| 1171 |
|
| 1172 |
static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
|
| 1173 |
&ppc405_gpio_writeb, |
| 1174 |
&ppc405_gpio_writew, |
| 1175 |
&ppc405_gpio_writel, |
| 1176 |
}; |
| 1177 |
|
| 1178 |
static void ppc405_gpio_reset (void *opaque) |
| 1179 |
{
|
| 1180 |
ppc405_gpio_t *gpio; |
| 1181 |
|
| 1182 |
gpio = opaque; |
| 1183 |
} |
| 1184 |
|
| 1185 |
void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
| 1186 |
target_phys_addr_t offset) |
| 1187 |
{
|
| 1188 |
ppc405_gpio_t *gpio; |
| 1189 |
|
| 1190 |
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
|
| 1191 |
if (gpio != NULL) { |
| 1192 |
gpio->base = offset; |
| 1193 |
ppc405_gpio_reset(gpio); |
| 1194 |
qemu_register_reset(&ppc405_gpio_reset, gpio); |
| 1195 |
#ifdef DEBUG_GPIO
|
| 1196 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
| 1197 |
#endif
|
| 1198 |
ppc4xx_mmio_register(env, mmio, offset, 0x038,
|
| 1199 |
ppc405_gpio_read, ppc405_gpio_write, gpio); |
| 1200 |
} |
| 1201 |
} |
| 1202 |
|
| 1203 |
/*****************************************************************************/
|
| 1204 |
/* Serial ports */
|
| 1205 |
static CPUReadMemoryFunc *serial_mm_read[] = {
|
| 1206 |
&serial_mm_readb, |
| 1207 |
&serial_mm_readw, |
| 1208 |
&serial_mm_readl, |
| 1209 |
}; |
| 1210 |
|
| 1211 |
static CPUWriteMemoryFunc *serial_mm_write[] = {
|
| 1212 |
&serial_mm_writeb, |
| 1213 |
&serial_mm_writew, |
| 1214 |
&serial_mm_writel, |
| 1215 |
}; |
| 1216 |
|
| 1217 |
void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
| 1218 |
target_phys_addr_t offset, qemu_irq irq, |
| 1219 |
CharDriverState *chr) |
| 1220 |
{
|
| 1221 |
void *serial;
|
| 1222 |
|
| 1223 |
#ifdef DEBUG_SERIAL
|
| 1224 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
| 1225 |
#endif
|
| 1226 |
serial = serial_mm_init(offset, 0, irq, 399193, chr, 0); |
| 1227 |
ppc4xx_mmio_register(env, mmio, offset, 0x008,
|
| 1228 |
serial_mm_read, serial_mm_write, serial); |
| 1229 |
} |
| 1230 |
|
| 1231 |
/*****************************************************************************/
|
| 1232 |
/* On Chip Memory */
|
| 1233 |
enum {
|
| 1234 |
OCM0_ISARC = 0x018,
|
| 1235 |
OCM0_ISACNTL = 0x019,
|
| 1236 |
OCM0_DSARC = 0x01A,
|
| 1237 |
OCM0_DSACNTL = 0x01B,
|
| 1238 |
}; |
| 1239 |
|
| 1240 |
typedef struct ppc405_ocm_t ppc405_ocm_t; |
| 1241 |
struct ppc405_ocm_t {
|
| 1242 |
target_ulong offset; |
| 1243 |
uint32_t isarc; |
| 1244 |
uint32_t isacntl; |
| 1245 |
uint32_t dsarc; |
| 1246 |
uint32_t dsacntl; |
| 1247 |
}; |
| 1248 |
|
| 1249 |
static void ocm_update_mappings (ppc405_ocm_t *ocm, |
| 1250 |
uint32_t isarc, uint32_t isacntl, |
| 1251 |
uint32_t dsarc, uint32_t dsacntl) |
| 1252 |
{
|
| 1253 |
#ifdef DEBUG_OCM
|
| 1254 |
printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 |
| 1255 |
" %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 |
| 1256 |
" (%08" PRIx32 " %08" PRIx32 ")\n", |
| 1257 |
isarc, isacntl, dsarc, dsacntl, |
| 1258 |
ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); |
| 1259 |
#endif
|
| 1260 |
if (ocm->isarc != isarc ||
|
| 1261 |
(ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { |
| 1262 |
if (ocm->isacntl & 0x80000000) { |
| 1263 |
/* Unmap previously assigned memory region */
|
| 1264 |
printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); |
| 1265 |
cpu_register_physical_memory(ocm->isarc, 0x04000000,
|
| 1266 |
IO_MEM_UNASSIGNED); |
| 1267 |
} |
| 1268 |
if (isacntl & 0x80000000) { |
| 1269 |
/* Map new instruction memory region */
|
| 1270 |
#ifdef DEBUG_OCM
|
| 1271 |
printf("OCM map ISA %08" PRIx32 "\n", isarc); |
| 1272 |
#endif
|
| 1273 |
cpu_register_physical_memory(isarc, 0x04000000,
|
| 1274 |
ocm->offset | IO_MEM_RAM); |
| 1275 |
} |
| 1276 |
} |
| 1277 |
if (ocm->dsarc != dsarc ||
|
| 1278 |
(ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { |
| 1279 |
if (ocm->dsacntl & 0x80000000) { |
| 1280 |
/* Beware not to unmap the region we just mapped */
|
| 1281 |
if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { |
| 1282 |
/* Unmap previously assigned memory region */
|
| 1283 |
#ifdef DEBUG_OCM
|
| 1284 |
printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); |
| 1285 |
#endif
|
| 1286 |
cpu_register_physical_memory(ocm->dsarc, 0x04000000,
|
| 1287 |
IO_MEM_UNASSIGNED); |
| 1288 |
} |
| 1289 |
} |
| 1290 |
if (dsacntl & 0x80000000) { |
| 1291 |
/* Beware not to remap the region we just mapped */
|
| 1292 |
if (!(isacntl & 0x80000000) || dsarc != isarc) { |
| 1293 |
/* Map new data memory region */
|
| 1294 |
#ifdef DEBUG_OCM
|
| 1295 |
printf("OCM map DSA %08" PRIx32 "\n", dsarc); |
| 1296 |
#endif
|
| 1297 |
cpu_register_physical_memory(dsarc, 0x04000000,
|
| 1298 |
ocm->offset | IO_MEM_RAM); |
| 1299 |
} |
| 1300 |
} |
| 1301 |
} |
| 1302 |
} |
| 1303 |
|
| 1304 |
static target_ulong dcr_read_ocm (void *opaque, int dcrn) |
| 1305 |
{
|
| 1306 |
ppc405_ocm_t *ocm; |
| 1307 |
target_ulong ret; |
| 1308 |
|
| 1309 |
ocm = opaque; |
| 1310 |
switch (dcrn) {
|
| 1311 |
case OCM0_ISARC:
|
| 1312 |
ret = ocm->isarc; |
| 1313 |
break;
|
| 1314 |
case OCM0_ISACNTL:
|
| 1315 |
ret = ocm->isacntl; |
| 1316 |
break;
|
| 1317 |
case OCM0_DSARC:
|
| 1318 |
ret = ocm->dsarc; |
| 1319 |
break;
|
| 1320 |
case OCM0_DSACNTL:
|
| 1321 |
ret = ocm->dsacntl; |
| 1322 |
break;
|
| 1323 |
default:
|
| 1324 |
ret = 0;
|
| 1325 |
break;
|
| 1326 |
} |
| 1327 |
|
| 1328 |
return ret;
|
| 1329 |
} |
| 1330 |
|
| 1331 |
static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) |
| 1332 |
{
|
| 1333 |
ppc405_ocm_t *ocm; |
| 1334 |
uint32_t isarc, dsarc, isacntl, dsacntl; |
| 1335 |
|
| 1336 |
ocm = opaque; |
| 1337 |
isarc = ocm->isarc; |
| 1338 |
dsarc = ocm->dsarc; |
| 1339 |
isacntl = ocm->isacntl; |
| 1340 |
dsacntl = ocm->dsacntl; |
| 1341 |
switch (dcrn) {
|
| 1342 |
case OCM0_ISARC:
|
| 1343 |
isarc = val & 0xFC000000;
|
| 1344 |
break;
|
| 1345 |
case OCM0_ISACNTL:
|
| 1346 |
isacntl = val & 0xC0000000;
|
| 1347 |
break;
|
| 1348 |
case OCM0_DSARC:
|
| 1349 |
isarc = val & 0xFC000000;
|
| 1350 |
break;
|
| 1351 |
case OCM0_DSACNTL:
|
| 1352 |
isacntl = val & 0xC0000000;
|
| 1353 |
break;
|
| 1354 |
} |
| 1355 |
ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
| 1356 |
ocm->isarc = isarc; |
| 1357 |
ocm->dsarc = dsarc; |
| 1358 |
ocm->isacntl = isacntl; |
| 1359 |
ocm->dsacntl = dsacntl; |
| 1360 |
} |
| 1361 |
|
| 1362 |
static void ocm_reset (void *opaque) |
| 1363 |
{
|
| 1364 |
ppc405_ocm_t *ocm; |
| 1365 |
uint32_t isarc, dsarc, isacntl, dsacntl; |
| 1366 |
|
| 1367 |
ocm = opaque; |
| 1368 |
isarc = 0x00000000;
|
| 1369 |
isacntl = 0x00000000;
|
| 1370 |
dsarc = 0x00000000;
|
| 1371 |
dsacntl = 0x00000000;
|
| 1372 |
ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
| 1373 |
ocm->isarc = isarc; |
| 1374 |
ocm->dsarc = dsarc; |
| 1375 |
ocm->isacntl = isacntl; |
| 1376 |
ocm->dsacntl = dsacntl; |
| 1377 |
} |
| 1378 |
|
| 1379 |
void ppc405_ocm_init (CPUState *env, unsigned long offset) |
| 1380 |
{
|
| 1381 |
ppc405_ocm_t *ocm; |
| 1382 |
|
| 1383 |
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
|
| 1384 |
if (ocm != NULL) { |
| 1385 |
ocm->offset = offset; |
| 1386 |
ocm_reset(ocm); |
| 1387 |
qemu_register_reset(&ocm_reset, ocm); |
| 1388 |
ppc_dcr_register(env, OCM0_ISARC, |
| 1389 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
| 1390 |
ppc_dcr_register(env, OCM0_ISACNTL, |
| 1391 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
| 1392 |
ppc_dcr_register(env, OCM0_DSARC, |
| 1393 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
| 1394 |
ppc_dcr_register(env, OCM0_DSACNTL, |
| 1395 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
| 1396 |
} |
| 1397 |
} |
| 1398 |
|
| 1399 |
/*****************************************************************************/
|
| 1400 |
/* I2C controller */
|
| 1401 |
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; |
| 1402 |
struct ppc4xx_i2c_t {
|
| 1403 |
target_phys_addr_t base; |
| 1404 |
qemu_irq irq; |
| 1405 |
uint8_t mdata; |
| 1406 |
uint8_t lmadr; |
| 1407 |
uint8_t hmadr; |
| 1408 |
uint8_t cntl; |
| 1409 |
uint8_t mdcntl; |
| 1410 |
uint8_t sts; |
| 1411 |
uint8_t extsts; |
| 1412 |
uint8_t sdata; |
| 1413 |
uint8_t lsadr; |
| 1414 |
uint8_t hsadr; |
| 1415 |
uint8_t clkdiv; |
| 1416 |
uint8_t intrmsk; |
| 1417 |
uint8_t xfrcnt; |
| 1418 |
uint8_t xtcntlss; |
| 1419 |
uint8_t directcntl; |
| 1420 |
}; |
| 1421 |
|
| 1422 |
static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) |
| 1423 |
{
|
| 1424 |
ppc4xx_i2c_t *i2c; |
| 1425 |
uint32_t ret; |
| 1426 |
|
| 1427 |
#ifdef DEBUG_I2C
|
| 1428 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1429 |
#endif
|
| 1430 |
i2c = opaque; |
| 1431 |
switch (addr - i2c->base) {
|
| 1432 |
case 0x00: |
| 1433 |
// i2c_readbyte(&i2c->mdata);
|
| 1434 |
ret = i2c->mdata; |
| 1435 |
break;
|
| 1436 |
case 0x02: |
| 1437 |
ret = i2c->sdata; |
| 1438 |
break;
|
| 1439 |
case 0x04: |
| 1440 |
ret = i2c->lmadr; |
| 1441 |
break;
|
| 1442 |
case 0x05: |
| 1443 |
ret = i2c->hmadr; |
| 1444 |
break;
|
| 1445 |
case 0x06: |
| 1446 |
ret = i2c->cntl; |
| 1447 |
break;
|
| 1448 |
case 0x07: |
| 1449 |
ret = i2c->mdcntl; |
| 1450 |
break;
|
| 1451 |
case 0x08: |
| 1452 |
ret = i2c->sts; |
| 1453 |
break;
|
| 1454 |
case 0x09: |
| 1455 |
ret = i2c->extsts; |
| 1456 |
break;
|
| 1457 |
case 0x0A: |
| 1458 |
ret = i2c->lsadr; |
| 1459 |
break;
|
| 1460 |
case 0x0B: |
| 1461 |
ret = i2c->hsadr; |
| 1462 |
break;
|
| 1463 |
case 0x0C: |
| 1464 |
ret = i2c->clkdiv; |
| 1465 |
break;
|
| 1466 |
case 0x0D: |
| 1467 |
ret = i2c->intrmsk; |
| 1468 |
break;
|
| 1469 |
case 0x0E: |
| 1470 |
ret = i2c->xfrcnt; |
| 1471 |
break;
|
| 1472 |
case 0x0F: |
| 1473 |
ret = i2c->xtcntlss; |
| 1474 |
break;
|
| 1475 |
case 0x10: |
| 1476 |
ret = i2c->directcntl; |
| 1477 |
break;
|
| 1478 |
default:
|
| 1479 |
ret = 0x00;
|
| 1480 |
break;
|
| 1481 |
} |
| 1482 |
#ifdef DEBUG_I2C
|
| 1483 |
printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret); |
| 1484 |
#endif
|
| 1485 |
|
| 1486 |
return ret;
|
| 1487 |
} |
| 1488 |
|
| 1489 |
static void ppc4xx_i2c_writeb (void *opaque, |
| 1490 |
target_phys_addr_t addr, uint32_t value) |
| 1491 |
{
|
| 1492 |
ppc4xx_i2c_t *i2c; |
| 1493 |
|
| 1494 |
#ifdef DEBUG_I2C
|
| 1495 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1496 |
#endif
|
| 1497 |
i2c = opaque; |
| 1498 |
switch (addr - i2c->base) {
|
| 1499 |
case 0x00: |
| 1500 |
i2c->mdata = value; |
| 1501 |
// i2c_sendbyte(&i2c->mdata);
|
| 1502 |
break;
|
| 1503 |
case 0x02: |
| 1504 |
i2c->sdata = value; |
| 1505 |
break;
|
| 1506 |
case 0x04: |
| 1507 |
i2c->lmadr = value; |
| 1508 |
break;
|
| 1509 |
case 0x05: |
| 1510 |
i2c->hmadr = value; |
| 1511 |
break;
|
| 1512 |
case 0x06: |
| 1513 |
i2c->cntl = value; |
| 1514 |
break;
|
| 1515 |
case 0x07: |
| 1516 |
i2c->mdcntl = value & 0xDF;
|
| 1517 |
break;
|
| 1518 |
case 0x08: |
| 1519 |
i2c->sts &= ~(value & 0x0A);
|
| 1520 |
break;
|
| 1521 |
case 0x09: |
| 1522 |
i2c->extsts &= ~(value & 0x8F);
|
| 1523 |
break;
|
| 1524 |
case 0x0A: |
| 1525 |
i2c->lsadr = value; |
| 1526 |
break;
|
| 1527 |
case 0x0B: |
| 1528 |
i2c->hsadr = value; |
| 1529 |
break;
|
| 1530 |
case 0x0C: |
| 1531 |
i2c->clkdiv = value; |
| 1532 |
break;
|
| 1533 |
case 0x0D: |
| 1534 |
i2c->intrmsk = value; |
| 1535 |
break;
|
| 1536 |
case 0x0E: |
| 1537 |
i2c->xfrcnt = value & 0x77;
|
| 1538 |
break;
|
| 1539 |
case 0x0F: |
| 1540 |
i2c->xtcntlss = value; |
| 1541 |
break;
|
| 1542 |
case 0x10: |
| 1543 |
i2c->directcntl = value & 0x7;
|
| 1544 |
break;
|
| 1545 |
} |
| 1546 |
} |
| 1547 |
|
| 1548 |
static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) |
| 1549 |
{
|
| 1550 |
uint32_t ret; |
| 1551 |
|
| 1552 |
#ifdef DEBUG_I2C
|
| 1553 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1554 |
#endif
|
| 1555 |
ret = ppc4xx_i2c_readb(opaque, addr) << 8;
|
| 1556 |
ret |= ppc4xx_i2c_readb(opaque, addr + 1);
|
| 1557 |
|
| 1558 |
return ret;
|
| 1559 |
} |
| 1560 |
|
| 1561 |
static void ppc4xx_i2c_writew (void *opaque, |
| 1562 |
target_phys_addr_t addr, uint32_t value) |
| 1563 |
{
|
| 1564 |
#ifdef DEBUG_I2C
|
| 1565 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1566 |
#endif
|
| 1567 |
ppc4xx_i2c_writeb(opaque, addr, value >> 8);
|
| 1568 |
ppc4xx_i2c_writeb(opaque, addr + 1, value);
|
| 1569 |
} |
| 1570 |
|
| 1571 |
static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) |
| 1572 |
{
|
| 1573 |
uint32_t ret; |
| 1574 |
|
| 1575 |
#ifdef DEBUG_I2C
|
| 1576 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1577 |
#endif
|
| 1578 |
ret = ppc4xx_i2c_readb(opaque, addr) << 24;
|
| 1579 |
ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16; |
| 1580 |
ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8; |
| 1581 |
ret |= ppc4xx_i2c_readb(opaque, addr + 3);
|
| 1582 |
|
| 1583 |
return ret;
|
| 1584 |
} |
| 1585 |
|
| 1586 |
static void ppc4xx_i2c_writel (void *opaque, |
| 1587 |
target_phys_addr_t addr, uint32_t value) |
| 1588 |
{
|
| 1589 |
#ifdef DEBUG_I2C
|
| 1590 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1591 |
#endif
|
| 1592 |
ppc4xx_i2c_writeb(opaque, addr, value >> 24);
|
| 1593 |
ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); |
| 1594 |
ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8); |
| 1595 |
ppc4xx_i2c_writeb(opaque, addr + 3, value);
|
| 1596 |
} |
| 1597 |
|
| 1598 |
static CPUReadMemoryFunc *i2c_read[] = {
|
| 1599 |
&ppc4xx_i2c_readb, |
| 1600 |
&ppc4xx_i2c_readw, |
| 1601 |
&ppc4xx_i2c_readl, |
| 1602 |
}; |
| 1603 |
|
| 1604 |
static CPUWriteMemoryFunc *i2c_write[] = {
|
| 1605 |
&ppc4xx_i2c_writeb, |
| 1606 |
&ppc4xx_i2c_writew, |
| 1607 |
&ppc4xx_i2c_writel, |
| 1608 |
}; |
| 1609 |
|
| 1610 |
static void ppc4xx_i2c_reset (void *opaque) |
| 1611 |
{
|
| 1612 |
ppc4xx_i2c_t *i2c; |
| 1613 |
|
| 1614 |
i2c = opaque; |
| 1615 |
i2c->mdata = 0x00;
|
| 1616 |
i2c->sdata = 0x00;
|
| 1617 |
i2c->cntl = 0x00;
|
| 1618 |
i2c->mdcntl = 0x00;
|
| 1619 |
i2c->sts = 0x00;
|
| 1620 |
i2c->extsts = 0x00;
|
| 1621 |
i2c->clkdiv = 0x00;
|
| 1622 |
i2c->xfrcnt = 0x00;
|
| 1623 |
i2c->directcntl = 0x0F;
|
| 1624 |
} |
| 1625 |
|
| 1626 |
void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
| 1627 |
target_phys_addr_t offset, qemu_irq irq) |
| 1628 |
{
|
| 1629 |
ppc4xx_i2c_t *i2c; |
| 1630 |
|
| 1631 |
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
|
| 1632 |
if (i2c != NULL) { |
| 1633 |
i2c->base = offset; |
| 1634 |
i2c->irq = irq; |
| 1635 |
ppc4xx_i2c_reset(i2c); |
| 1636 |
#ifdef DEBUG_I2C
|
| 1637 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
| 1638 |
#endif
|
| 1639 |
ppc4xx_mmio_register(env, mmio, offset, 0x011,
|
| 1640 |
i2c_read, i2c_write, i2c); |
| 1641 |
qemu_register_reset(ppc4xx_i2c_reset, i2c); |
| 1642 |
} |
| 1643 |
} |
| 1644 |
|
| 1645 |
/*****************************************************************************/
|
| 1646 |
/* General purpose timers */
|
| 1647 |
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; |
| 1648 |
struct ppc4xx_gpt_t {
|
| 1649 |
target_phys_addr_t base; |
| 1650 |
int64_t tb_offset; |
| 1651 |
uint32_t tb_freq; |
| 1652 |
struct QEMUTimer *timer;
|
| 1653 |
qemu_irq irqs[5];
|
| 1654 |
uint32_t oe; |
| 1655 |
uint32_t ol; |
| 1656 |
uint32_t im; |
| 1657 |
uint32_t is; |
| 1658 |
uint32_t ie; |
| 1659 |
uint32_t comp[5];
|
| 1660 |
uint32_t mask[5];
|
| 1661 |
}; |
| 1662 |
|
| 1663 |
static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) |
| 1664 |
{
|
| 1665 |
#ifdef DEBUG_GPT
|
| 1666 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1667 |
#endif
|
| 1668 |
/* XXX: generate a bus fault */
|
| 1669 |
return -1; |
| 1670 |
} |
| 1671 |
|
| 1672 |
static void ppc4xx_gpt_writeb (void *opaque, |
| 1673 |
target_phys_addr_t addr, uint32_t value) |
| 1674 |
{
|
| 1675 |
#ifdef DEBUG_I2C
|
| 1676 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1677 |
#endif
|
| 1678 |
/* XXX: generate a bus fault */
|
| 1679 |
} |
| 1680 |
|
| 1681 |
static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) |
| 1682 |
{
|
| 1683 |
#ifdef DEBUG_GPT
|
| 1684 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1685 |
#endif
|
| 1686 |
/* XXX: generate a bus fault */
|
| 1687 |
return -1; |
| 1688 |
} |
| 1689 |
|
| 1690 |
static void ppc4xx_gpt_writew (void *opaque, |
| 1691 |
target_phys_addr_t addr, uint32_t value) |
| 1692 |
{
|
| 1693 |
#ifdef DEBUG_I2C
|
| 1694 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1695 |
#endif
|
| 1696 |
/* XXX: generate a bus fault */
|
| 1697 |
} |
| 1698 |
|
| 1699 |
static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) |
| 1700 |
{
|
| 1701 |
/* XXX: TODO */
|
| 1702 |
return 0; |
| 1703 |
} |
| 1704 |
|
| 1705 |
static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) |
| 1706 |
{
|
| 1707 |
/* XXX: TODO */
|
| 1708 |
} |
| 1709 |
|
| 1710 |
static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) |
| 1711 |
{
|
| 1712 |
uint32_t mask; |
| 1713 |
int i;
|
| 1714 |
|
| 1715 |
mask = 0x80000000;
|
| 1716 |
for (i = 0; i < 5; i++) { |
| 1717 |
if (gpt->oe & mask) {
|
| 1718 |
/* Output is enabled */
|
| 1719 |
if (ppc4xx_gpt_compare(gpt, i)) {
|
| 1720 |
/* Comparison is OK */
|
| 1721 |
ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); |
| 1722 |
} else {
|
| 1723 |
/* Comparison is KO */
|
| 1724 |
ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); |
| 1725 |
} |
| 1726 |
} |
| 1727 |
mask = mask >> 1;
|
| 1728 |
} |
| 1729 |
} |
| 1730 |
|
| 1731 |
static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) |
| 1732 |
{
|
| 1733 |
uint32_t mask; |
| 1734 |
int i;
|
| 1735 |
|
| 1736 |
mask = 0x00008000;
|
| 1737 |
for (i = 0; i < 5; i++) { |
| 1738 |
if (gpt->is & gpt->im & mask)
|
| 1739 |
qemu_irq_raise(gpt->irqs[i]); |
| 1740 |
else
|
| 1741 |
qemu_irq_lower(gpt->irqs[i]); |
| 1742 |
mask = mask >> 1;
|
| 1743 |
} |
| 1744 |
} |
| 1745 |
|
| 1746 |
static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) |
| 1747 |
{
|
| 1748 |
/* XXX: TODO */
|
| 1749 |
} |
| 1750 |
|
| 1751 |
static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) |
| 1752 |
{
|
| 1753 |
ppc4xx_gpt_t *gpt; |
| 1754 |
uint32_t ret; |
| 1755 |
int idx;
|
| 1756 |
|
| 1757 |
#ifdef DEBUG_GPT
|
| 1758 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1759 |
#endif
|
| 1760 |
gpt = opaque; |
| 1761 |
switch (addr - gpt->base) {
|
| 1762 |
case 0x00: |
| 1763 |
/* Time base counter */
|
| 1764 |
ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, |
| 1765 |
gpt->tb_freq, ticks_per_sec); |
| 1766 |
break;
|
| 1767 |
case 0x10: |
| 1768 |
/* Output enable */
|
| 1769 |
ret = gpt->oe; |
| 1770 |
break;
|
| 1771 |
case 0x14: |
| 1772 |
/* Output level */
|
| 1773 |
ret = gpt->ol; |
| 1774 |
break;
|
| 1775 |
case 0x18: |
| 1776 |
/* Interrupt mask */
|
| 1777 |
ret = gpt->im; |
| 1778 |
break;
|
| 1779 |
case 0x1C: |
| 1780 |
case 0x20: |
| 1781 |
/* Interrupt status */
|
| 1782 |
ret = gpt->is; |
| 1783 |
break;
|
| 1784 |
case 0x24: |
| 1785 |
/* Interrupt enable */
|
| 1786 |
ret = gpt->ie; |
| 1787 |
break;
|
| 1788 |
case 0x80 ... 0x90: |
| 1789 |
/* Compare timer */
|
| 1790 |
idx = ((addr - gpt->base) - 0x80) >> 2; |
| 1791 |
ret = gpt->comp[idx]; |
| 1792 |
break;
|
| 1793 |
case 0xC0 ... 0xD0: |
| 1794 |
/* Compare mask */
|
| 1795 |
idx = ((addr - gpt->base) - 0xC0) >> 2; |
| 1796 |
ret = gpt->mask[idx]; |
| 1797 |
break;
|
| 1798 |
default:
|
| 1799 |
ret = -1;
|
| 1800 |
break;
|
| 1801 |
} |
| 1802 |
|
| 1803 |
return ret;
|
| 1804 |
} |
| 1805 |
|
| 1806 |
static void ppc4xx_gpt_writel (void *opaque, |
| 1807 |
target_phys_addr_t addr, uint32_t value) |
| 1808 |
{
|
| 1809 |
ppc4xx_gpt_t *gpt; |
| 1810 |
int idx;
|
| 1811 |
|
| 1812 |
#ifdef DEBUG_I2C
|
| 1813 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1814 |
#endif
|
| 1815 |
gpt = opaque; |
| 1816 |
switch (addr - gpt->base) {
|
| 1817 |
case 0x00: |
| 1818 |
/* Time base counter */
|
| 1819 |
gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq) |
| 1820 |
- qemu_get_clock(vm_clock); |
| 1821 |
ppc4xx_gpt_compute_timer(gpt); |
| 1822 |
break;
|
| 1823 |
case 0x10: |
| 1824 |
/* Output enable */
|
| 1825 |
gpt->oe = value & 0xF8000000;
|
| 1826 |
ppc4xx_gpt_set_outputs(gpt); |
| 1827 |
break;
|
| 1828 |
case 0x14: |
| 1829 |
/* Output level */
|
| 1830 |
gpt->ol = value & 0xF8000000;
|
| 1831 |
ppc4xx_gpt_set_outputs(gpt); |
| 1832 |
break;
|
| 1833 |
case 0x18: |
| 1834 |
/* Interrupt mask */
|
| 1835 |
gpt->im = value & 0x0000F800;
|
| 1836 |
break;
|
| 1837 |
case 0x1C: |
| 1838 |
/* Interrupt status set */
|
| 1839 |
gpt->is |= value & 0x0000F800;
|
| 1840 |
ppc4xx_gpt_set_irqs(gpt); |
| 1841 |
break;
|
| 1842 |
case 0x20: |
| 1843 |
/* Interrupt status clear */
|
| 1844 |
gpt->is &= ~(value & 0x0000F800);
|
| 1845 |
ppc4xx_gpt_set_irqs(gpt); |
| 1846 |
break;
|
| 1847 |
case 0x24: |
| 1848 |
/* Interrupt enable */
|
| 1849 |
gpt->ie = value & 0x0000F800;
|
| 1850 |
ppc4xx_gpt_set_irqs(gpt); |
| 1851 |
break;
|
| 1852 |
case 0x80 ... 0x90: |
| 1853 |
/* Compare timer */
|
| 1854 |
idx = ((addr - gpt->base) - 0x80) >> 2; |
| 1855 |
gpt->comp[idx] = value & 0xF8000000;
|
| 1856 |
ppc4xx_gpt_compute_timer(gpt); |
| 1857 |
break;
|
| 1858 |
case 0xC0 ... 0xD0: |
| 1859 |
/* Compare mask */
|
| 1860 |
idx = ((addr - gpt->base) - 0xC0) >> 2; |
| 1861 |
gpt->mask[idx] = value & 0xF8000000;
|
| 1862 |
ppc4xx_gpt_compute_timer(gpt); |
| 1863 |
break;
|
| 1864 |
} |
| 1865 |
} |
| 1866 |
|
| 1867 |
static CPUReadMemoryFunc *gpt_read[] = {
|
| 1868 |
&ppc4xx_gpt_readb, |
| 1869 |
&ppc4xx_gpt_readw, |
| 1870 |
&ppc4xx_gpt_readl, |
| 1871 |
}; |
| 1872 |
|
| 1873 |
static CPUWriteMemoryFunc *gpt_write[] = {
|
| 1874 |
&ppc4xx_gpt_writeb, |
| 1875 |
&ppc4xx_gpt_writew, |
| 1876 |
&ppc4xx_gpt_writel, |
| 1877 |
}; |
| 1878 |
|
| 1879 |
static void ppc4xx_gpt_cb (void *opaque) |
| 1880 |
{
|
| 1881 |
ppc4xx_gpt_t *gpt; |
| 1882 |
|
| 1883 |
gpt = opaque; |
| 1884 |
ppc4xx_gpt_set_irqs(gpt); |
| 1885 |
ppc4xx_gpt_set_outputs(gpt); |
| 1886 |
ppc4xx_gpt_compute_timer(gpt); |
| 1887 |
} |
| 1888 |
|
| 1889 |
static void ppc4xx_gpt_reset (void *opaque) |
| 1890 |
{
|
| 1891 |
ppc4xx_gpt_t *gpt; |
| 1892 |
int i;
|
| 1893 |
|
| 1894 |
gpt = opaque; |
| 1895 |
qemu_del_timer(gpt->timer); |
| 1896 |
gpt->oe = 0x00000000;
|
| 1897 |
gpt->ol = 0x00000000;
|
| 1898 |
gpt->im = 0x00000000;
|
| 1899 |
gpt->is = 0x00000000;
|
| 1900 |
gpt->ie = 0x00000000;
|
| 1901 |
for (i = 0; i < 5; i++) { |
| 1902 |
gpt->comp[i] = 0x00000000;
|
| 1903 |
gpt->mask[i] = 0x00000000;
|
| 1904 |
} |
| 1905 |
} |
| 1906 |
|
| 1907 |
void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
| 1908 |
target_phys_addr_t offset, qemu_irq irqs[5])
|
| 1909 |
{
|
| 1910 |
ppc4xx_gpt_t *gpt; |
| 1911 |
int i;
|
| 1912 |
|
| 1913 |
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
|
| 1914 |
if (gpt != NULL) { |
| 1915 |
gpt->base = offset; |
| 1916 |
for (i = 0; i < 5; i++) |
| 1917 |
gpt->irqs[i] = irqs[i]; |
| 1918 |
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); |
| 1919 |
ppc4xx_gpt_reset(gpt); |
| 1920 |
#ifdef DEBUG_GPT
|
| 1921 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
| 1922 |
#endif
|
| 1923 |
ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
|
| 1924 |
gpt_read, gpt_write, gpt); |
| 1925 |
qemu_register_reset(ppc4xx_gpt_reset, gpt); |
| 1926 |
} |
| 1927 |
} |
| 1928 |
|
| 1929 |
/*****************************************************************************/
|
| 1930 |
/* MAL */
|
| 1931 |
enum {
|
| 1932 |
MAL0_CFG = 0x180,
|
| 1933 |
MAL0_ESR = 0x181,
|
| 1934 |
MAL0_IER = 0x182,
|
| 1935 |
MAL0_TXCASR = 0x184,
|
| 1936 |
MAL0_TXCARR = 0x185,
|
| 1937 |
MAL0_TXEOBISR = 0x186,
|
| 1938 |
MAL0_TXDEIR = 0x187,
|
| 1939 |
MAL0_RXCASR = 0x190,
|
| 1940 |
MAL0_RXCARR = 0x191,
|
| 1941 |
MAL0_RXEOBISR = 0x192,
|
| 1942 |
MAL0_RXDEIR = 0x193,
|
| 1943 |
MAL0_TXCTP0R = 0x1A0,
|
| 1944 |
MAL0_TXCTP1R = 0x1A1,
|
| 1945 |
MAL0_TXCTP2R = 0x1A2,
|
| 1946 |
MAL0_TXCTP3R = 0x1A3,
|
| 1947 |
MAL0_RXCTP0R = 0x1C0,
|
| 1948 |
MAL0_RXCTP1R = 0x1C1,
|
| 1949 |
MAL0_RCBS0 = 0x1E0,
|
| 1950 |
MAL0_RCBS1 = 0x1E1,
|
| 1951 |
}; |
| 1952 |
|
| 1953 |
typedef struct ppc40x_mal_t ppc40x_mal_t; |
| 1954 |
struct ppc40x_mal_t {
|
| 1955 |
qemu_irq irqs[4];
|
| 1956 |
uint32_t cfg; |
| 1957 |
uint32_t esr; |
| 1958 |
uint32_t ier; |
| 1959 |
uint32_t txcasr; |
| 1960 |
uint32_t txcarr; |
| 1961 |
uint32_t txeobisr; |
| 1962 |
uint32_t txdeir; |
| 1963 |
uint32_t rxcasr; |
| 1964 |
uint32_t rxcarr; |
| 1965 |
uint32_t rxeobisr; |
| 1966 |
uint32_t rxdeir; |
| 1967 |
uint32_t txctpr[4];
|
| 1968 |
uint32_t rxctpr[2];
|
| 1969 |
uint32_t rcbs[2];
|
| 1970 |
}; |
| 1971 |
|
| 1972 |
static void ppc40x_mal_reset (void *opaque); |
| 1973 |
|
| 1974 |
static target_ulong dcr_read_mal (void *opaque, int dcrn) |
| 1975 |
{
|
| 1976 |
ppc40x_mal_t *mal; |
| 1977 |
target_ulong ret; |
| 1978 |
|
| 1979 |
mal = opaque; |
| 1980 |
switch (dcrn) {
|
| 1981 |
case MAL0_CFG:
|
| 1982 |
ret = mal->cfg; |
| 1983 |
break;
|
| 1984 |
case MAL0_ESR:
|
| 1985 |
ret = mal->esr; |
| 1986 |
break;
|
| 1987 |
case MAL0_IER:
|
| 1988 |
ret = mal->ier; |
| 1989 |
break;
|
| 1990 |
case MAL0_TXCASR:
|
| 1991 |
ret = mal->txcasr; |
| 1992 |
break;
|
| 1993 |
case MAL0_TXCARR:
|
| 1994 |
ret = mal->txcarr; |
| 1995 |
break;
|
| 1996 |
case MAL0_TXEOBISR:
|
| 1997 |
ret = mal->txeobisr; |
| 1998 |
break;
|
| 1999 |
case MAL0_TXDEIR:
|
| 2000 |
ret = mal->txdeir; |
| 2001 |
break;
|
| 2002 |
case MAL0_RXCASR:
|
| 2003 |
ret = mal->rxcasr; |
| 2004 |
break;
|
| 2005 |
case MAL0_RXCARR:
|
| 2006 |
ret = mal->rxcarr; |
| 2007 |
break;
|
| 2008 |
case MAL0_RXEOBISR:
|
| 2009 |
ret = mal->rxeobisr; |
| 2010 |
break;
|
| 2011 |
case MAL0_RXDEIR:
|
| 2012 |
ret = mal->rxdeir; |
| 2013 |
break;
|
| 2014 |
case MAL0_TXCTP0R:
|
| 2015 |
ret = mal->txctpr[0];
|
| 2016 |
break;
|
| 2017 |
case MAL0_TXCTP1R:
|
| 2018 |
ret = mal->txctpr[1];
|
| 2019 |
break;
|
| 2020 |
case MAL0_TXCTP2R:
|
| 2021 |
ret = mal->txctpr[2];
|
| 2022 |
break;
|
| 2023 |
case MAL0_TXCTP3R:
|
| 2024 |
ret = mal->txctpr[3];
|
| 2025 |
break;
|
| 2026 |
case MAL0_RXCTP0R:
|
| 2027 |
ret = mal->rxctpr[0];
|
| 2028 |
break;
|
| 2029 |
case MAL0_RXCTP1R:
|
| 2030 |
ret = mal->rxctpr[1];
|
| 2031 |
break;
|
| 2032 |
case MAL0_RCBS0:
|
| 2033 |
ret = mal->rcbs[0];
|
| 2034 |
break;
|
| 2035 |
case MAL0_RCBS1:
|
| 2036 |
ret = mal->rcbs[1];
|
| 2037 |
break;
|
| 2038 |
default:
|
| 2039 |
ret = 0;
|
| 2040 |
break;
|
| 2041 |
} |
| 2042 |
|
| 2043 |
return ret;
|
| 2044 |
} |
| 2045 |
|
| 2046 |
static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) |
| 2047 |
{
|
| 2048 |
ppc40x_mal_t *mal; |
| 2049 |
int idx;
|
| 2050 |
|
| 2051 |
mal = opaque; |
| 2052 |
switch (dcrn) {
|
| 2053 |
case MAL0_CFG:
|
| 2054 |
if (val & 0x80000000) |
| 2055 |
ppc40x_mal_reset(mal); |
| 2056 |
mal->cfg = val & 0x00FFC087;
|
| 2057 |
break;
|
| 2058 |
case MAL0_ESR:
|
| 2059 |
/* Read/clear */
|
| 2060 |
mal->esr &= ~val; |
| 2061 |
break;
|
| 2062 |
case MAL0_IER:
|
| 2063 |
mal->ier = val & 0x0000001F;
|
| 2064 |
break;
|
| 2065 |
case MAL0_TXCASR:
|
| 2066 |
mal->txcasr = val & 0xF0000000;
|
| 2067 |
break;
|
| 2068 |
case MAL0_TXCARR:
|
| 2069 |
mal->txcarr = val & 0xF0000000;
|
| 2070 |
break;
|
| 2071 |
case MAL0_TXEOBISR:
|
| 2072 |
/* Read/clear */
|
| 2073 |
mal->txeobisr &= ~val; |
| 2074 |
break;
|
| 2075 |
case MAL0_TXDEIR:
|
| 2076 |
/* Read/clear */
|
| 2077 |
mal->txdeir &= ~val; |
| 2078 |
break;
|
| 2079 |
case MAL0_RXCASR:
|
| 2080 |
mal->rxcasr = val & 0xC0000000;
|
| 2081 |
break;
|
| 2082 |
case MAL0_RXCARR:
|
| 2083 |
mal->rxcarr = val & 0xC0000000;
|
| 2084 |
break;
|
| 2085 |
case MAL0_RXEOBISR:
|
| 2086 |
/* Read/clear */
|
| 2087 |
mal->rxeobisr &= ~val; |
| 2088 |
break;
|
| 2089 |
case MAL0_RXDEIR:
|
| 2090 |
/* Read/clear */
|
| 2091 |
mal->rxdeir &= ~val; |
| 2092 |
break;
|
| 2093 |
case MAL0_TXCTP0R:
|
| 2094 |
idx = 0;
|
| 2095 |
goto update_tx_ptr;
|
| 2096 |
case MAL0_TXCTP1R:
|
| 2097 |
idx = 1;
|
| 2098 |
goto update_tx_ptr;
|
| 2099 |
case MAL0_TXCTP2R:
|
| 2100 |
idx = 2;
|
| 2101 |
goto update_tx_ptr;
|
| 2102 |
case MAL0_TXCTP3R:
|
| 2103 |
idx = 3;
|
| 2104 |
update_tx_ptr:
|
| 2105 |
mal->txctpr[idx] = val; |
| 2106 |
break;
|
| 2107 |
case MAL0_RXCTP0R:
|
| 2108 |
idx = 0;
|
| 2109 |
goto update_rx_ptr;
|
| 2110 |
case MAL0_RXCTP1R:
|
| 2111 |
idx = 1;
|
| 2112 |
update_rx_ptr:
|
| 2113 |
mal->rxctpr[idx] = val; |
| 2114 |
break;
|
| 2115 |
case MAL0_RCBS0:
|
| 2116 |
idx = 0;
|
| 2117 |
goto update_rx_size;
|
| 2118 |
case MAL0_RCBS1:
|
| 2119 |
idx = 1;
|
| 2120 |
update_rx_size:
|
| 2121 |
mal->rcbs[idx] = val & 0x000000FF;
|
| 2122 |
break;
|
| 2123 |
} |
| 2124 |
} |
| 2125 |
|
| 2126 |
static void ppc40x_mal_reset (void *opaque) |
| 2127 |
{
|
| 2128 |
ppc40x_mal_t *mal; |
| 2129 |
|
| 2130 |
mal = opaque; |
| 2131 |
mal->cfg = 0x0007C000;
|
| 2132 |
mal->esr = 0x00000000;
|
| 2133 |
mal->ier = 0x00000000;
|
| 2134 |
mal->rxcasr = 0x00000000;
|
| 2135 |
mal->rxdeir = 0x00000000;
|
| 2136 |
mal->rxeobisr = 0x00000000;
|
| 2137 |
mal->txcasr = 0x00000000;
|
| 2138 |
mal->txdeir = 0x00000000;
|
| 2139 |
mal->txeobisr = 0x00000000;
|
| 2140 |
} |
| 2141 |
|
| 2142 |
void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]) |
| 2143 |
{
|
| 2144 |
ppc40x_mal_t *mal; |
| 2145 |
int i;
|
| 2146 |
|
| 2147 |
mal = qemu_mallocz(sizeof(ppc40x_mal_t));
|
| 2148 |
if (mal != NULL) { |
| 2149 |
for (i = 0; i < 4; i++) |
| 2150 |
mal->irqs[i] = irqs[i]; |
| 2151 |
ppc40x_mal_reset(mal); |
| 2152 |
qemu_register_reset(&ppc40x_mal_reset, mal); |
| 2153 |
ppc_dcr_register(env, MAL0_CFG, |
| 2154 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2155 |
ppc_dcr_register(env, MAL0_ESR, |
| 2156 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2157 |
ppc_dcr_register(env, MAL0_IER, |
| 2158 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2159 |
ppc_dcr_register(env, MAL0_TXCASR, |
| 2160 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2161 |
ppc_dcr_register(env, MAL0_TXCARR, |
| 2162 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2163 |
ppc_dcr_register(env, MAL0_TXEOBISR, |
| 2164 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2165 |
ppc_dcr_register(env, MAL0_TXDEIR, |
| 2166 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2167 |
ppc_dcr_register(env, MAL0_RXCASR, |
| 2168 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2169 |
ppc_dcr_register(env, MAL0_RXCARR, |
| 2170 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2171 |
ppc_dcr_register(env, MAL0_RXEOBISR, |
| 2172 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2173 |
ppc_dcr_register(env, MAL0_RXDEIR, |
| 2174 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2175 |
ppc_dcr_register(env, MAL0_TXCTP0R, |
| 2176 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2177 |
ppc_dcr_register(env, MAL0_TXCTP1R, |
| 2178 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2179 |
ppc_dcr_register(env, MAL0_TXCTP2R, |
| 2180 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2181 |
ppc_dcr_register(env, MAL0_TXCTP3R, |
| 2182 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2183 |
ppc_dcr_register(env, MAL0_RXCTP0R, |
| 2184 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2185 |
ppc_dcr_register(env, MAL0_RXCTP1R, |
| 2186 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2187 |
ppc_dcr_register(env, MAL0_RCBS0, |
| 2188 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2189 |
ppc_dcr_register(env, MAL0_RCBS1, |
| 2190 |
mal, &dcr_read_mal, &dcr_write_mal); |
| 2191 |
} |
| 2192 |
} |
| 2193 |
|
| 2194 |
/*****************************************************************************/
|
| 2195 |
/* SPR */
|
| 2196 |
void ppc40x_core_reset (CPUState *env)
|
| 2197 |
{
|
| 2198 |
target_ulong dbsr; |
| 2199 |
|
| 2200 |
printf("Reset PowerPC core\n");
|
| 2201 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
| 2202 |
/* XXX: TOFIX */
|
| 2203 |
#if 0
|
| 2204 |
cpu_ppc_reset(env);
|
| 2205 |
#else
|
| 2206 |
qemu_system_reset_request(); |
| 2207 |
#endif
|
| 2208 |
dbsr = env->spr[SPR_40x_DBSR]; |
| 2209 |
dbsr &= ~0x00000300;
|
| 2210 |
dbsr |= 0x00000100;
|
| 2211 |
env->spr[SPR_40x_DBSR] = dbsr; |
| 2212 |
} |
| 2213 |
|
| 2214 |
void ppc40x_chip_reset (CPUState *env)
|
| 2215 |
{
|
| 2216 |
target_ulong dbsr; |
| 2217 |
|
| 2218 |
printf("Reset PowerPC chip\n");
|
| 2219 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
| 2220 |
/* XXX: TOFIX */
|
| 2221 |
#if 0
|
| 2222 |
cpu_ppc_reset(env);
|
| 2223 |
#else
|
| 2224 |
qemu_system_reset_request(); |
| 2225 |
#endif
|
| 2226 |
/* XXX: TODO reset all internal peripherals */
|
| 2227 |
dbsr = env->spr[SPR_40x_DBSR]; |
| 2228 |
dbsr &= ~0x00000300;
|
| 2229 |
dbsr |= 0x00000200;
|
| 2230 |
env->spr[SPR_40x_DBSR] = dbsr; |
| 2231 |
} |
| 2232 |
|
| 2233 |
void ppc40x_system_reset (CPUState *env)
|
| 2234 |
{
|
| 2235 |
printf("Reset PowerPC system\n");
|
| 2236 |
qemu_system_reset_request(); |
| 2237 |
} |
| 2238 |
|
| 2239 |
void store_40x_dbcr0 (CPUState *env, uint32_t val)
|
| 2240 |
{
|
| 2241 |
switch ((val >> 28) & 0x3) { |
| 2242 |
case 0x0: |
| 2243 |
/* No action */
|
| 2244 |
break;
|
| 2245 |
case 0x1: |
| 2246 |
/* Core reset */
|
| 2247 |
ppc40x_core_reset(env); |
| 2248 |
break;
|
| 2249 |
case 0x2: |
| 2250 |
/* Chip reset */
|
| 2251 |
ppc40x_chip_reset(env); |
| 2252 |
break;
|
| 2253 |
case 0x3: |
| 2254 |
/* System reset */
|
| 2255 |
ppc40x_system_reset(env); |
| 2256 |
break;
|
| 2257 |
} |
| 2258 |
} |
| 2259 |
|
| 2260 |
/*****************************************************************************/
|
| 2261 |
/* PowerPC 405CR */
|
| 2262 |
enum {
|
| 2263 |
PPC405CR_CPC0_PLLMR = 0x0B0,
|
| 2264 |
PPC405CR_CPC0_CR0 = 0x0B1,
|
| 2265 |
PPC405CR_CPC0_CR1 = 0x0B2,
|
| 2266 |
PPC405CR_CPC0_PSR = 0x0B4,
|
| 2267 |
PPC405CR_CPC0_JTAGID = 0x0B5,
|
| 2268 |
PPC405CR_CPC0_ER = 0x0B9,
|
| 2269 |
PPC405CR_CPC0_FR = 0x0BA,
|
| 2270 |
PPC405CR_CPC0_SR = 0x0BB,
|
| 2271 |
}; |
| 2272 |
|
| 2273 |
enum {
|
| 2274 |
PPC405CR_CPU_CLK = 0,
|
| 2275 |
PPC405CR_TMR_CLK = 1,
|
| 2276 |
PPC405CR_PLB_CLK = 2,
|
| 2277 |
PPC405CR_SDRAM_CLK = 3,
|
| 2278 |
PPC405CR_OPB_CLK = 4,
|
| 2279 |
PPC405CR_EXT_CLK = 5,
|
| 2280 |
PPC405CR_UART_CLK = 6,
|
| 2281 |
PPC405CR_CLK_NB = 7,
|
| 2282 |
}; |
| 2283 |
|
| 2284 |
typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; |
| 2285 |
struct ppc405cr_cpc_t {
|
| 2286 |
clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
| 2287 |
uint32_t sysclk; |
| 2288 |
uint32_t psr; |
| 2289 |
uint32_t cr0; |
| 2290 |
uint32_t cr1; |
| 2291 |
uint32_t jtagid; |
| 2292 |
uint32_t pllmr; |
| 2293 |
uint32_t er; |
| 2294 |
uint32_t fr; |
| 2295 |
}; |
| 2296 |
|
| 2297 |
static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) |
| 2298 |
{
|
| 2299 |
uint64_t VCO_out, PLL_out; |
| 2300 |
uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; |
| 2301 |
int M, D0, D1, D2;
|
| 2302 |
|
| 2303 |
D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ |
| 2304 |
if (cpc->pllmr & 0x80000000) { |
| 2305 |
D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ |
| 2306 |
D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ |
| 2307 |
M = D0 * D1 * D2; |
| 2308 |
VCO_out = cpc->sysclk * M; |
| 2309 |
if (VCO_out < 400000000 || VCO_out > 800000000) { |
| 2310 |
/* PLL cannot lock */
|
| 2311 |
cpc->pllmr &= ~0x80000000;
|
| 2312 |
goto bypass_pll;
|
| 2313 |
} |
| 2314 |
PLL_out = VCO_out / D2; |
| 2315 |
} else {
|
| 2316 |
/* Bypass PLL */
|
| 2317 |
bypass_pll:
|
| 2318 |
M = D0; |
| 2319 |
PLL_out = cpc->sysclk * M; |
| 2320 |
} |
| 2321 |
CPU_clk = PLL_out; |
| 2322 |
if (cpc->cr1 & 0x00800000) |
| 2323 |
TMR_clk = cpc->sysclk; /* Should have a separate clock */
|
| 2324 |
else
|
| 2325 |
TMR_clk = CPU_clk; |
| 2326 |
PLB_clk = CPU_clk / D0; |
| 2327 |
SDRAM_clk = PLB_clk; |
| 2328 |
D0 = ((cpc->pllmr >> 10) & 0x3) + 1; |
| 2329 |
OPB_clk = PLB_clk / D0; |
| 2330 |
D0 = ((cpc->pllmr >> 24) & 0x3) + 2; |
| 2331 |
EXT_clk = PLB_clk / D0; |
| 2332 |
D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; |
| 2333 |
UART_clk = CPU_clk / D0; |
| 2334 |
/* Setup CPU clocks */
|
| 2335 |
clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); |
| 2336 |
/* Setup time-base clock */
|
| 2337 |
clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); |
| 2338 |
/* Setup PLB clock */
|
| 2339 |
clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); |
| 2340 |
/* Setup SDRAM clock */
|
| 2341 |
clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); |
| 2342 |
/* Setup OPB clock */
|
| 2343 |
clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); |
| 2344 |
/* Setup external clock */
|
| 2345 |
clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); |
| 2346 |
/* Setup UART clock */
|
| 2347 |
clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); |
| 2348 |
} |
| 2349 |
|
| 2350 |
static target_ulong dcr_read_crcpc (void *opaque, int dcrn) |
| 2351 |
{
|
| 2352 |
ppc405cr_cpc_t *cpc; |
| 2353 |
target_ulong ret; |
| 2354 |
|
| 2355 |
cpc = opaque; |
| 2356 |
switch (dcrn) {
|
| 2357 |
case PPC405CR_CPC0_PLLMR:
|
| 2358 |
ret = cpc->pllmr; |
| 2359 |
break;
|
| 2360 |
case PPC405CR_CPC0_CR0:
|
| 2361 |
ret = cpc->cr0; |
| 2362 |
break;
|
| 2363 |
case PPC405CR_CPC0_CR1:
|
| 2364 |
ret = cpc->cr1; |
| 2365 |
break;
|
| 2366 |
case PPC405CR_CPC0_PSR:
|
| 2367 |
ret = cpc->psr; |
| 2368 |
break;
|
| 2369 |
case PPC405CR_CPC0_JTAGID:
|
| 2370 |
ret = cpc->jtagid; |
| 2371 |
break;
|
| 2372 |
case PPC405CR_CPC0_ER:
|
| 2373 |
ret = cpc->er; |
| 2374 |
break;
|
| 2375 |
case PPC405CR_CPC0_FR:
|
| 2376 |
ret = cpc->fr; |
| 2377 |
break;
|
| 2378 |
case PPC405CR_CPC0_SR:
|
| 2379 |
ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
|
| 2380 |
break;
|
| 2381 |
default:
|
| 2382 |
/* Avoid gcc warning */
|
| 2383 |
ret = 0;
|
| 2384 |
break;
|
| 2385 |
} |
| 2386 |
|
| 2387 |
return ret;
|
| 2388 |
} |
| 2389 |
|
| 2390 |
static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) |
| 2391 |
{
|
| 2392 |
ppc405cr_cpc_t *cpc; |
| 2393 |
|
| 2394 |
cpc = opaque; |
| 2395 |
switch (dcrn) {
|
| 2396 |
case PPC405CR_CPC0_PLLMR:
|
| 2397 |
cpc->pllmr = val & 0xFFF77C3F;
|
| 2398 |
break;
|
| 2399 |
case PPC405CR_CPC0_CR0:
|
| 2400 |
cpc->cr0 = val & 0x0FFFFFFE;
|
| 2401 |
break;
|
| 2402 |
case PPC405CR_CPC0_CR1:
|
| 2403 |
cpc->cr1 = val & 0x00800000;
|
| 2404 |
break;
|
| 2405 |
case PPC405CR_CPC0_PSR:
|
| 2406 |
/* Read-only */
|
| 2407 |
break;
|
| 2408 |
case PPC405CR_CPC0_JTAGID:
|
| 2409 |
/* Read-only */
|
| 2410 |
break;
|
| 2411 |
case PPC405CR_CPC0_ER:
|
| 2412 |
cpc->er = val & 0xBFFC0000;
|
| 2413 |
break;
|
| 2414 |
case PPC405CR_CPC0_FR:
|
| 2415 |
cpc->fr = val & 0xBFFC0000;
|
| 2416 |
break;
|
| 2417 |
case PPC405CR_CPC0_SR:
|
| 2418 |
/* Read-only */
|
| 2419 |
break;
|
| 2420 |
} |
| 2421 |
} |
| 2422 |
|
| 2423 |
static void ppc405cr_cpc_reset (void *opaque) |
| 2424 |
{
|
| 2425 |
ppc405cr_cpc_t *cpc; |
| 2426 |
int D;
|
| 2427 |
|
| 2428 |
cpc = opaque; |
| 2429 |
/* Compute PLLMR value from PSR settings */
|
| 2430 |
cpc->pllmr = 0x80000000;
|
| 2431 |
/* PFWD */
|
| 2432 |
switch ((cpc->psr >> 30) & 3) { |
| 2433 |
case 0: |
| 2434 |
/* Bypass */
|
| 2435 |
cpc->pllmr &= ~0x80000000;
|
| 2436 |
break;
|
| 2437 |
case 1: |
| 2438 |
/* Divide by 3 */
|
| 2439 |
cpc->pllmr |= 5 << 16; |
| 2440 |
break;
|
| 2441 |
case 2: |
| 2442 |
/* Divide by 4 */
|
| 2443 |
cpc->pllmr |= 4 << 16; |
| 2444 |
break;
|
| 2445 |
case 3: |
| 2446 |
/* Divide by 6 */
|
| 2447 |
cpc->pllmr |= 2 << 16; |
| 2448 |
break;
|
| 2449 |
} |
| 2450 |
/* PFBD */
|
| 2451 |
D = (cpc->psr >> 28) & 3; |
| 2452 |
cpc->pllmr |= (D + 1) << 20; |
| 2453 |
/* PT */
|
| 2454 |
D = (cpc->psr >> 25) & 7; |
| 2455 |
switch (D) {
|
| 2456 |
case 0x2: |
| 2457 |
cpc->pllmr |= 0x13;
|
| 2458 |
break;
|
| 2459 |
case 0x4: |
| 2460 |
cpc->pllmr |= 0x15;
|
| 2461 |
break;
|
| 2462 |
case 0x5: |
| 2463 |
cpc->pllmr |= 0x16;
|
| 2464 |
break;
|
| 2465 |
default:
|
| 2466 |
break;
|
| 2467 |
} |
| 2468 |
/* PDC */
|
| 2469 |
D = (cpc->psr >> 23) & 3; |
| 2470 |
cpc->pllmr |= D << 26;
|
| 2471 |
/* ODP */
|
| 2472 |
D = (cpc->psr >> 21) & 3; |
| 2473 |
cpc->pllmr |= D << 10;
|
| 2474 |
/* EBPD */
|
| 2475 |
D = (cpc->psr >> 17) & 3; |
| 2476 |
cpc->pllmr |= D << 24;
|
| 2477 |
cpc->cr0 = 0x0000003C;
|
| 2478 |
cpc->cr1 = 0x2B0D8800;
|
| 2479 |
cpc->er = 0x00000000;
|
| 2480 |
cpc->fr = 0x00000000;
|
| 2481 |
ppc405cr_clk_setup(cpc); |
| 2482 |
} |
| 2483 |
|
| 2484 |
static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) |
| 2485 |
{
|
| 2486 |
int D;
|
| 2487 |
|
| 2488 |
/* XXX: this should be read from IO pins */
|
| 2489 |
cpc->psr = 0x00000000; /* 8 bits ROM */ |
| 2490 |
/* PFWD */
|
| 2491 |
D = 0x2; /* Divide by 4 */ |
| 2492 |
cpc->psr |= D << 30;
|
| 2493 |
/* PFBD */
|
| 2494 |
D = 0x1; /* Divide by 2 */ |
| 2495 |
cpc->psr |= D << 28;
|
| 2496 |
/* PDC */
|
| 2497 |
D = 0x1; /* Divide by 2 */ |
| 2498 |
cpc->psr |= D << 23;
|
| 2499 |
/* PT */
|
| 2500 |
D = 0x5; /* M = 16 */ |
| 2501 |
cpc->psr |= D << 25;
|
| 2502 |
/* ODP */
|
| 2503 |
D = 0x1; /* Divide by 2 */ |
| 2504 |
cpc->psr |= D << 21;
|
| 2505 |
/* EBDP */
|
| 2506 |
D = 0x2; /* Divide by 4 */ |
| 2507 |
cpc->psr |= D << 17;
|
| 2508 |
} |
| 2509 |
|
| 2510 |
static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], |
| 2511 |
uint32_t sysclk) |
| 2512 |
{
|
| 2513 |
ppc405cr_cpc_t *cpc; |
| 2514 |
|
| 2515 |
cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
|
| 2516 |
if (cpc != NULL) { |
| 2517 |
memcpy(cpc->clk_setup, clk_setup, |
| 2518 |
PPC405CR_CLK_NB * sizeof(clk_setup_t));
|
| 2519 |
cpc->sysclk = sysclk; |
| 2520 |
cpc->jtagid = 0x42051049;
|
| 2521 |
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, |
| 2522 |
&dcr_read_crcpc, &dcr_write_crcpc); |
| 2523 |
ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, |
| 2524 |
&dcr_read_crcpc, &dcr_write_crcpc); |
| 2525 |
ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, |
| 2526 |
&dcr_read_crcpc, &dcr_write_crcpc); |
| 2527 |
ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, |
| 2528 |
&dcr_read_crcpc, &dcr_write_crcpc); |
| 2529 |
ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, |
| 2530 |
&dcr_read_crcpc, &dcr_write_crcpc); |
| 2531 |
ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, |
| 2532 |
&dcr_read_crcpc, &dcr_write_crcpc); |
| 2533 |
ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, |
| 2534 |
&dcr_read_crcpc, &dcr_write_crcpc); |
| 2535 |
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, |
| 2536 |
&dcr_read_crcpc, &dcr_write_crcpc); |
| 2537 |
ppc405cr_clk_init(cpc); |
| 2538 |
qemu_register_reset(ppc405cr_cpc_reset, cpc); |
| 2539 |
ppc405cr_cpc_reset(cpc); |
| 2540 |
} |
| 2541 |
} |
| 2542 |
|
| 2543 |
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
|
| 2544 |
target_phys_addr_t ram_sizes[4],
|
| 2545 |
uint32_t sysclk, qemu_irq **picp, |
| 2546 |
ram_addr_t *offsetp, int do_init)
|
| 2547 |
{
|
| 2548 |
clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
| 2549 |
qemu_irq dma_irqs[4];
|
| 2550 |
CPUState *env; |
| 2551 |
ppc4xx_mmio_t *mmio; |
| 2552 |
qemu_irq *pic, *irqs; |
| 2553 |
ram_addr_t offset; |
| 2554 |
int i;
|
| 2555 |
|
| 2556 |
memset(clk_setup, 0, sizeof(clk_setup)); |
| 2557 |
env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
| 2558 |
&clk_setup[PPC405CR_TMR_CLK], sysclk); |
| 2559 |
/* Memory mapped devices registers */
|
| 2560 |
mmio = ppc4xx_mmio_init(env, 0xEF600000);
|
| 2561 |
/* PLB arbitrer */
|
| 2562 |
ppc4xx_plb_init(env); |
| 2563 |
/* PLB to OPB bridge */
|
| 2564 |
ppc4xx_pob_init(env); |
| 2565 |
/* OBP arbitrer */
|
| 2566 |
ppc4xx_opba_init(env, mmio, 0x600);
|
| 2567 |
/* Universal interrupt controller */
|
| 2568 |
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
| 2569 |
irqs[PPCUIC_OUTPUT_INT] = |
| 2570 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
| 2571 |
irqs[PPCUIC_OUTPUT_CINT] = |
| 2572 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
| 2573 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
| 2574 |
*picp = pic; |
| 2575 |
/* SDRAM controller */
|
| 2576 |
ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); |
| 2577 |
offset = 0;
|
| 2578 |
for (i = 0; i < 4; i++) |
| 2579 |
offset += ram_sizes[i]; |
| 2580 |
/* External bus controller */
|
| 2581 |
ppc405_ebc_init(env); |
| 2582 |
/* DMA controller */
|
| 2583 |
dma_irqs[0] = pic[26]; |
| 2584 |
dma_irqs[1] = pic[25]; |
| 2585 |
dma_irqs[2] = pic[24]; |
| 2586 |
dma_irqs[3] = pic[23]; |
| 2587 |
ppc405_dma_init(env, dma_irqs); |
| 2588 |
/* Serial ports */
|
| 2589 |
if (serial_hds[0] != NULL) { |
| 2590 |
ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]); |
| 2591 |
} |
| 2592 |
if (serial_hds[1] != NULL) { |
| 2593 |
ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]); |
| 2594 |
} |
| 2595 |
/* IIC controller */
|
| 2596 |
ppc405_i2c_init(env, mmio, 0x500, pic[2]); |
| 2597 |
/* GPIO */
|
| 2598 |
ppc405_gpio_init(env, mmio, 0x700);
|
| 2599 |
/* CPU control */
|
| 2600 |
ppc405cr_cpc_init(env, clk_setup, sysclk); |
| 2601 |
*offsetp = offset; |
| 2602 |
|
| 2603 |
return env;
|
| 2604 |
} |
| 2605 |
|
| 2606 |
/*****************************************************************************/
|
| 2607 |
/* PowerPC 405EP */
|
| 2608 |
/* CPU control */
|
| 2609 |
enum {
|
| 2610 |
PPC405EP_CPC0_PLLMR0 = 0x0F0,
|
| 2611 |
PPC405EP_CPC0_BOOT = 0x0F1,
|
| 2612 |
PPC405EP_CPC0_EPCTL = 0x0F3,
|
| 2613 |
PPC405EP_CPC0_PLLMR1 = 0x0F4,
|
| 2614 |
PPC405EP_CPC0_UCR = 0x0F5,
|
| 2615 |
PPC405EP_CPC0_SRR = 0x0F6,
|
| 2616 |
PPC405EP_CPC0_JTAGID = 0x0F7,
|
| 2617 |
PPC405EP_CPC0_PCI = 0x0F9,
|
| 2618 |
#if 0
|
| 2619 |
PPC405EP_CPC0_ER = xxx,
|
| 2620 |
PPC405EP_CPC0_FR = xxx,
|
| 2621 |
PPC405EP_CPC0_SR = xxx,
|
| 2622 |
#endif
|
| 2623 |
}; |
| 2624 |
|
| 2625 |
enum {
|
| 2626 |
PPC405EP_CPU_CLK = 0,
|
| 2627 |
PPC405EP_PLB_CLK = 1,
|
| 2628 |
PPC405EP_OPB_CLK = 2,
|
| 2629 |
PPC405EP_EBC_CLK = 3,
|
| 2630 |
PPC405EP_MAL_CLK = 4,
|
| 2631 |
PPC405EP_PCI_CLK = 5,
|
| 2632 |
PPC405EP_UART0_CLK = 6,
|
| 2633 |
PPC405EP_UART1_CLK = 7,
|
| 2634 |
PPC405EP_CLK_NB = 8,
|
| 2635 |
}; |
| 2636 |
|
| 2637 |
typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; |
| 2638 |
struct ppc405ep_cpc_t {
|
| 2639 |
uint32_t sysclk; |
| 2640 |
clk_setup_t clk_setup[PPC405EP_CLK_NB]; |
| 2641 |
uint32_t boot; |
| 2642 |
uint32_t epctl; |
| 2643 |
uint32_t pllmr[2];
|
| 2644 |
uint32_t ucr; |
| 2645 |
uint32_t srr; |
| 2646 |
uint32_t jtagid; |
| 2647 |
uint32_t pci; |
| 2648 |
/* Clock and power management */
|
| 2649 |
uint32_t er; |
| 2650 |
uint32_t fr; |
| 2651 |
uint32_t sr; |
| 2652 |
}; |
| 2653 |
|
| 2654 |
static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) |
| 2655 |
{
|
| 2656 |
uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; |
| 2657 |
uint32_t UART0_clk, UART1_clk; |
| 2658 |
uint64_t VCO_out, PLL_out; |
| 2659 |
int M, D;
|
| 2660 |
|
| 2661 |
VCO_out = 0;
|
| 2662 |
if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { |
| 2663 |
M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ |
| 2664 |
#ifdef DEBUG_CLOCKS_LL
|
| 2665 |
printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); |
| 2666 |
#endif
|
| 2667 |
D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ |
| 2668 |
#ifdef DEBUG_CLOCKS_LL
|
| 2669 |
printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); |
| 2670 |
#endif
|
| 2671 |
VCO_out = cpc->sysclk * M * D; |
| 2672 |
if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { |
| 2673 |
/* Error - unlock the PLL */
|
| 2674 |
printf("VCO out of range %" PRIu64 "\n", VCO_out); |
| 2675 |
#if 0
|
| 2676 |
cpc->pllmr[1] &= ~0x80000000;
|
| 2677 |
goto pll_bypass;
|
| 2678 |
#endif
|
| 2679 |
} |
| 2680 |
PLL_out = VCO_out / D; |
| 2681 |
/* Pretend the PLL is locked */
|
| 2682 |
cpc->boot |= 0x00000001;
|
| 2683 |
} else {
|
| 2684 |
#if 0
|
| 2685 |
pll_bypass:
|
| 2686 |
#endif
|
| 2687 |
PLL_out = cpc->sysclk; |
| 2688 |
if (cpc->pllmr[1] & 0x40000000) { |
| 2689 |
/* Pretend the PLL is not locked */
|
| 2690 |
cpc->boot &= ~0x00000001;
|
| 2691 |
} |
| 2692 |
} |
| 2693 |
/* Now, compute all other clocks */
|
| 2694 |
D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ |
| 2695 |
#ifdef DEBUG_CLOCKS_LL
|
| 2696 |
printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); |
| 2697 |
#endif
|
| 2698 |
CPU_clk = PLL_out / D; |
| 2699 |
D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ |
| 2700 |
#ifdef DEBUG_CLOCKS_LL
|
| 2701 |
printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); |
| 2702 |
#endif
|
| 2703 |
PLB_clk = CPU_clk / D; |
| 2704 |
D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ |
| 2705 |
#ifdef DEBUG_CLOCKS_LL
|
| 2706 |
printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); |
| 2707 |
#endif
|
| 2708 |
OPB_clk = PLB_clk / D; |
| 2709 |
D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ |
| 2710 |
#ifdef DEBUG_CLOCKS_LL
|
| 2711 |
printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); |
| 2712 |
#endif
|
| 2713 |
EBC_clk = PLB_clk / D; |
| 2714 |
D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ |
| 2715 |
#ifdef DEBUG_CLOCKS_LL
|
| 2716 |
printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); |
| 2717 |
#endif
|
| 2718 |
MAL_clk = PLB_clk / D; |
| 2719 |
D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ |
| 2720 |
#ifdef DEBUG_CLOCKS_LL
|
| 2721 |
printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); |
| 2722 |
#endif
|
| 2723 |
PCI_clk = PLB_clk / D; |
| 2724 |
D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ |
| 2725 |
#ifdef DEBUG_CLOCKS_LL
|
| 2726 |
printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); |
| 2727 |
#endif
|
| 2728 |
UART0_clk = PLL_out / D; |
| 2729 |
D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ |
| 2730 |
#ifdef DEBUG_CLOCKS_LL
|
| 2731 |
printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); |
| 2732 |
#endif
|
| 2733 |
UART1_clk = PLL_out / D; |
| 2734 |
#ifdef DEBUG_CLOCKS
|
| 2735 |
printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 |
| 2736 |
" PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); |
| 2737 |
printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 |
| 2738 |
" MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 |
| 2739 |
" UART1 %" PRIu32 "\n", |
| 2740 |
CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, |
| 2741 |
UART0_clk, UART1_clk); |
| 2742 |
#endif
|
| 2743 |
/* Setup CPU clocks */
|
| 2744 |
clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); |
| 2745 |
/* Setup PLB clock */
|
| 2746 |
clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); |
| 2747 |
/* Setup OPB clock */
|
| 2748 |
clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); |
| 2749 |
/* Setup external clock */
|
| 2750 |
clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); |
| 2751 |
/* Setup MAL clock */
|
| 2752 |
clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); |
| 2753 |
/* Setup PCI clock */
|
| 2754 |
clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); |
| 2755 |
/* Setup UART0 clock */
|
| 2756 |
clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); |
| 2757 |
/* Setup UART1 clock */
|
| 2758 |
clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); |
| 2759 |
} |
| 2760 |
|
| 2761 |
static target_ulong dcr_read_epcpc (void *opaque, int dcrn) |
| 2762 |
{
|
| 2763 |
ppc405ep_cpc_t *cpc; |
| 2764 |
target_ulong ret; |
| 2765 |
|
| 2766 |
cpc = opaque; |
| 2767 |
switch (dcrn) {
|
| 2768 |
case PPC405EP_CPC0_BOOT:
|
| 2769 |
ret = cpc->boot; |
| 2770 |
break;
|
| 2771 |
case PPC405EP_CPC0_EPCTL:
|
| 2772 |
ret = cpc->epctl; |
| 2773 |
break;
|
| 2774 |
case PPC405EP_CPC0_PLLMR0:
|
| 2775 |
ret = cpc->pllmr[0];
|
| 2776 |
break;
|
| 2777 |
case PPC405EP_CPC0_PLLMR1:
|
| 2778 |
ret = cpc->pllmr[1];
|
| 2779 |
break;
|
| 2780 |
case PPC405EP_CPC0_UCR:
|
| 2781 |
ret = cpc->ucr; |
| 2782 |
break;
|
| 2783 |
case PPC405EP_CPC0_SRR:
|
| 2784 |
ret = cpc->srr; |
| 2785 |
break;
|
| 2786 |
case PPC405EP_CPC0_JTAGID:
|
| 2787 |
ret = cpc->jtagid; |
| 2788 |
break;
|
| 2789 |
case PPC405EP_CPC0_PCI:
|
| 2790 |
ret = cpc->pci; |
| 2791 |
break;
|
| 2792 |
default:
|
| 2793 |
/* Avoid gcc warning */
|
| 2794 |
ret = 0;
|
| 2795 |
break;
|
| 2796 |
} |
| 2797 |
|
| 2798 |
return ret;
|
| 2799 |
} |
| 2800 |
|
| 2801 |
static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) |
| 2802 |
{
|
| 2803 |
ppc405ep_cpc_t *cpc; |
| 2804 |
|
| 2805 |
cpc = opaque; |
| 2806 |
switch (dcrn) {
|
| 2807 |
case PPC405EP_CPC0_BOOT:
|
| 2808 |
/* Read-only register */
|
| 2809 |
break;
|
| 2810 |
case PPC405EP_CPC0_EPCTL:
|
| 2811 |
/* Don't care for now */
|
| 2812 |
cpc->epctl = val & 0xC00000F3;
|
| 2813 |
break;
|
| 2814 |
case PPC405EP_CPC0_PLLMR0:
|
| 2815 |
cpc->pllmr[0] = val & 0x00633333; |
| 2816 |
ppc405ep_compute_clocks(cpc); |
| 2817 |
break;
|
| 2818 |
case PPC405EP_CPC0_PLLMR1:
|
| 2819 |
cpc->pllmr[1] = val & 0xC0F73FFF; |
| 2820 |
ppc405ep_compute_clocks(cpc); |
| 2821 |
break;
|
| 2822 |
case PPC405EP_CPC0_UCR:
|
| 2823 |
/* UART control - don't care for now */
|
| 2824 |
cpc->ucr = val & 0x003F7F7F;
|
| 2825 |
break;
|
| 2826 |
case PPC405EP_CPC0_SRR:
|
| 2827 |
cpc->srr = val; |
| 2828 |
break;
|
| 2829 |
case PPC405EP_CPC0_JTAGID:
|
| 2830 |
/* Read-only */
|
| 2831 |
break;
|
| 2832 |
case PPC405EP_CPC0_PCI:
|
| 2833 |
cpc->pci = val; |
| 2834 |
break;
|
| 2835 |
} |
| 2836 |
} |
| 2837 |
|
| 2838 |
static void ppc405ep_cpc_reset (void *opaque) |
| 2839 |
{
|
| 2840 |
ppc405ep_cpc_t *cpc = opaque; |
| 2841 |
|
| 2842 |
cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ |
| 2843 |
cpc->epctl = 0x00000000;
|
| 2844 |
cpc->pllmr[0] = 0x00011010; |
| 2845 |
cpc->pllmr[1] = 0x40000000; |
| 2846 |
cpc->ucr = 0x00000000;
|
| 2847 |
cpc->srr = 0x00040000;
|
| 2848 |
cpc->pci = 0x00000000;
|
| 2849 |
cpc->er = 0x00000000;
|
| 2850 |
cpc->fr = 0x00000000;
|
| 2851 |
cpc->sr = 0x00000000;
|
| 2852 |
ppc405ep_compute_clocks(cpc); |
| 2853 |
} |
| 2854 |
|
| 2855 |
/* XXX: sysclk should be between 25 and 100 MHz */
|
| 2856 |
static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], |
| 2857 |
uint32_t sysclk) |
| 2858 |
{
|
| 2859 |
ppc405ep_cpc_t *cpc; |
| 2860 |
|
| 2861 |
cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
|
| 2862 |
if (cpc != NULL) { |
| 2863 |
memcpy(cpc->clk_setup, clk_setup, |
| 2864 |
PPC405EP_CLK_NB * sizeof(clk_setup_t));
|
| 2865 |
cpc->jtagid = 0x20267049;
|
| 2866 |
cpc->sysclk = sysclk; |
| 2867 |
ppc405ep_cpc_reset(cpc); |
| 2868 |
qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
| 2869 |
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
| 2870 |
&dcr_read_epcpc, &dcr_write_epcpc); |
| 2871 |
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, |
| 2872 |
&dcr_read_epcpc, &dcr_write_epcpc); |
| 2873 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, |
| 2874 |
&dcr_read_epcpc, &dcr_write_epcpc); |
| 2875 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, |
| 2876 |
&dcr_read_epcpc, &dcr_write_epcpc); |
| 2877 |
ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, |
| 2878 |
&dcr_read_epcpc, &dcr_write_epcpc); |
| 2879 |
ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, |
| 2880 |
&dcr_read_epcpc, &dcr_write_epcpc); |
| 2881 |
ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, |
| 2882 |
&dcr_read_epcpc, &dcr_write_epcpc); |
| 2883 |
ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, |
| 2884 |
&dcr_read_epcpc, &dcr_write_epcpc); |
| 2885 |
#if 0
|
| 2886 |
ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
|
| 2887 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
| 2888 |
ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
|
| 2889 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
| 2890 |
ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
|
| 2891 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
| 2892 |
#endif
|
| 2893 |
} |
| 2894 |
} |
| 2895 |
|
| 2896 |
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
|
| 2897 |
target_phys_addr_t ram_sizes[2],
|
| 2898 |
uint32_t sysclk, qemu_irq **picp, |
| 2899 |
ram_addr_t *offsetp, int do_init)
|
| 2900 |
{
|
| 2901 |
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
| 2902 |
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
| 2903 |
CPUState *env; |
| 2904 |
ppc4xx_mmio_t *mmio; |
| 2905 |
qemu_irq *pic, *irqs; |
| 2906 |
ram_addr_t offset; |
| 2907 |
int i;
|
| 2908 |
|
| 2909 |
memset(clk_setup, 0, sizeof(clk_setup)); |
| 2910 |
/* init CPUs */
|
| 2911 |
env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
|
| 2912 |
&tlb_clk_setup, sysclk); |
| 2913 |
clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; |
| 2914 |
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; |
| 2915 |
/* Internal devices init */
|
| 2916 |
/* Memory mapped devices registers */
|
| 2917 |
mmio = ppc4xx_mmio_init(env, 0xEF600000);
|
| 2918 |
/* PLB arbitrer */
|
| 2919 |
ppc4xx_plb_init(env); |
| 2920 |
/* PLB to OPB bridge */
|
| 2921 |
ppc4xx_pob_init(env); |
| 2922 |
/* OBP arbitrer */
|
| 2923 |
ppc4xx_opba_init(env, mmio, 0x600);
|
| 2924 |
/* Universal interrupt controller */
|
| 2925 |
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
| 2926 |
irqs[PPCUIC_OUTPUT_INT] = |
| 2927 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
| 2928 |
irqs[PPCUIC_OUTPUT_CINT] = |
| 2929 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
| 2930 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
| 2931 |
*picp = pic; |
| 2932 |
/* SDRAM controller */
|
| 2933 |
/* XXX 405EP has no ECC interrupt */
|
| 2934 |
ppc405_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); |
| 2935 |
offset = 0;
|
| 2936 |
for (i = 0; i < 2; i++) |
| 2937 |
offset += ram_sizes[i]; |
| 2938 |
/* External bus controller */
|
| 2939 |
ppc405_ebc_init(env); |
| 2940 |
/* DMA controller */
|
| 2941 |
dma_irqs[0] = pic[5]; |
| 2942 |
dma_irqs[1] = pic[6]; |
| 2943 |
dma_irqs[2] = pic[7]; |
| 2944 |
dma_irqs[3] = pic[8]; |
| 2945 |
ppc405_dma_init(env, dma_irqs); |
| 2946 |
/* IIC controller */
|
| 2947 |
ppc405_i2c_init(env, mmio, 0x500, pic[2]); |
| 2948 |
/* GPIO */
|
| 2949 |
ppc405_gpio_init(env, mmio, 0x700);
|
| 2950 |
/* Serial ports */
|
| 2951 |
if (serial_hds[0] != NULL) { |
| 2952 |
ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]); |
| 2953 |
} |
| 2954 |
if (serial_hds[1] != NULL) { |
| 2955 |
ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]); |
| 2956 |
} |
| 2957 |
/* OCM */
|
| 2958 |
ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]); |
| 2959 |
offset += 4096;
|
| 2960 |
/* GPT */
|
| 2961 |
gpt_irqs[0] = pic[19]; |
| 2962 |
gpt_irqs[1] = pic[20]; |
| 2963 |
gpt_irqs[2] = pic[21]; |
| 2964 |
gpt_irqs[3] = pic[22]; |
| 2965 |
gpt_irqs[4] = pic[23]; |
| 2966 |
ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
|
| 2967 |
/* PCI */
|
| 2968 |
/* Uses pic[3], pic[16], pic[18] */
|
| 2969 |
/* MAL */
|
| 2970 |
mal_irqs[0] = pic[11]; |
| 2971 |
mal_irqs[1] = pic[12]; |
| 2972 |
mal_irqs[2] = pic[13]; |
| 2973 |
mal_irqs[3] = pic[14]; |
| 2974 |
ppc405_mal_init(env, mal_irqs); |
| 2975 |
/* Ethernet */
|
| 2976 |
/* Uses pic[9], pic[15], pic[17] */
|
| 2977 |
/* CPU control */
|
| 2978 |
ppc405ep_cpc_init(env, clk_setup, sysclk); |
| 2979 |
*offsetp = offset; |
| 2980 |
|
| 2981 |
return env;
|
| 2982 |
} |