root / hw / omap1.c @ e94bbefe
History | View | Annotate | Download (122.3 kB)
1 | c3d2689d | balrog | /*
|
---|---|---|---|
2 | c3d2689d | balrog | * TI OMAP processors emulation.
|
3 | c3d2689d | balrog | *
|
4 | b4e3104b | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
|
5 | c3d2689d | balrog | *
|
6 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
|
7 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
|
8 | c3d2689d | balrog | * published by the Free Software Foundation; either version 2 of
|
9 | c3d2689d | balrog | * the License, or (at your option) any later version.
|
10 | c3d2689d | balrog | *
|
11 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
|
12 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
14 | c3d2689d | balrog | * GNU General Public License for more details.
|
15 | c3d2689d | balrog | *
|
16 | c3d2689d | balrog | * You should have received a copy of the GNU General Public License
|
17 | c3d2689d | balrog | * along with this program; if not, write to the Free Software
|
18 | c3d2689d | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
19 | c3d2689d | balrog | * MA 02111-1307 USA
|
20 | c3d2689d | balrog | */
|
21 | 87ecb68b | pbrook | #include "hw.h" |
22 | 87ecb68b | pbrook | #include "arm-misc.h" |
23 | 87ecb68b | pbrook | #include "omap.h" |
24 | 87ecb68b | pbrook | #include "sysemu.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | /* We use pc-style serial ports. */
|
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | c3d2689d | balrog | |
29 | c3d2689d | balrog | /* Should signal the TCMI */
|
30 | 66450b15 | balrog | uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
|
31 | 66450b15 | balrog | { |
32 | 02645926 | balrog | uint8_t ret; |
33 | 02645926 | balrog | |
34 | 66450b15 | balrog | OMAP_8B_REG(addr); |
35 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 1); |
36 | 02645926 | balrog | return ret;
|
37 | 66450b15 | balrog | } |
38 | 66450b15 | balrog | |
39 | 66450b15 | balrog | void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
40 | 66450b15 | balrog | uint32_t value) |
41 | 66450b15 | balrog | { |
42 | b854bc19 | balrog | uint8_t val8 = value; |
43 | b854bc19 | balrog | |
44 | 66450b15 | balrog | OMAP_8B_REG(addr); |
45 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &val8, 1); |
46 | 66450b15 | balrog | } |
47 | 66450b15 | balrog | |
48 | b30bb3a2 | balrog | uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
|
49 | c3d2689d | balrog | { |
50 | b854bc19 | balrog | uint16_t ret; |
51 | b854bc19 | balrog | |
52 | c3d2689d | balrog | OMAP_16B_REG(addr); |
53 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 2); |
54 | b854bc19 | balrog | return ret;
|
55 | c3d2689d | balrog | } |
56 | c3d2689d | balrog | |
57 | b30bb3a2 | balrog | void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
58 | c3d2689d | balrog | uint32_t value) |
59 | c3d2689d | balrog | { |
60 | b854bc19 | balrog | uint16_t val16 = value; |
61 | b854bc19 | balrog | |
62 | c3d2689d | balrog | OMAP_16B_REG(addr); |
63 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &val16, 2); |
64 | c3d2689d | balrog | } |
65 | c3d2689d | balrog | |
66 | b30bb3a2 | balrog | uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
|
67 | c3d2689d | balrog | { |
68 | b854bc19 | balrog | uint32_t ret; |
69 | b854bc19 | balrog | |
70 | c3d2689d | balrog | OMAP_32B_REG(addr); |
71 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 4); |
72 | b854bc19 | balrog | return ret;
|
73 | c3d2689d | balrog | } |
74 | c3d2689d | balrog | |
75 | b30bb3a2 | balrog | void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
76 | c3d2689d | balrog | uint32_t value) |
77 | c3d2689d | balrog | { |
78 | c3d2689d | balrog | OMAP_32B_REG(addr); |
79 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &value, 4); |
80 | c3d2689d | balrog | } |
81 | c3d2689d | balrog | |
82 | c3d2689d | balrog | /* Interrupt Handlers */
|
83 | 106627d0 | balrog | struct omap_intr_handler_bank_s {
|
84 | c3d2689d | balrog | uint32_t irqs; |
85 | 106627d0 | balrog | uint32_t inputs; |
86 | c3d2689d | balrog | uint32_t mask; |
87 | c3d2689d | balrog | uint32_t fiq; |
88 | 106627d0 | balrog | uint32_t sens_edge; |
89 | 106627d0 | balrog | unsigned char priority[32]; |
90 | c3d2689d | balrog | }; |
91 | c3d2689d | balrog | |
92 | 106627d0 | balrog | struct omap_intr_handler_s {
|
93 | 106627d0 | balrog | qemu_irq *pins; |
94 | 106627d0 | balrog | qemu_irq parent_intr[2];
|
95 | 106627d0 | balrog | target_phys_addr_t base; |
96 | 106627d0 | balrog | unsigned char nbanks; |
97 | c3d2689d | balrog | |
98 | 106627d0 | balrog | /* state */
|
99 | 106627d0 | balrog | uint32_t new_agr[2];
|
100 | 106627d0 | balrog | int sir_intr[2]; |
101 | 106627d0 | balrog | struct omap_intr_handler_bank_s banks[];
|
102 | 106627d0 | balrog | }; |
103 | c3d2689d | balrog | |
104 | 106627d0 | balrog | static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq) |
105 | 106627d0 | balrog | { |
106 | 106627d0 | balrog | int i, j, sir_intr, p_intr, p, f;
|
107 | 106627d0 | balrog | uint32_t level; |
108 | 106627d0 | balrog | sir_intr = 0;
|
109 | 106627d0 | balrog | p_intr = 255;
|
110 | 106627d0 | balrog | |
111 | 106627d0 | balrog | /* Find the interrupt line with the highest dynamic priority.
|
112 | 106627d0 | balrog | * Note: 0 denotes the hightest priority.
|
113 | 106627d0 | balrog | * If all interrupts have the same priority, the default order is IRQ_N,
|
114 | 106627d0 | balrog | * IRQ_N-1,...,IRQ_0. */
|
115 | 106627d0 | balrog | for (j = 0; j < s->nbanks; ++j) { |
116 | 106627d0 | balrog | level = s->banks[j].irqs & ~s->banks[j].mask & |
117 | 106627d0 | balrog | (is_fiq ? s->banks[j].fiq : ~s->banks[j].fiq); |
118 | 106627d0 | balrog | for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, |
119 | 106627d0 | balrog | level >>= f) { |
120 | 106627d0 | balrog | p = s->banks[j].priority[i]; |
121 | 106627d0 | balrog | if (p <= p_intr) {
|
122 | 106627d0 | balrog | p_intr = p; |
123 | 106627d0 | balrog | sir_intr = 32 * j + i;
|
124 | 106627d0 | balrog | } |
125 | 106627d0 | balrog | f = ffs(level >> 1);
|
126 | 106627d0 | balrog | } |
127 | cfa0b71d | balrog | } |
128 | 106627d0 | balrog | s->sir_intr[is_fiq] = sir_intr; |
129 | c3d2689d | balrog | } |
130 | c3d2689d | balrog | |
131 | 106627d0 | balrog | static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) |
132 | c3d2689d | balrog | { |
133 | 106627d0 | balrog | int i;
|
134 | 106627d0 | balrog | uint32_t has_intr = 0;
|
135 | c3d2689d | balrog | |
136 | 106627d0 | balrog | for (i = 0; i < s->nbanks; ++i) |
137 | 106627d0 | balrog | has_intr |= s->banks[i].irqs & ~s->banks[i].mask & |
138 | 106627d0 | balrog | (is_fiq ? s->banks[i].fiq : ~s->banks[i].fiq); |
139 | c3d2689d | balrog | |
140 | 106627d0 | balrog | if (s->new_agr[is_fiq] && has_intr) {
|
141 | 106627d0 | balrog | s->new_agr[is_fiq] = 0;
|
142 | 106627d0 | balrog | omap_inth_sir_update(s, is_fiq); |
143 | 106627d0 | balrog | qemu_set_irq(s->parent_intr[is_fiq], 1);
|
144 | c3d2689d | balrog | } |
145 | c3d2689d | balrog | } |
146 | c3d2689d | balrog | |
147 | c3d2689d | balrog | #define INT_FALLING_EDGE 0 |
148 | c3d2689d | balrog | #define INT_LOW_LEVEL 1 |
149 | c3d2689d | balrog | |
150 | c3d2689d | balrog | static void omap_set_intr(void *opaque, int irq, int req) |
151 | c3d2689d | balrog | { |
152 | c3d2689d | balrog | struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
153 | c3d2689d | balrog | uint32_t rise; |
154 | c3d2689d | balrog | |
155 | 106627d0 | balrog | struct omap_intr_handler_bank_s *bank = &ih->banks[irq >> 5]; |
156 | 106627d0 | balrog | int n = irq & 31; |
157 | 106627d0 | balrog | |
158 | c3d2689d | balrog | if (req) {
|
159 | 106627d0 | balrog | rise = ~bank->irqs & (1 << n);
|
160 | 106627d0 | balrog | if (~bank->sens_edge & (1 << n)) |
161 | 106627d0 | balrog | rise &= ~bank->inputs & (1 << n);
|
162 | 106627d0 | balrog | |
163 | 106627d0 | balrog | bank->inputs |= (1 << n);
|
164 | 106627d0 | balrog | if (rise) {
|
165 | 106627d0 | balrog | bank->irqs |= rise; |
166 | 106627d0 | balrog | omap_inth_update(ih, 0);
|
167 | 106627d0 | balrog | omap_inth_update(ih, 1);
|
168 | 106627d0 | balrog | } |
169 | c3d2689d | balrog | } else {
|
170 | 106627d0 | balrog | rise = bank->sens_edge & bank->irqs & (1 << n);
|
171 | 106627d0 | balrog | bank->irqs &= ~rise; |
172 | 106627d0 | balrog | bank->inputs &= ~(1 << n);
|
173 | c3d2689d | balrog | } |
174 | c3d2689d | balrog | } |
175 | c3d2689d | balrog | |
176 | c3d2689d | balrog | static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
177 | c3d2689d | balrog | { |
178 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
179 | c3d2689d | balrog | int i, offset = addr - s->base;
|
180 | 106627d0 | balrog | int bank_no = offset >> 8; |
181 | 106627d0 | balrog | int line_no;
|
182 | 106627d0 | balrog | struct omap_intr_handler_bank_s *bank = &s->banks[bank_no];
|
183 | 106627d0 | balrog | offset &= 0xff;
|
184 | c3d2689d | balrog | |
185 | c3d2689d | balrog | switch (offset) {
|
186 | c3d2689d | balrog | case 0x00: /* ITR */ |
187 | 106627d0 | balrog | return bank->irqs;
|
188 | c3d2689d | balrog | |
189 | c3d2689d | balrog | case 0x04: /* MIR */ |
190 | 106627d0 | balrog | return bank->mask;
|
191 | c3d2689d | balrog | |
192 | c3d2689d | balrog | case 0x10: /* SIR_IRQ_CODE */ |
193 | 106627d0 | balrog | case 0x14: /* SIR_FIQ_CODE */ |
194 | 106627d0 | balrog | if (bank_no != 0) |
195 | 106627d0 | balrog | break;
|
196 | 106627d0 | balrog | line_no = s->sir_intr[(offset - 0x10) >> 2]; |
197 | 106627d0 | balrog | bank = &s->banks[line_no >> 5];
|
198 | 106627d0 | balrog | i = line_no & 31;
|
199 | 106627d0 | balrog | if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE) |
200 | 106627d0 | balrog | bank->irqs &= ~(1 << i);
|
201 | f2df5260 | balrog | return line_no;
|
202 | c3d2689d | balrog | |
203 | c3d2689d | balrog | case 0x18: /* CONTROL_REG */ |
204 | 106627d0 | balrog | if (bank_no != 0) |
205 | 106627d0 | balrog | break;
|
206 | c3d2689d | balrog | return 0; |
207 | c3d2689d | balrog | |
208 | c3d2689d | balrog | case 0x1c: /* ILR0 */ |
209 | c3d2689d | balrog | case 0x20: /* ILR1 */ |
210 | c3d2689d | balrog | case 0x24: /* ILR2 */ |
211 | c3d2689d | balrog | case 0x28: /* ILR3 */ |
212 | c3d2689d | balrog | case 0x2c: /* ILR4 */ |
213 | c3d2689d | balrog | case 0x30: /* ILR5 */ |
214 | c3d2689d | balrog | case 0x34: /* ILR6 */ |
215 | c3d2689d | balrog | case 0x38: /* ILR7 */ |
216 | c3d2689d | balrog | case 0x3c: /* ILR8 */ |
217 | c3d2689d | balrog | case 0x40: /* ILR9 */ |
218 | c3d2689d | balrog | case 0x44: /* ILR10 */ |
219 | c3d2689d | balrog | case 0x48: /* ILR11 */ |
220 | c3d2689d | balrog | case 0x4c: /* ILR12 */ |
221 | c3d2689d | balrog | case 0x50: /* ILR13 */ |
222 | c3d2689d | balrog | case 0x54: /* ILR14 */ |
223 | c3d2689d | balrog | case 0x58: /* ILR15 */ |
224 | c3d2689d | balrog | case 0x5c: /* ILR16 */ |
225 | c3d2689d | balrog | case 0x60: /* ILR17 */ |
226 | c3d2689d | balrog | case 0x64: /* ILR18 */ |
227 | c3d2689d | balrog | case 0x68: /* ILR19 */ |
228 | c3d2689d | balrog | case 0x6c: /* ILR20 */ |
229 | c3d2689d | balrog | case 0x70: /* ILR21 */ |
230 | c3d2689d | balrog | case 0x74: /* ILR22 */ |
231 | c3d2689d | balrog | case 0x78: /* ILR23 */ |
232 | c3d2689d | balrog | case 0x7c: /* ILR24 */ |
233 | c3d2689d | balrog | case 0x80: /* ILR25 */ |
234 | c3d2689d | balrog | case 0x84: /* ILR26 */ |
235 | c3d2689d | balrog | case 0x88: /* ILR27 */ |
236 | c3d2689d | balrog | case 0x8c: /* ILR28 */ |
237 | c3d2689d | balrog | case 0x90: /* ILR29 */ |
238 | c3d2689d | balrog | case 0x94: /* ILR30 */ |
239 | c3d2689d | balrog | case 0x98: /* ILR31 */ |
240 | c3d2689d | balrog | i = (offset - 0x1c) >> 2; |
241 | 106627d0 | balrog | return (bank->priority[i] << 2) | |
242 | 106627d0 | balrog | (((bank->sens_edge >> i) & 1) << 1) | |
243 | 106627d0 | balrog | ((bank->fiq >> i) & 1);
|
244 | c3d2689d | balrog | |
245 | c3d2689d | balrog | case 0x9c: /* ISR */ |
246 | c3d2689d | balrog | return 0x00000000; |
247 | c3d2689d | balrog | |
248 | c3d2689d | balrog | } |
249 | 106627d0 | balrog | OMAP_BAD_REG(addr); |
250 | c3d2689d | balrog | return 0; |
251 | c3d2689d | balrog | } |
252 | c3d2689d | balrog | |
253 | c3d2689d | balrog | static void omap_inth_write(void *opaque, target_phys_addr_t addr, |
254 | c3d2689d | balrog | uint32_t value) |
255 | c3d2689d | balrog | { |
256 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
257 | c3d2689d | balrog | int i, offset = addr - s->base;
|
258 | 106627d0 | balrog | int bank_no = offset >> 8; |
259 | 106627d0 | balrog | struct omap_intr_handler_bank_s *bank = &s->banks[bank_no];
|
260 | 106627d0 | balrog | offset &= 0xff;
|
261 | c3d2689d | balrog | |
262 | c3d2689d | balrog | switch (offset) {
|
263 | c3d2689d | balrog | case 0x00: /* ITR */ |
264 | 106627d0 | balrog | /* Important: ignore the clearing if the IRQ is level-triggered and
|
265 | 106627d0 | balrog | the input bit is 1 */
|
266 | 106627d0 | balrog | bank->irqs &= value | (bank->inputs & bank->sens_edge); |
267 | c3d2689d | balrog | return;
|
268 | c3d2689d | balrog | |
269 | c3d2689d | balrog | case 0x04: /* MIR */ |
270 | 106627d0 | balrog | bank->mask = value; |
271 | 106627d0 | balrog | omap_inth_update(s, 0);
|
272 | 106627d0 | balrog | omap_inth_update(s, 1);
|
273 | c3d2689d | balrog | return;
|
274 | c3d2689d | balrog | |
275 | c3d2689d | balrog | case 0x10: /* SIR_IRQ_CODE */ |
276 | c3d2689d | balrog | case 0x14: /* SIR_FIQ_CODE */ |
277 | c3d2689d | balrog | OMAP_RO_REG(addr); |
278 | c3d2689d | balrog | break;
|
279 | c3d2689d | balrog | |
280 | c3d2689d | balrog | case 0x18: /* CONTROL_REG */ |
281 | 106627d0 | balrog | if (bank_no != 0) |
282 | 106627d0 | balrog | break;
|
283 | 106627d0 | balrog | if (value & 2) { |
284 | 106627d0 | balrog | qemu_set_irq(s->parent_intr[1], 0); |
285 | 106627d0 | balrog | s->new_agr[1] = ~0; |
286 | 106627d0 | balrog | omap_inth_update(s, 1);
|
287 | 106627d0 | balrog | } |
288 | 106627d0 | balrog | if (value & 1) { |
289 | 106627d0 | balrog | qemu_set_irq(s->parent_intr[0], 0); |
290 | 106627d0 | balrog | s->new_agr[0] = ~0; |
291 | 106627d0 | balrog | omap_inth_update(s, 0);
|
292 | 106627d0 | balrog | } |
293 | c3d2689d | balrog | return;
|
294 | c3d2689d | balrog | |
295 | c3d2689d | balrog | case 0x1c: /* ILR0 */ |
296 | c3d2689d | balrog | case 0x20: /* ILR1 */ |
297 | c3d2689d | balrog | case 0x24: /* ILR2 */ |
298 | c3d2689d | balrog | case 0x28: /* ILR3 */ |
299 | c3d2689d | balrog | case 0x2c: /* ILR4 */ |
300 | c3d2689d | balrog | case 0x30: /* ILR5 */ |
301 | c3d2689d | balrog | case 0x34: /* ILR6 */ |
302 | c3d2689d | balrog | case 0x38: /* ILR7 */ |
303 | c3d2689d | balrog | case 0x3c: /* ILR8 */ |
304 | c3d2689d | balrog | case 0x40: /* ILR9 */ |
305 | c3d2689d | balrog | case 0x44: /* ILR10 */ |
306 | c3d2689d | balrog | case 0x48: /* ILR11 */ |
307 | c3d2689d | balrog | case 0x4c: /* ILR12 */ |
308 | c3d2689d | balrog | case 0x50: /* ILR13 */ |
309 | c3d2689d | balrog | case 0x54: /* ILR14 */ |
310 | c3d2689d | balrog | case 0x58: /* ILR15 */ |
311 | c3d2689d | balrog | case 0x5c: /* ILR16 */ |
312 | c3d2689d | balrog | case 0x60: /* ILR17 */ |
313 | c3d2689d | balrog | case 0x64: /* ILR18 */ |
314 | c3d2689d | balrog | case 0x68: /* ILR19 */ |
315 | c3d2689d | balrog | case 0x6c: /* ILR20 */ |
316 | c3d2689d | balrog | case 0x70: /* ILR21 */ |
317 | c3d2689d | balrog | case 0x74: /* ILR22 */ |
318 | c3d2689d | balrog | case 0x78: /* ILR23 */ |
319 | c3d2689d | balrog | case 0x7c: /* ILR24 */ |
320 | c3d2689d | balrog | case 0x80: /* ILR25 */ |
321 | c3d2689d | balrog | case 0x84: /* ILR26 */ |
322 | c3d2689d | balrog | case 0x88: /* ILR27 */ |
323 | c3d2689d | balrog | case 0x8c: /* ILR28 */ |
324 | c3d2689d | balrog | case 0x90: /* ILR29 */ |
325 | c3d2689d | balrog | case 0x94: /* ILR30 */ |
326 | c3d2689d | balrog | case 0x98: /* ILR31 */ |
327 | c3d2689d | balrog | i = (offset - 0x1c) >> 2; |
328 | 106627d0 | balrog | bank->priority[i] = (value >> 2) & 0x1f; |
329 | 106627d0 | balrog | bank->sens_edge &= ~(1 << i);
|
330 | 106627d0 | balrog | bank->sens_edge |= ((value >> 1) & 1) << i; |
331 | 106627d0 | balrog | bank->fiq &= ~(1 << i);
|
332 | 106627d0 | balrog | bank->fiq |= (value & 1) << i;
|
333 | c3d2689d | balrog | return;
|
334 | c3d2689d | balrog | |
335 | c3d2689d | balrog | case 0x9c: /* ISR */ |
336 | c3d2689d | balrog | for (i = 0; i < 32; i ++) |
337 | c3d2689d | balrog | if (value & (1 << i)) { |
338 | 106627d0 | balrog | omap_set_intr(s, 32 * bank_no + i, 1); |
339 | c3d2689d | balrog | return;
|
340 | c3d2689d | balrog | } |
341 | c3d2689d | balrog | return;
|
342 | c3d2689d | balrog | } |
343 | 106627d0 | balrog | OMAP_BAD_REG(addr); |
344 | c3d2689d | balrog | } |
345 | c3d2689d | balrog | |
346 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_inth_readfn[] = {
|
347 | c3d2689d | balrog | omap_badwidth_read32, |
348 | c3d2689d | balrog | omap_badwidth_read32, |
349 | c3d2689d | balrog | omap_inth_read, |
350 | c3d2689d | balrog | }; |
351 | c3d2689d | balrog | |
352 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_inth_writefn[] = {
|
353 | c3d2689d | balrog | omap_inth_write, |
354 | c3d2689d | balrog | omap_inth_write, |
355 | c3d2689d | balrog | omap_inth_write, |
356 | c3d2689d | balrog | }; |
357 | c3d2689d | balrog | |
358 | 106627d0 | balrog | void omap_inth_reset(struct omap_intr_handler_s *s) |
359 | c3d2689d | balrog | { |
360 | 106627d0 | balrog | int i;
|
361 | 106627d0 | balrog | |
362 | 106627d0 | balrog | for (i = 0; i < s->nbanks; ++i){ |
363 | 106627d0 | balrog | s->banks[i].irqs = 0x00000000;
|
364 | 106627d0 | balrog | s->banks[i].mask = 0xffffffff;
|
365 | 106627d0 | balrog | s->banks[i].sens_edge = 0x00000000;
|
366 | 106627d0 | balrog | s->banks[i].fiq = 0x00000000;
|
367 | 106627d0 | balrog | s->banks[i].inputs = 0x00000000;
|
368 | 106627d0 | balrog | memset(s->banks[i].priority, 0, sizeof(s->banks[i].priority)); |
369 | 106627d0 | balrog | } |
370 | c3d2689d | balrog | |
371 | 106627d0 | balrog | s->new_agr[0] = ~0; |
372 | 106627d0 | balrog | s->new_agr[1] = ~0; |
373 | 106627d0 | balrog | s->sir_intr[0] = 0; |
374 | 106627d0 | balrog | s->sir_intr[1] = 0; |
375 | 106627d0 | balrog | |
376 | 106627d0 | balrog | qemu_set_irq(s->parent_intr[0], 0); |
377 | 106627d0 | balrog | qemu_set_irq(s->parent_intr[1], 0); |
378 | c3d2689d | balrog | } |
379 | c3d2689d | balrog | |
380 | c3d2689d | balrog | struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
|
381 | 106627d0 | balrog | unsigned long size, unsigned char nbanks, |
382 | 106627d0 | balrog | qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk) |
383 | c3d2689d | balrog | { |
384 | c3d2689d | balrog | int iomemtype;
|
385 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
386 | 106627d0 | balrog | qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
387 | 106627d0 | balrog | sizeof(struct omap_intr_handler_bank_s) * nbanks); |
388 | c3d2689d | balrog | |
389 | 106627d0 | balrog | s->parent_intr[0] = parent_irq;
|
390 | 106627d0 | balrog | s->parent_intr[1] = parent_fiq;
|
391 | c3d2689d | balrog | s->base = base; |
392 | 106627d0 | balrog | s->nbanks = nbanks; |
393 | 106627d0 | balrog | s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
|
394 | 106627d0 | balrog | |
395 | c3d2689d | balrog | omap_inth_reset(s); |
396 | c3d2689d | balrog | |
397 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
|
398 | c3d2689d | balrog | omap_inth_writefn, s); |
399 | c3d2689d | balrog | cpu_register_physical_memory(s->base, size, iomemtype); |
400 | c3d2689d | balrog | |
401 | c3d2689d | balrog | return s;
|
402 | c3d2689d | balrog | } |
403 | c3d2689d | balrog | |
404 | c3d2689d | balrog | /* MPU OS timers */
|
405 | c3d2689d | balrog | struct omap_mpu_timer_s {
|
406 | c3d2689d | balrog | qemu_irq irq; |
407 | c3d2689d | balrog | omap_clk clk; |
408 | c3d2689d | balrog | target_phys_addr_t base; |
409 | c3d2689d | balrog | uint32_t val; |
410 | c3d2689d | balrog | int64_t time; |
411 | c3d2689d | balrog | QEMUTimer *timer; |
412 | c3d2689d | balrog | int64_t rate; |
413 | c3d2689d | balrog | int it_ena;
|
414 | c3d2689d | balrog | |
415 | c3d2689d | balrog | int enable;
|
416 | c3d2689d | balrog | int ptv;
|
417 | c3d2689d | balrog | int ar;
|
418 | c3d2689d | balrog | int st;
|
419 | c3d2689d | balrog | uint32_t reset_val; |
420 | c3d2689d | balrog | }; |
421 | c3d2689d | balrog | |
422 | c3d2689d | balrog | static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) |
423 | c3d2689d | balrog | { |
424 | c3d2689d | balrog | uint64_t distance = qemu_get_clock(vm_clock) - timer->time; |
425 | c3d2689d | balrog | |
426 | c3d2689d | balrog | if (timer->st && timer->enable && timer->rate)
|
427 | c3d2689d | balrog | return timer->val - muldiv64(distance >> (timer->ptv + 1), |
428 | c3d2689d | balrog | timer->rate, ticks_per_sec); |
429 | c3d2689d | balrog | else
|
430 | c3d2689d | balrog | return timer->val;
|
431 | c3d2689d | balrog | } |
432 | c3d2689d | balrog | |
433 | c3d2689d | balrog | static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) |
434 | c3d2689d | balrog | { |
435 | c3d2689d | balrog | timer->val = omap_timer_read(timer); |
436 | c3d2689d | balrog | timer->time = qemu_get_clock(vm_clock); |
437 | c3d2689d | balrog | } |
438 | c3d2689d | balrog | |
439 | c3d2689d | balrog | static inline void omap_timer_update(struct omap_mpu_timer_s *timer) |
440 | c3d2689d | balrog | { |
441 | c3d2689d | balrog | int64_t expires; |
442 | c3d2689d | balrog | |
443 | c3d2689d | balrog | if (timer->enable && timer->st && timer->rate) {
|
444 | c3d2689d | balrog | timer->val = timer->reset_val; /* Should skip this on clk enable */
|
445 | b854bc19 | balrog | expires = muldiv64(timer->val << (timer->ptv + 1),
|
446 | c3d2689d | balrog | ticks_per_sec, timer->rate); |
447 | b854bc19 | balrog | |
448 | b854bc19 | balrog | /* If timer expiry would be sooner than in about 1 ms and
|
449 | b854bc19 | balrog | * auto-reload isn't set, then fire immediately. This is a hack
|
450 | b854bc19 | balrog | * to make systems like PalmOS run in acceptable time. PalmOS
|
451 | b854bc19 | balrog | * sets the interval to a very low value and polls the status bit
|
452 | b854bc19 | balrog | * in a busy loop when it wants to sleep just a couple of CPU
|
453 | b854bc19 | balrog | * ticks. */
|
454 | b854bc19 | balrog | if (expires > (ticks_per_sec >> 10) || timer->ar) |
455 | b854bc19 | balrog | qemu_mod_timer(timer->timer, timer->time + expires); |
456 | b854bc19 | balrog | else {
|
457 | b854bc19 | balrog | timer->val = 0;
|
458 | b854bc19 | balrog | timer->st = 0;
|
459 | b854bc19 | balrog | if (timer->it_ena)
|
460 | 106627d0 | balrog | /* Edge-triggered irq */
|
461 | 106627d0 | balrog | qemu_irq_pulse(timer->irq); |
462 | b854bc19 | balrog | } |
463 | c3d2689d | balrog | } else
|
464 | c3d2689d | balrog | qemu_del_timer(timer->timer); |
465 | c3d2689d | balrog | } |
466 | c3d2689d | balrog | |
467 | c3d2689d | balrog | static void omap_timer_tick(void *opaque) |
468 | c3d2689d | balrog | { |
469 | c3d2689d | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
470 | c3d2689d | balrog | omap_timer_sync(timer); |
471 | c3d2689d | balrog | |
472 | c3d2689d | balrog | if (!timer->ar) {
|
473 | c3d2689d | balrog | timer->val = 0;
|
474 | c3d2689d | balrog | timer->st = 0;
|
475 | c3d2689d | balrog | } |
476 | c3d2689d | balrog | |
477 | c3d2689d | balrog | if (timer->it_ena)
|
478 | 106627d0 | balrog | /* Edge-triggered irq */
|
479 | 106627d0 | balrog | qemu_irq_pulse(timer->irq); |
480 | c3d2689d | balrog | omap_timer_update(timer); |
481 | c3d2689d | balrog | } |
482 | c3d2689d | balrog | |
483 | c3d2689d | balrog | static void omap_timer_clk_update(void *opaque, int line, int on) |
484 | c3d2689d | balrog | { |
485 | c3d2689d | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
486 | c3d2689d | balrog | |
487 | c3d2689d | balrog | omap_timer_sync(timer); |
488 | c3d2689d | balrog | timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
|
489 | c3d2689d | balrog | omap_timer_update(timer); |
490 | c3d2689d | balrog | } |
491 | c3d2689d | balrog | |
492 | c3d2689d | balrog | static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) |
493 | c3d2689d | balrog | { |
494 | c3d2689d | balrog | omap_clk_adduser(timer->clk, |
495 | c3d2689d | balrog | qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]); |
496 | c3d2689d | balrog | timer->rate = omap_clk_getrate(timer->clk); |
497 | c3d2689d | balrog | } |
498 | c3d2689d | balrog | |
499 | c3d2689d | balrog | static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) |
500 | c3d2689d | balrog | { |
501 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
502 | c3d2689d | balrog | int offset = addr - s->base;
|
503 | c3d2689d | balrog | |
504 | c3d2689d | balrog | switch (offset) {
|
505 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
506 | c3d2689d | balrog | return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; |
507 | c3d2689d | balrog | |
508 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
509 | c3d2689d | balrog | break;
|
510 | c3d2689d | balrog | |
511 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
512 | c3d2689d | balrog | return omap_timer_read(s);
|
513 | c3d2689d | balrog | } |
514 | c3d2689d | balrog | |
515 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
516 | c3d2689d | balrog | return 0; |
517 | c3d2689d | balrog | } |
518 | c3d2689d | balrog | |
519 | c3d2689d | balrog | static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, |
520 | c3d2689d | balrog | uint32_t value) |
521 | c3d2689d | balrog | { |
522 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
523 | c3d2689d | balrog | int offset = addr - s->base;
|
524 | c3d2689d | balrog | |
525 | c3d2689d | balrog | switch (offset) {
|
526 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
527 | c3d2689d | balrog | omap_timer_sync(s); |
528 | c3d2689d | balrog | s->enable = (value >> 5) & 1; |
529 | c3d2689d | balrog | s->ptv = (value >> 2) & 7; |
530 | c3d2689d | balrog | s->ar = (value >> 1) & 1; |
531 | c3d2689d | balrog | s->st = value & 1;
|
532 | c3d2689d | balrog | omap_timer_update(s); |
533 | c3d2689d | balrog | return;
|
534 | c3d2689d | balrog | |
535 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
536 | c3d2689d | balrog | s->reset_val = value; |
537 | c3d2689d | balrog | return;
|
538 | c3d2689d | balrog | |
539 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
540 | c3d2689d | balrog | OMAP_RO_REG(addr); |
541 | c3d2689d | balrog | break;
|
542 | c3d2689d | balrog | |
543 | c3d2689d | balrog | default:
|
544 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
545 | c3d2689d | balrog | } |
546 | c3d2689d | balrog | } |
547 | c3d2689d | balrog | |
548 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
|
549 | c3d2689d | balrog | omap_badwidth_read32, |
550 | c3d2689d | balrog | omap_badwidth_read32, |
551 | c3d2689d | balrog | omap_mpu_timer_read, |
552 | c3d2689d | balrog | }; |
553 | c3d2689d | balrog | |
554 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
|
555 | c3d2689d | balrog | omap_badwidth_write32, |
556 | c3d2689d | balrog | omap_badwidth_write32, |
557 | c3d2689d | balrog | omap_mpu_timer_write, |
558 | c3d2689d | balrog | }; |
559 | c3d2689d | balrog | |
560 | c3d2689d | balrog | static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) |
561 | c3d2689d | balrog | { |
562 | c3d2689d | balrog | qemu_del_timer(s->timer); |
563 | c3d2689d | balrog | s->enable = 0;
|
564 | c3d2689d | balrog | s->reset_val = 31337;
|
565 | c3d2689d | balrog | s->val = 0;
|
566 | c3d2689d | balrog | s->ptv = 0;
|
567 | c3d2689d | balrog | s->ar = 0;
|
568 | c3d2689d | balrog | s->st = 0;
|
569 | c3d2689d | balrog | s->it_ena = 1;
|
570 | c3d2689d | balrog | } |
571 | c3d2689d | balrog | |
572 | c3d2689d | balrog | struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
|
573 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
574 | c3d2689d | balrog | { |
575 | c3d2689d | balrog | int iomemtype;
|
576 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) |
577 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_mpu_timer_s)); |
578 | c3d2689d | balrog | |
579 | c3d2689d | balrog | s->irq = irq; |
580 | c3d2689d | balrog | s->clk = clk; |
581 | c3d2689d | balrog | s->base = base; |
582 | c3d2689d | balrog | s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s); |
583 | c3d2689d | balrog | omap_mpu_timer_reset(s); |
584 | c3d2689d | balrog | omap_timer_clk_setup(s); |
585 | c3d2689d | balrog | |
586 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
|
587 | c3d2689d | balrog | omap_mpu_timer_writefn, s); |
588 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
589 | c3d2689d | balrog | |
590 | c3d2689d | balrog | return s;
|
591 | c3d2689d | balrog | } |
592 | c3d2689d | balrog | |
593 | c3d2689d | balrog | /* Watchdog timer */
|
594 | c3d2689d | balrog | struct omap_watchdog_timer_s {
|
595 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
|
596 | c3d2689d | balrog | uint8_t last_wr; |
597 | c3d2689d | balrog | int mode;
|
598 | c3d2689d | balrog | int free;
|
599 | c3d2689d | balrog | int reset;
|
600 | c3d2689d | balrog | }; |
601 | c3d2689d | balrog | |
602 | c3d2689d | balrog | static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) |
603 | c3d2689d | balrog | { |
604 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
605 | c3d2689d | balrog | int offset = addr - s->timer.base;
|
606 | c3d2689d | balrog | |
607 | c3d2689d | balrog | switch (offset) {
|
608 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
609 | c3d2689d | balrog | return (s->timer.ptv << 9) | (s->timer.ar << 8) | |
610 | c3d2689d | balrog | (s->timer.st << 7) | (s->free << 1); |
611 | c3d2689d | balrog | |
612 | c3d2689d | balrog | case 0x04: /* READ_TIMER */ |
613 | c3d2689d | balrog | return omap_timer_read(&s->timer);
|
614 | c3d2689d | balrog | |
615 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
616 | c3d2689d | balrog | return s->mode << 15; |
617 | c3d2689d | balrog | } |
618 | c3d2689d | balrog | |
619 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
620 | c3d2689d | balrog | return 0; |
621 | c3d2689d | balrog | } |
622 | c3d2689d | balrog | |
623 | c3d2689d | balrog | static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, |
624 | c3d2689d | balrog | uint32_t value) |
625 | c3d2689d | balrog | { |
626 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
627 | c3d2689d | balrog | int offset = addr - s->timer.base;
|
628 | c3d2689d | balrog | |
629 | c3d2689d | balrog | switch (offset) {
|
630 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
631 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
632 | c3d2689d | balrog | s->timer.ptv = (value >> 9) & 7; |
633 | c3d2689d | balrog | s->timer.ar = (value >> 8) & 1; |
634 | c3d2689d | balrog | s->timer.st = (value >> 7) & 1; |
635 | c3d2689d | balrog | s->free = (value >> 1) & 1; |
636 | c3d2689d | balrog | omap_timer_update(&s->timer); |
637 | c3d2689d | balrog | break;
|
638 | c3d2689d | balrog | |
639 | c3d2689d | balrog | case 0x04: /* LOAD_TIMER */ |
640 | c3d2689d | balrog | s->timer.reset_val = value & 0xffff;
|
641 | c3d2689d | balrog | break;
|
642 | c3d2689d | balrog | |
643 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
644 | c3d2689d | balrog | if (!s->mode && ((value >> 15) & 1)) |
645 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
646 | c3d2689d | balrog | s->mode |= (value >> 15) & 1; |
647 | c3d2689d | balrog | if (s->last_wr == 0xf5) { |
648 | c3d2689d | balrog | if ((value & 0xff) == 0xa0) { |
649 | d8f699cb | balrog | if (s->mode) {
|
650 | d8f699cb | balrog | s->mode = 0;
|
651 | d8f699cb | balrog | omap_clk_put(s->timer.clk); |
652 | d8f699cb | balrog | } |
653 | c3d2689d | balrog | } else {
|
654 | c3d2689d | balrog | /* XXX: on T|E hardware somehow this has no effect,
|
655 | c3d2689d | balrog | * on Zire 71 it works as specified. */
|
656 | c3d2689d | balrog | s->reset = 1;
|
657 | c3d2689d | balrog | qemu_system_reset_request(); |
658 | c3d2689d | balrog | } |
659 | c3d2689d | balrog | } |
660 | c3d2689d | balrog | s->last_wr = value & 0xff;
|
661 | c3d2689d | balrog | break;
|
662 | c3d2689d | balrog | |
663 | c3d2689d | balrog | default:
|
664 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
665 | c3d2689d | balrog | } |
666 | c3d2689d | balrog | } |
667 | c3d2689d | balrog | |
668 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
|
669 | c3d2689d | balrog | omap_badwidth_read16, |
670 | c3d2689d | balrog | omap_wd_timer_read, |
671 | c3d2689d | balrog | omap_badwidth_read16, |
672 | c3d2689d | balrog | }; |
673 | c3d2689d | balrog | |
674 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
|
675 | c3d2689d | balrog | omap_badwidth_write16, |
676 | c3d2689d | balrog | omap_wd_timer_write, |
677 | c3d2689d | balrog | omap_badwidth_write16, |
678 | c3d2689d | balrog | }; |
679 | c3d2689d | balrog | |
680 | c3d2689d | balrog | static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) |
681 | c3d2689d | balrog | { |
682 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
683 | c3d2689d | balrog | if (!s->mode)
|
684 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
685 | c3d2689d | balrog | s->mode = 1;
|
686 | c3d2689d | balrog | s->free = 1;
|
687 | c3d2689d | balrog | s->reset = 0;
|
688 | c3d2689d | balrog | s->timer.enable = 1;
|
689 | c3d2689d | balrog | s->timer.it_ena = 1;
|
690 | c3d2689d | balrog | s->timer.reset_val = 0xffff;
|
691 | c3d2689d | balrog | s->timer.val = 0;
|
692 | c3d2689d | balrog | s->timer.st = 0;
|
693 | c3d2689d | balrog | s->timer.ptv = 0;
|
694 | c3d2689d | balrog | s->timer.ar = 0;
|
695 | c3d2689d | balrog | omap_timer_update(&s->timer); |
696 | c3d2689d | balrog | } |
697 | c3d2689d | balrog | |
698 | c3d2689d | balrog | struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
|
699 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
700 | c3d2689d | balrog | { |
701 | c3d2689d | balrog | int iomemtype;
|
702 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) |
703 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_watchdog_timer_s)); |
704 | c3d2689d | balrog | |
705 | c3d2689d | balrog | s->timer.irq = irq; |
706 | c3d2689d | balrog | s->timer.clk = clk; |
707 | c3d2689d | balrog | s->timer.base = base; |
708 | c3d2689d | balrog | s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
709 | c3d2689d | balrog | omap_wd_timer_reset(s); |
710 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
711 | c3d2689d | balrog | |
712 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
|
713 | c3d2689d | balrog | omap_wd_timer_writefn, s); |
714 | c3d2689d | balrog | cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
|
715 | c3d2689d | balrog | |
716 | c3d2689d | balrog | return s;
|
717 | c3d2689d | balrog | } |
718 | c3d2689d | balrog | |
719 | c3d2689d | balrog | /* 32-kHz timer */
|
720 | c3d2689d | balrog | struct omap_32khz_timer_s {
|
721 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
|
722 | c3d2689d | balrog | }; |
723 | c3d2689d | balrog | |
724 | c3d2689d | balrog | static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) |
725 | c3d2689d | balrog | { |
726 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
727 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
728 | c3d2689d | balrog | |
729 | c3d2689d | balrog | switch (offset) {
|
730 | c3d2689d | balrog | case 0x00: /* TVR */ |
731 | c3d2689d | balrog | return s->timer.reset_val;
|
732 | c3d2689d | balrog | |
733 | c3d2689d | balrog | case 0x04: /* TCR */ |
734 | c3d2689d | balrog | return omap_timer_read(&s->timer);
|
735 | c3d2689d | balrog | |
736 | c3d2689d | balrog | case 0x08: /* CR */ |
737 | c3d2689d | balrog | return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; |
738 | c3d2689d | balrog | |
739 | c3d2689d | balrog | default:
|
740 | c3d2689d | balrog | break;
|
741 | c3d2689d | balrog | } |
742 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
743 | c3d2689d | balrog | return 0; |
744 | c3d2689d | balrog | } |
745 | c3d2689d | balrog | |
746 | c3d2689d | balrog | static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, |
747 | c3d2689d | balrog | uint32_t value) |
748 | c3d2689d | balrog | { |
749 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
750 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
751 | c3d2689d | balrog | |
752 | c3d2689d | balrog | switch (offset) {
|
753 | c3d2689d | balrog | case 0x00: /* TVR */ |
754 | c3d2689d | balrog | s->timer.reset_val = value & 0x00ffffff;
|
755 | c3d2689d | balrog | break;
|
756 | c3d2689d | balrog | |
757 | c3d2689d | balrog | case 0x04: /* TCR */ |
758 | c3d2689d | balrog | OMAP_RO_REG(addr); |
759 | c3d2689d | balrog | break;
|
760 | c3d2689d | balrog | |
761 | c3d2689d | balrog | case 0x08: /* CR */ |
762 | c3d2689d | balrog | s->timer.ar = (value >> 3) & 1; |
763 | c3d2689d | balrog | s->timer.it_ena = (value >> 2) & 1; |
764 | c3d2689d | balrog | if (s->timer.st != (value & 1) || (value & 2)) { |
765 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
766 | c3d2689d | balrog | s->timer.enable = value & 1;
|
767 | c3d2689d | balrog | s->timer.st = value & 1;
|
768 | c3d2689d | balrog | omap_timer_update(&s->timer); |
769 | c3d2689d | balrog | } |
770 | c3d2689d | balrog | break;
|
771 | c3d2689d | balrog | |
772 | c3d2689d | balrog | default:
|
773 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
774 | c3d2689d | balrog | } |
775 | c3d2689d | balrog | } |
776 | c3d2689d | balrog | |
777 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
|
778 | c3d2689d | balrog | omap_badwidth_read32, |
779 | c3d2689d | balrog | omap_badwidth_read32, |
780 | c3d2689d | balrog | omap_os_timer_read, |
781 | c3d2689d | balrog | }; |
782 | c3d2689d | balrog | |
783 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
|
784 | c3d2689d | balrog | omap_badwidth_write32, |
785 | c3d2689d | balrog | omap_badwidth_write32, |
786 | c3d2689d | balrog | omap_os_timer_write, |
787 | c3d2689d | balrog | }; |
788 | c3d2689d | balrog | |
789 | c3d2689d | balrog | static void omap_os_timer_reset(struct omap_32khz_timer_s *s) |
790 | c3d2689d | balrog | { |
791 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
792 | c3d2689d | balrog | s->timer.enable = 0;
|
793 | c3d2689d | balrog | s->timer.it_ena = 0;
|
794 | c3d2689d | balrog | s->timer.reset_val = 0x00ffffff;
|
795 | c3d2689d | balrog | s->timer.val = 0;
|
796 | c3d2689d | balrog | s->timer.st = 0;
|
797 | c3d2689d | balrog | s->timer.ptv = 0;
|
798 | c3d2689d | balrog | s->timer.ar = 1;
|
799 | c3d2689d | balrog | } |
800 | c3d2689d | balrog | |
801 | c3d2689d | balrog | struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
|
802 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
803 | c3d2689d | balrog | { |
804 | c3d2689d | balrog | int iomemtype;
|
805 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) |
806 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_32khz_timer_s)); |
807 | c3d2689d | balrog | |
808 | c3d2689d | balrog | s->timer.irq = irq; |
809 | c3d2689d | balrog | s->timer.clk = clk; |
810 | c3d2689d | balrog | s->timer.base = base; |
811 | c3d2689d | balrog | s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
812 | c3d2689d | balrog | omap_os_timer_reset(s); |
813 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
814 | c3d2689d | balrog | |
815 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
|
816 | c3d2689d | balrog | omap_os_timer_writefn, s); |
817 | c3d2689d | balrog | cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
|
818 | c3d2689d | balrog | |
819 | c3d2689d | balrog | return s;
|
820 | c3d2689d | balrog | } |
821 | c3d2689d | balrog | |
822 | c3d2689d | balrog | /* Ultra Low-Power Device Module */
|
823 | c3d2689d | balrog | static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr) |
824 | c3d2689d | balrog | { |
825 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
826 | c3d2689d | balrog | int offset = addr - s->ulpd_pm_base;
|
827 | c3d2689d | balrog | uint16_t ret; |
828 | c3d2689d | balrog | |
829 | c3d2689d | balrog | switch (offset) {
|
830 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
831 | c3d2689d | balrog | ret = s->ulpd_pm_regs[offset >> 2];
|
832 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = 0; |
833 | c3d2689d | balrog | qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
|
834 | c3d2689d | balrog | return ret;
|
835 | c3d2689d | balrog | |
836 | c3d2689d | balrog | case 0x18: /* Reserved */ |
837 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
838 | c3d2689d | balrog | case 0x20: /* Reserved */ |
839 | c3d2689d | balrog | case 0x28: /* Reserved */ |
840 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
841 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
842 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
843 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
844 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
845 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
846 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
847 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
848 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
849 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
850 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
851 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
852 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
853 | c3d2689d | balrog | /* XXX: check clk::usecount state for every clock */
|
854 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
855 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
856 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
857 | c3d2689d | balrog | return s->ulpd_pm_regs[offset >> 2]; |
858 | c3d2689d | balrog | } |
859 | c3d2689d | balrog | |
860 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
861 | c3d2689d | balrog | return 0; |
862 | c3d2689d | balrog | } |
863 | c3d2689d | balrog | |
864 | c3d2689d | balrog | static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, |
865 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
866 | c3d2689d | balrog | { |
867 | c3d2689d | balrog | if (diff & (1 << 4)) /* USB_MCLK_EN */ |
868 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); |
869 | c3d2689d | balrog | if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ |
870 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); |
871 | c3d2689d | balrog | } |
872 | c3d2689d | balrog | |
873 | c3d2689d | balrog | static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, |
874 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
875 | c3d2689d | balrog | { |
876 | c3d2689d | balrog | if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ |
877 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); |
878 | c3d2689d | balrog | if (diff & (1 << 1)) /* SOFT_COM_REQ */ |
879 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); |
880 | c3d2689d | balrog | if (diff & (1 << 2)) /* SOFT_SDW_REQ */ |
881 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); |
882 | c3d2689d | balrog | if (diff & (1 << 3)) /* SOFT_USB_REQ */ |
883 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); |
884 | c3d2689d | balrog | } |
885 | c3d2689d | balrog | |
886 | c3d2689d | balrog | static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, |
887 | c3d2689d | balrog | uint32_t value) |
888 | c3d2689d | balrog | { |
889 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
890 | c3d2689d | balrog | int offset = addr - s->ulpd_pm_base;
|
891 | c3d2689d | balrog | int64_t now, ticks; |
892 | c3d2689d | balrog | int div, mult;
|
893 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
894 | c3d2689d | balrog | uint16_t diff; |
895 | c3d2689d | balrog | |
896 | c3d2689d | balrog | switch (offset) {
|
897 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
898 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
899 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
900 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
901 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
902 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
903 | c3d2689d | balrog | OMAP_RO_REG(addr); |
904 | c3d2689d | balrog | break;
|
905 | c3d2689d | balrog | |
906 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
907 | c3d2689d | balrog | /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
|
908 | c3d2689d | balrog | if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) { |
909 | c3d2689d | balrog | now = qemu_get_clock(vm_clock); |
910 | c3d2689d | balrog | |
911 | c3d2689d | balrog | if (value & 1) |
912 | c3d2689d | balrog | s->ulpd_gauge_start = now; |
913 | c3d2689d | balrog | else {
|
914 | c3d2689d | balrog | now -= s->ulpd_gauge_start; |
915 | c3d2689d | balrog | |
916 | c3d2689d | balrog | /* 32-kHz ticks */
|
917 | c3d2689d | balrog | ticks = muldiv64(now, 32768, ticks_per_sec);
|
918 | c3d2689d | balrog | s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; |
919 | c3d2689d | balrog | s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; |
920 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_32K */ |
921 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; |
922 | c3d2689d | balrog | |
923 | c3d2689d | balrog | /* High frequency ticks */
|
924 | c3d2689d | balrog | ticks = muldiv64(now, 12000000, ticks_per_sec);
|
925 | c3d2689d | balrog | s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; |
926 | c3d2689d | balrog | s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; |
927 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_HI_FREQ */ |
928 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; |
929 | c3d2689d | balrog | |
930 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ |
931 | c3d2689d | balrog | qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
|
932 | c3d2689d | balrog | } |
933 | c3d2689d | balrog | } |
934 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value;
|
935 | c3d2689d | balrog | break;
|
936 | c3d2689d | balrog | |
937 | c3d2689d | balrog | case 0x18: /* Reserved */ |
938 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
939 | c3d2689d | balrog | case 0x20: /* Reserved */ |
940 | c3d2689d | balrog | case 0x28: /* Reserved */ |
941 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
942 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
943 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
944 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
945 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
946 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
947 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value;
|
948 | c3d2689d | balrog | break;
|
949 | c3d2689d | balrog | |
950 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
951 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
952 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x3f; |
953 | c3d2689d | balrog | omap_ulpd_clk_update(s, diff, value); |
954 | c3d2689d | balrog | break;
|
955 | c3d2689d | balrog | |
956 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
957 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
958 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x1f; |
959 | c3d2689d | balrog | omap_ulpd_req_update(s, diff, value); |
960 | c3d2689d | balrog | break;
|
961 | c3d2689d | balrog | |
962 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
963 | c3d2689d | balrog | /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
|
964 | c3d2689d | balrog | * omitted altogether, probably a typo. */
|
965 | c3d2689d | balrog | /* This register has identical semantics with DPLL(1:3) control
|
966 | c3d2689d | balrog | * registers, see omap_dpll_write() */
|
967 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] & value;
|
968 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x2fff; |
969 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
970 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
971 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
972 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
973 | c3d2689d | balrog | } else {
|
974 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
975 | c3d2689d | balrog | mult = 1;
|
976 | c3d2689d | balrog | } |
977 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
|
978 | c3d2689d | balrog | } |
979 | c3d2689d | balrog | |
980 | c3d2689d | balrog | /* Enter the desired mode. */
|
981 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] =
|
982 | c3d2689d | balrog | (s->ulpd_pm_regs[offset >> 2] & 0xfffe) | |
983 | c3d2689d | balrog | ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1); |
984 | c3d2689d | balrog | |
985 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
986 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] |= 2; |
987 | c3d2689d | balrog | break;
|
988 | c3d2689d | balrog | |
989 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
990 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] & value;
|
991 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0xf; |
992 | c3d2689d | balrog | if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
993 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
|
994 | c3d2689d | balrog | (value & (1 << 0)) ? "apll" : "dpll4")); |
995 | c3d2689d | balrog | break;
|
996 | c3d2689d | balrog | |
997 | c3d2689d | balrog | default:
|
998 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
999 | c3d2689d | balrog | } |
1000 | c3d2689d | balrog | } |
1001 | c3d2689d | balrog | |
1002 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
|
1003 | c3d2689d | balrog | omap_badwidth_read16, |
1004 | c3d2689d | balrog | omap_ulpd_pm_read, |
1005 | c3d2689d | balrog | omap_badwidth_read16, |
1006 | c3d2689d | balrog | }; |
1007 | c3d2689d | balrog | |
1008 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
|
1009 | c3d2689d | balrog | omap_badwidth_write16, |
1010 | c3d2689d | balrog | omap_ulpd_pm_write, |
1011 | c3d2689d | balrog | omap_badwidth_write16, |
1012 | c3d2689d | balrog | }; |
1013 | c3d2689d | balrog | |
1014 | c3d2689d | balrog | static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) |
1015 | c3d2689d | balrog | { |
1016 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; |
1017 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; |
1018 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; |
1019 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; |
1020 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; |
1021 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; |
1022 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; |
1023 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; |
1024 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; |
1025 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; |
1026 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; |
1027 | c3d2689d | balrog | omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); |
1028 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; |
1029 | c3d2689d | balrog | omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); |
1030 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; |
1031 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; |
1032 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; |
1033 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ |
1034 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; |
1035 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; |
1036 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; |
1037 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); |
1038 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); |
1039 | c3d2689d | balrog | } |
1040 | c3d2689d | balrog | |
1041 | c3d2689d | balrog | static void omap_ulpd_pm_init(target_phys_addr_t base, |
1042 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1043 | c3d2689d | balrog | { |
1044 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn, |
1045 | c3d2689d | balrog | omap_ulpd_pm_writefn, mpu); |
1046 | c3d2689d | balrog | |
1047 | c3d2689d | balrog | mpu->ulpd_pm_base = base; |
1048 | c3d2689d | balrog | cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
|
1049 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
1050 | c3d2689d | balrog | } |
1051 | c3d2689d | balrog | |
1052 | c3d2689d | balrog | /* OMAP Pin Configuration */
|
1053 | c3d2689d | balrog | static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr) |
1054 | c3d2689d | balrog | { |
1055 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1056 | c3d2689d | balrog | int offset = addr - s->pin_cfg_base;
|
1057 | c3d2689d | balrog | |
1058 | c3d2689d | balrog | switch (offset) {
|
1059 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
1060 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
1061 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
1062 | c3d2689d | balrog | return s->func_mux_ctrl[offset >> 2]; |
1063 | c3d2689d | balrog | |
1064 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
1065 | c3d2689d | balrog | return s->comp_mode_ctrl[0]; |
1066 | c3d2689d | balrog | |
1067 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
1068 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
1069 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
1070 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1071 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
1072 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
1073 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
1074 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
1075 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
1076 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
1077 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
1078 | c3d2689d | balrog | return s->func_mux_ctrl[(offset >> 2) - 1]; |
1079 | c3d2689d | balrog | |
1080 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
1081 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
1082 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
1083 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
1084 | c3d2689d | balrog | return s->pull_dwn_ctrl[(offset & 0xf) >> 2]; |
1085 | c3d2689d | balrog | |
1086 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
1087 | c3d2689d | balrog | return s->gate_inh_ctrl[0]; |
1088 | c3d2689d | balrog | |
1089 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
1090 | c3d2689d | balrog | return s->voltage_ctrl[0]; |
1091 | c3d2689d | balrog | |
1092 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
1093 | c3d2689d | balrog | return s->test_dbg_ctrl[0]; |
1094 | c3d2689d | balrog | |
1095 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
1096 | c3d2689d | balrog | return s->mod_conf_ctrl[0]; |
1097 | c3d2689d | balrog | } |
1098 | c3d2689d | balrog | |
1099 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1100 | c3d2689d | balrog | return 0; |
1101 | c3d2689d | balrog | } |
1102 | c3d2689d | balrog | |
1103 | c3d2689d | balrog | static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, |
1104 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1105 | c3d2689d | balrog | { |
1106 | c3d2689d | balrog | if (s->compat1509) {
|
1107 | c3d2689d | balrog | if (diff & (1 << 9)) /* BLUETOOTH */ |
1108 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
|
1109 | c3d2689d | balrog | (~value >> 9) & 1); |
1110 | c3d2689d | balrog | if (diff & (1 << 7)) /* USB.CLKO */ |
1111 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb.clko"),
|
1112 | c3d2689d | balrog | (value >> 7) & 1); |
1113 | c3d2689d | balrog | } |
1114 | c3d2689d | balrog | } |
1115 | c3d2689d | balrog | |
1116 | c3d2689d | balrog | static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, |
1117 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1118 | c3d2689d | balrog | { |
1119 | c3d2689d | balrog | if (s->compat1509) {
|
1120 | c3d2689d | balrog | if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */ |
1121 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
|
1122 | c3d2689d | balrog | (value >> 31) & 1); |
1123 | c3d2689d | balrog | if (diff & (1 << 1)) /* CLK32K */ |
1124 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "clk32k_out"),
|
1125 | c3d2689d | balrog | (~value >> 1) & 1); |
1126 | c3d2689d | balrog | } |
1127 | c3d2689d | balrog | } |
1128 | c3d2689d | balrog | |
1129 | c3d2689d | balrog | static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, |
1130 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1131 | c3d2689d | balrog | { |
1132 | c3d2689d | balrog | if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */ |
1133 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart3_ck"),
|
1134 | c3d2689d | balrog | omap_findclk(s, ((value >> 31) & 1) ? |
1135 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1136 | c3d2689d | balrog | if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ |
1137 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart2_ck"),
|
1138 | c3d2689d | balrog | omap_findclk(s, ((value >> 30) & 1) ? |
1139 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1140 | c3d2689d | balrog | if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ |
1141 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart1_ck"),
|
1142 | c3d2689d | balrog | omap_findclk(s, ((value >> 29) & 1) ? |
1143 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1144 | c3d2689d | balrog | if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ |
1145 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "mmc_ck"),
|
1146 | c3d2689d | balrog | omap_findclk(s, ((value >> 23) & 1) ? |
1147 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1148 | c3d2689d | balrog | if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ |
1149 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
|
1150 | c3d2689d | balrog | omap_findclk(s, ((value >> 12) & 1) ? |
1151 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1152 | c3d2689d | balrog | if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ |
1153 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); |
1154 | c3d2689d | balrog | } |
1155 | c3d2689d | balrog | |
1156 | c3d2689d | balrog | static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, |
1157 | c3d2689d | balrog | uint32_t value) |
1158 | c3d2689d | balrog | { |
1159 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1160 | c3d2689d | balrog | int offset = addr - s->pin_cfg_base;
|
1161 | c3d2689d | balrog | uint32_t diff; |
1162 | c3d2689d | balrog | |
1163 | c3d2689d | balrog | switch (offset) {
|
1164 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
1165 | c3d2689d | balrog | diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1166 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1167 | c3d2689d | balrog | omap_pin_funcmux0_update(s, diff, value); |
1168 | c3d2689d | balrog | return;
|
1169 | c3d2689d | balrog | |
1170 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
1171 | c3d2689d | balrog | diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1172 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1173 | c3d2689d | balrog | omap_pin_funcmux1_update(s, diff, value); |
1174 | c3d2689d | balrog | return;
|
1175 | c3d2689d | balrog | |
1176 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
1177 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1178 | c3d2689d | balrog | return;
|
1179 | c3d2689d | balrog | |
1180 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
1181 | c3d2689d | balrog | s->comp_mode_ctrl[0] = value;
|
1182 | c3d2689d | balrog | s->compat1509 = (value != 0x0000eaef);
|
1183 | c3d2689d | balrog | omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); |
1184 | c3d2689d | balrog | omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); |
1185 | c3d2689d | balrog | return;
|
1186 | c3d2689d | balrog | |
1187 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
1188 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
1189 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
1190 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1191 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
1192 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
1193 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
1194 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
1195 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
1196 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
1197 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
1198 | c3d2689d | balrog | s->func_mux_ctrl[(offset >> 2) - 1] = value; |
1199 | c3d2689d | balrog | return;
|
1200 | c3d2689d | balrog | |
1201 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
1202 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
1203 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
1204 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
1205 | c3d2689d | balrog | s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value; |
1206 | c3d2689d | balrog | return;
|
1207 | c3d2689d | balrog | |
1208 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
1209 | c3d2689d | balrog | s->gate_inh_ctrl[0] = value;
|
1210 | c3d2689d | balrog | return;
|
1211 | c3d2689d | balrog | |
1212 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
1213 | c3d2689d | balrog | s->voltage_ctrl[0] = value;
|
1214 | c3d2689d | balrog | return;
|
1215 | c3d2689d | balrog | |
1216 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
1217 | c3d2689d | balrog | s->test_dbg_ctrl[0] = value;
|
1218 | c3d2689d | balrog | return;
|
1219 | c3d2689d | balrog | |
1220 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
1221 | c3d2689d | balrog | diff = s->mod_conf_ctrl[0] ^ value;
|
1222 | c3d2689d | balrog | s->mod_conf_ctrl[0] = value;
|
1223 | c3d2689d | balrog | omap_pin_modconf1_update(s, diff, value); |
1224 | c3d2689d | balrog | return;
|
1225 | c3d2689d | balrog | |
1226 | c3d2689d | balrog | default:
|
1227 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1228 | c3d2689d | balrog | } |
1229 | c3d2689d | balrog | } |
1230 | c3d2689d | balrog | |
1231 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
|
1232 | c3d2689d | balrog | omap_badwidth_read32, |
1233 | c3d2689d | balrog | omap_badwidth_read32, |
1234 | c3d2689d | balrog | omap_pin_cfg_read, |
1235 | c3d2689d | balrog | }; |
1236 | c3d2689d | balrog | |
1237 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
|
1238 | c3d2689d | balrog | omap_badwidth_write32, |
1239 | c3d2689d | balrog | omap_badwidth_write32, |
1240 | c3d2689d | balrog | omap_pin_cfg_write, |
1241 | c3d2689d | balrog | }; |
1242 | c3d2689d | balrog | |
1243 | c3d2689d | balrog | static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) |
1244 | c3d2689d | balrog | { |
1245 | c3d2689d | balrog | /* Start in Compatibility Mode. */
|
1246 | c3d2689d | balrog | mpu->compat1509 = 1;
|
1247 | c3d2689d | balrog | omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); |
1248 | c3d2689d | balrog | omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); |
1249 | c3d2689d | balrog | omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); |
1250 | c3d2689d | balrog | memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); |
1251 | c3d2689d | balrog | memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); |
1252 | c3d2689d | balrog | memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); |
1253 | c3d2689d | balrog | memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); |
1254 | c3d2689d | balrog | memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); |
1255 | c3d2689d | balrog | memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); |
1256 | c3d2689d | balrog | memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); |
1257 | c3d2689d | balrog | } |
1258 | c3d2689d | balrog | |
1259 | c3d2689d | balrog | static void omap_pin_cfg_init(target_phys_addr_t base, |
1260 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1261 | c3d2689d | balrog | { |
1262 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn, |
1263 | c3d2689d | balrog | omap_pin_cfg_writefn, mpu); |
1264 | c3d2689d | balrog | |
1265 | c3d2689d | balrog | mpu->pin_cfg_base = base; |
1266 | c3d2689d | balrog | cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
|
1267 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
1268 | c3d2689d | balrog | } |
1269 | c3d2689d | balrog | |
1270 | c3d2689d | balrog | /* Device Identification, Die Identification */
|
1271 | c3d2689d | balrog | static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr) |
1272 | c3d2689d | balrog | { |
1273 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1274 | c3d2689d | balrog | |
1275 | c3d2689d | balrog | switch (addr) {
|
1276 | c3d2689d | balrog | case 0xfffe1800: /* DIE_ID_LSB */ |
1277 | c3d2689d | balrog | return 0xc9581f0e; |
1278 | c3d2689d | balrog | case 0xfffe1804: /* DIE_ID_MSB */ |
1279 | c3d2689d | balrog | return 0xa8858bfa; |
1280 | c3d2689d | balrog | |
1281 | c3d2689d | balrog | case 0xfffe2000: /* PRODUCT_ID_LSB */ |
1282 | c3d2689d | balrog | return 0x00aaaafc; |
1283 | c3d2689d | balrog | case 0xfffe2004: /* PRODUCT_ID_MSB */ |
1284 | c3d2689d | balrog | return 0xcafeb574; |
1285 | c3d2689d | balrog | |
1286 | c3d2689d | balrog | case 0xfffed400: /* JTAG_ID_LSB */ |
1287 | c3d2689d | balrog | switch (s->mpu_model) {
|
1288 | c3d2689d | balrog | case omap310:
|
1289 | c3d2689d | balrog | return 0x03310315; |
1290 | c3d2689d | balrog | case omap1510:
|
1291 | c3d2689d | balrog | return 0x03310115; |
1292 | c3d2689d | balrog | } |
1293 | c3d2689d | balrog | break;
|
1294 | c3d2689d | balrog | |
1295 | c3d2689d | balrog | case 0xfffed404: /* JTAG_ID_MSB */ |
1296 | c3d2689d | balrog | switch (s->mpu_model) {
|
1297 | c3d2689d | balrog | case omap310:
|
1298 | c3d2689d | balrog | return 0xfb57402f; |
1299 | c3d2689d | balrog | case omap1510:
|
1300 | c3d2689d | balrog | return 0xfb47002f; |
1301 | c3d2689d | balrog | } |
1302 | c3d2689d | balrog | break;
|
1303 | c3d2689d | balrog | } |
1304 | c3d2689d | balrog | |
1305 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1306 | c3d2689d | balrog | return 0; |
1307 | c3d2689d | balrog | } |
1308 | c3d2689d | balrog | |
1309 | c3d2689d | balrog | static void omap_id_write(void *opaque, target_phys_addr_t addr, |
1310 | c3d2689d | balrog | uint32_t value) |
1311 | c3d2689d | balrog | { |
1312 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1313 | c3d2689d | balrog | } |
1314 | c3d2689d | balrog | |
1315 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_id_readfn[] = {
|
1316 | c3d2689d | balrog | omap_badwidth_read32, |
1317 | c3d2689d | balrog | omap_badwidth_read32, |
1318 | c3d2689d | balrog | omap_id_read, |
1319 | c3d2689d | balrog | }; |
1320 | c3d2689d | balrog | |
1321 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_id_writefn[] = {
|
1322 | c3d2689d | balrog | omap_badwidth_write32, |
1323 | c3d2689d | balrog | omap_badwidth_write32, |
1324 | c3d2689d | balrog | omap_id_write, |
1325 | c3d2689d | balrog | }; |
1326 | c3d2689d | balrog | |
1327 | c3d2689d | balrog | static void omap_id_init(struct omap_mpu_state_s *mpu) |
1328 | c3d2689d | balrog | { |
1329 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_id_readfn, |
1330 | c3d2689d | balrog | omap_id_writefn, mpu); |
1331 | c3d2689d | balrog | cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype); |
1332 | c3d2689d | balrog | cpu_register_physical_memory(0xfffed400, 0x100, iomemtype); |
1333 | c3d2689d | balrog | if (!cpu_is_omap15xx(mpu))
|
1334 | c3d2689d | balrog | cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype); |
1335 | c3d2689d | balrog | } |
1336 | c3d2689d | balrog | |
1337 | c3d2689d | balrog | /* MPUI Control (Dummy) */
|
1338 | c3d2689d | balrog | static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) |
1339 | c3d2689d | balrog | { |
1340 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1341 | c3d2689d | balrog | int offset = addr - s->mpui_base;
|
1342 | c3d2689d | balrog | |
1343 | c3d2689d | balrog | switch (offset) {
|
1344 | c3d2689d | balrog | case 0x00: /* CTRL */ |
1345 | c3d2689d | balrog | return s->mpui_ctrl;
|
1346 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
1347 | c3d2689d | balrog | return 0x01ffffff; |
1348 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
1349 | c3d2689d | balrog | return 0xffffffff; |
1350 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
1351 | c3d2689d | balrog | return 0x00000800; |
1352 | c3d2689d | balrog | case 0x10: /* STATUS */ |
1353 | c3d2689d | balrog | return 0x00000000; |
1354 | c3d2689d | balrog | |
1355 | c3d2689d | balrog | /* Not in OMAP310 */
|
1356 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
1357 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
1358 | c3d2689d | balrog | return 0x00000000; |
1359 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
1360 | c3d2689d | balrog | return 0x0000ffff; |
1361 | c3d2689d | balrog | } |
1362 | c3d2689d | balrog | |
1363 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1364 | c3d2689d | balrog | return 0; |
1365 | c3d2689d | balrog | } |
1366 | c3d2689d | balrog | |
1367 | c3d2689d | balrog | static void omap_mpui_write(void *opaque, target_phys_addr_t addr, |
1368 | c3d2689d | balrog | uint32_t value) |
1369 | c3d2689d | balrog | { |
1370 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1371 | c3d2689d | balrog | int offset = addr - s->mpui_base;
|
1372 | c3d2689d | balrog | |
1373 | c3d2689d | balrog | switch (offset) {
|
1374 | c3d2689d | balrog | case 0x00: /* CTRL */ |
1375 | c3d2689d | balrog | s->mpui_ctrl = value & 0x007fffff;
|
1376 | c3d2689d | balrog | break;
|
1377 | c3d2689d | balrog | |
1378 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
1379 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
1380 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
1381 | c3d2689d | balrog | case 0x10: /* STATUS */ |
1382 | c3d2689d | balrog | /* Not in OMAP310 */
|
1383 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
1384 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1385 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
1386 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
1387 | c3d2689d | balrog | break;
|
1388 | c3d2689d | balrog | |
1389 | c3d2689d | balrog | default:
|
1390 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1391 | c3d2689d | balrog | } |
1392 | c3d2689d | balrog | } |
1393 | c3d2689d | balrog | |
1394 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_mpui_readfn[] = {
|
1395 | c3d2689d | balrog | omap_badwidth_read32, |
1396 | c3d2689d | balrog | omap_badwidth_read32, |
1397 | c3d2689d | balrog | omap_mpui_read, |
1398 | c3d2689d | balrog | }; |
1399 | c3d2689d | balrog | |
1400 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
|
1401 | c3d2689d | balrog | omap_badwidth_write32, |
1402 | c3d2689d | balrog | omap_badwidth_write32, |
1403 | c3d2689d | balrog | omap_mpui_write, |
1404 | c3d2689d | balrog | }; |
1405 | c3d2689d | balrog | |
1406 | c3d2689d | balrog | static void omap_mpui_reset(struct omap_mpu_state_s *s) |
1407 | c3d2689d | balrog | { |
1408 | c3d2689d | balrog | s->mpui_ctrl = 0x0003ff1b;
|
1409 | c3d2689d | balrog | } |
1410 | c3d2689d | balrog | |
1411 | c3d2689d | balrog | static void omap_mpui_init(target_phys_addr_t base, |
1412 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1413 | c3d2689d | balrog | { |
1414 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn, |
1415 | c3d2689d | balrog | omap_mpui_writefn, mpu); |
1416 | c3d2689d | balrog | |
1417 | c3d2689d | balrog | mpu->mpui_base = base; |
1418 | c3d2689d | balrog | cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
|
1419 | c3d2689d | balrog | |
1420 | c3d2689d | balrog | omap_mpui_reset(mpu); |
1421 | c3d2689d | balrog | } |
1422 | c3d2689d | balrog | |
1423 | c3d2689d | balrog | /* TIPB Bridges */
|
1424 | c3d2689d | balrog | struct omap_tipb_bridge_s {
|
1425 | c3d2689d | balrog | target_phys_addr_t base; |
1426 | c3d2689d | balrog | qemu_irq abort; |
1427 | c3d2689d | balrog | |
1428 | c3d2689d | balrog | int width_intr;
|
1429 | c3d2689d | balrog | uint16_t control; |
1430 | c3d2689d | balrog | uint16_t alloc; |
1431 | c3d2689d | balrog | uint16_t buffer; |
1432 | c3d2689d | balrog | uint16_t enh_control; |
1433 | c3d2689d | balrog | }; |
1434 | c3d2689d | balrog | |
1435 | c3d2689d | balrog | static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) |
1436 | c3d2689d | balrog | { |
1437 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
1438 | c3d2689d | balrog | int offset = addr - s->base;
|
1439 | c3d2689d | balrog | |
1440 | c3d2689d | balrog | switch (offset) {
|
1441 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
1442 | c3d2689d | balrog | return s->control;
|
1443 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
1444 | c3d2689d | balrog | return s->alloc;
|
1445 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
1446 | c3d2689d | balrog | return s->buffer;
|
1447 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
1448 | c3d2689d | balrog | return s->enh_control;
|
1449 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
1450 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
1451 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
1452 | c3d2689d | balrog | return 0xffff; |
1453 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
1454 | c3d2689d | balrog | return 0x00f8; |
1455 | c3d2689d | balrog | } |
1456 | c3d2689d | balrog | |
1457 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1458 | c3d2689d | balrog | return 0; |
1459 | c3d2689d | balrog | } |
1460 | c3d2689d | balrog | |
1461 | c3d2689d | balrog | static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, |
1462 | c3d2689d | balrog | uint32_t value) |
1463 | c3d2689d | balrog | { |
1464 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
1465 | c3d2689d | balrog | int offset = addr - s->base;
|
1466 | c3d2689d | balrog | |
1467 | c3d2689d | balrog | switch (offset) {
|
1468 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
1469 | c3d2689d | balrog | s->control = value & 0xffff;
|
1470 | c3d2689d | balrog | break;
|
1471 | c3d2689d | balrog | |
1472 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
1473 | c3d2689d | balrog | s->alloc = value & 0x003f;
|
1474 | c3d2689d | balrog | break;
|
1475 | c3d2689d | balrog | |
1476 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
1477 | c3d2689d | balrog | s->buffer = value & 0x0003;
|
1478 | c3d2689d | balrog | break;
|
1479 | c3d2689d | balrog | |
1480 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
1481 | c3d2689d | balrog | s->width_intr = !(value & 2);
|
1482 | c3d2689d | balrog | s->enh_control = value & 0x000f;
|
1483 | c3d2689d | balrog | break;
|
1484 | c3d2689d | balrog | |
1485 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
1486 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
1487 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
1488 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
1489 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1490 | c3d2689d | balrog | break;
|
1491 | c3d2689d | balrog | |
1492 | c3d2689d | balrog | default:
|
1493 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1494 | c3d2689d | balrog | } |
1495 | c3d2689d | balrog | } |
1496 | c3d2689d | balrog | |
1497 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
|
1498 | c3d2689d | balrog | omap_badwidth_read16, |
1499 | c3d2689d | balrog | omap_tipb_bridge_read, |
1500 | c3d2689d | balrog | omap_tipb_bridge_read, |
1501 | c3d2689d | balrog | }; |
1502 | c3d2689d | balrog | |
1503 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
|
1504 | c3d2689d | balrog | omap_badwidth_write16, |
1505 | c3d2689d | balrog | omap_tipb_bridge_write, |
1506 | c3d2689d | balrog | omap_tipb_bridge_write, |
1507 | c3d2689d | balrog | }; |
1508 | c3d2689d | balrog | |
1509 | c3d2689d | balrog | static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) |
1510 | c3d2689d | balrog | { |
1511 | c3d2689d | balrog | s->control = 0xffff;
|
1512 | c3d2689d | balrog | s->alloc = 0x0009;
|
1513 | c3d2689d | balrog | s->buffer = 0x0000;
|
1514 | c3d2689d | balrog | s->enh_control = 0x000f;
|
1515 | c3d2689d | balrog | } |
1516 | c3d2689d | balrog | |
1517 | c3d2689d | balrog | struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
|
1518 | c3d2689d | balrog | qemu_irq abort_irq, omap_clk clk) |
1519 | c3d2689d | balrog | { |
1520 | c3d2689d | balrog | int iomemtype;
|
1521 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) |
1522 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_tipb_bridge_s)); |
1523 | c3d2689d | balrog | |
1524 | c3d2689d | balrog | s->abort = abort_irq; |
1525 | c3d2689d | balrog | s->base = base; |
1526 | c3d2689d | balrog | omap_tipb_bridge_reset(s); |
1527 | c3d2689d | balrog | |
1528 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
|
1529 | c3d2689d | balrog | omap_tipb_bridge_writefn, s); |
1530 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
1531 | c3d2689d | balrog | |
1532 | c3d2689d | balrog | return s;
|
1533 | c3d2689d | balrog | } |
1534 | c3d2689d | balrog | |
1535 | c3d2689d | balrog | /* Dummy Traffic Controller's Memory Interface */
|
1536 | c3d2689d | balrog | static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) |
1537 | c3d2689d | balrog | { |
1538 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1539 | c3d2689d | balrog | int offset = addr - s->tcmi_base;
|
1540 | c3d2689d | balrog | uint32_t ret; |
1541 | c3d2689d | balrog | |
1542 | c3d2689d | balrog | switch (offset) {
|
1543 | d8f699cb | balrog | case 0x00: /* IMIF_PRIO */ |
1544 | d8f699cb | balrog | case 0x04: /* EMIFS_PRIO */ |
1545 | d8f699cb | balrog | case 0x08: /* EMIFF_PRIO */ |
1546 | d8f699cb | balrog | case 0x0c: /* EMIFS_CONFIG */ |
1547 | d8f699cb | balrog | case 0x10: /* EMIFS_CS0_CONFIG */ |
1548 | d8f699cb | balrog | case 0x14: /* EMIFS_CS1_CONFIG */ |
1549 | d8f699cb | balrog | case 0x18: /* EMIFS_CS2_CONFIG */ |
1550 | d8f699cb | balrog | case 0x1c: /* EMIFS_CS3_CONFIG */ |
1551 | d8f699cb | balrog | case 0x24: /* EMIFF_MRS */ |
1552 | d8f699cb | balrog | case 0x28: /* TIMEOUT1 */ |
1553 | d8f699cb | balrog | case 0x2c: /* TIMEOUT2 */ |
1554 | d8f699cb | balrog | case 0x30: /* TIMEOUT3 */ |
1555 | d8f699cb | balrog | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
1556 | d8f699cb | balrog | case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
1557 | c3d2689d | balrog | return s->tcmi_regs[offset >> 2]; |
1558 | c3d2689d | balrog | |
1559 | d8f699cb | balrog | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
1560 | c3d2689d | balrog | ret = s->tcmi_regs[offset >> 2];
|
1561 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ |
1562 | c3d2689d | balrog | /* XXX: We can try using the VGA_DIRTY flag for this */
|
1563 | c3d2689d | balrog | return ret;
|
1564 | c3d2689d | balrog | } |
1565 | c3d2689d | balrog | |
1566 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1567 | c3d2689d | balrog | return 0; |
1568 | c3d2689d | balrog | } |
1569 | c3d2689d | balrog | |
1570 | c3d2689d | balrog | static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, |
1571 | c3d2689d | balrog | uint32_t value) |
1572 | c3d2689d | balrog | { |
1573 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1574 | c3d2689d | balrog | int offset = addr - s->tcmi_base;
|
1575 | c3d2689d | balrog | |
1576 | c3d2689d | balrog | switch (offset) {
|
1577 | d8f699cb | balrog | case 0x00: /* IMIF_PRIO */ |
1578 | d8f699cb | balrog | case 0x04: /* EMIFS_PRIO */ |
1579 | d8f699cb | balrog | case 0x08: /* EMIFF_PRIO */ |
1580 | d8f699cb | balrog | case 0x10: /* EMIFS_CS0_CONFIG */ |
1581 | d8f699cb | balrog | case 0x14: /* EMIFS_CS1_CONFIG */ |
1582 | d8f699cb | balrog | case 0x18: /* EMIFS_CS2_CONFIG */ |
1583 | d8f699cb | balrog | case 0x1c: /* EMIFS_CS3_CONFIG */ |
1584 | d8f699cb | balrog | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
1585 | d8f699cb | balrog | case 0x24: /* EMIFF_MRS */ |
1586 | d8f699cb | balrog | case 0x28: /* TIMEOUT1 */ |
1587 | d8f699cb | balrog | case 0x2c: /* TIMEOUT2 */ |
1588 | d8f699cb | balrog | case 0x30: /* TIMEOUT3 */ |
1589 | d8f699cb | balrog | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
1590 | d8f699cb | balrog | case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
1591 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] = value;
|
1592 | c3d2689d | balrog | break;
|
1593 | d8f699cb | balrog | case 0x0c: /* EMIFS_CONFIG */ |
1594 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4); |
1595 | c3d2689d | balrog | break;
|
1596 | c3d2689d | balrog | |
1597 | c3d2689d | balrog | default:
|
1598 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1599 | c3d2689d | balrog | } |
1600 | c3d2689d | balrog | } |
1601 | c3d2689d | balrog | |
1602 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
|
1603 | c3d2689d | balrog | omap_badwidth_read32, |
1604 | c3d2689d | balrog | omap_badwidth_read32, |
1605 | c3d2689d | balrog | omap_tcmi_read, |
1606 | c3d2689d | balrog | }; |
1607 | c3d2689d | balrog | |
1608 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
|
1609 | c3d2689d | balrog | omap_badwidth_write32, |
1610 | c3d2689d | balrog | omap_badwidth_write32, |
1611 | c3d2689d | balrog | omap_tcmi_write, |
1612 | c3d2689d | balrog | }; |
1613 | c3d2689d | balrog | |
1614 | c3d2689d | balrog | static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) |
1615 | c3d2689d | balrog | { |
1616 | c3d2689d | balrog | mpu->tcmi_regs[0x00 >> 2] = 0x00000000; |
1617 | c3d2689d | balrog | mpu->tcmi_regs[0x04 >> 2] = 0x00000000; |
1618 | c3d2689d | balrog | mpu->tcmi_regs[0x08 >> 2] = 0x00000000; |
1619 | c3d2689d | balrog | mpu->tcmi_regs[0x0c >> 2] = 0x00000010; |
1620 | c3d2689d | balrog | mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; |
1621 | c3d2689d | balrog | mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; |
1622 | c3d2689d | balrog | mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; |
1623 | c3d2689d | balrog | mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; |
1624 | c3d2689d | balrog | mpu->tcmi_regs[0x20 >> 2] = 0x00618800; |
1625 | c3d2689d | balrog | mpu->tcmi_regs[0x24 >> 2] = 0x00000037; |
1626 | c3d2689d | balrog | mpu->tcmi_regs[0x28 >> 2] = 0x00000000; |
1627 | c3d2689d | balrog | mpu->tcmi_regs[0x2c >> 2] = 0x00000000; |
1628 | c3d2689d | balrog | mpu->tcmi_regs[0x30 >> 2] = 0x00000000; |
1629 | c3d2689d | balrog | mpu->tcmi_regs[0x3c >> 2] = 0x00000003; |
1630 | c3d2689d | balrog | mpu->tcmi_regs[0x40 >> 2] = 0x00000000; |
1631 | c3d2689d | balrog | } |
1632 | c3d2689d | balrog | |
1633 | c3d2689d | balrog | static void omap_tcmi_init(target_phys_addr_t base, |
1634 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1635 | c3d2689d | balrog | { |
1636 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn, |
1637 | c3d2689d | balrog | omap_tcmi_writefn, mpu); |
1638 | c3d2689d | balrog | |
1639 | c3d2689d | balrog | mpu->tcmi_base = base; |
1640 | c3d2689d | balrog | cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
|
1641 | c3d2689d | balrog | omap_tcmi_reset(mpu); |
1642 | c3d2689d | balrog | } |
1643 | c3d2689d | balrog | |
1644 | c3d2689d | balrog | /* Digital phase-locked loops control */
|
1645 | c3d2689d | balrog | static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr) |
1646 | c3d2689d | balrog | { |
1647 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
1648 | c3d2689d | balrog | int offset = addr - s->base;
|
1649 | c3d2689d | balrog | |
1650 | c3d2689d | balrog | if (offset == 0x00) /* CTL_REG */ |
1651 | c3d2689d | balrog | return s->mode;
|
1652 | c3d2689d | balrog | |
1653 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1654 | c3d2689d | balrog | return 0; |
1655 | c3d2689d | balrog | } |
1656 | c3d2689d | balrog | |
1657 | c3d2689d | balrog | static void omap_dpll_write(void *opaque, target_phys_addr_t addr, |
1658 | c3d2689d | balrog | uint32_t value) |
1659 | c3d2689d | balrog | { |
1660 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
1661 | c3d2689d | balrog | uint16_t diff; |
1662 | c3d2689d | balrog | int offset = addr - s->base;
|
1663 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
1664 | c3d2689d | balrog | int div, mult;
|
1665 | c3d2689d | balrog | |
1666 | c3d2689d | balrog | if (offset == 0x00) { /* CTL_REG */ |
1667 | c3d2689d | balrog | /* See omap_ulpd_pm_write() too */
|
1668 | c3d2689d | balrog | diff = s->mode & value; |
1669 | c3d2689d | balrog | s->mode = value & 0x2fff;
|
1670 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
1671 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
1672 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
1673 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
1674 | c3d2689d | balrog | } else {
|
1675 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
1676 | c3d2689d | balrog | mult = 1;
|
1677 | c3d2689d | balrog | } |
1678 | c3d2689d | balrog | omap_clk_setrate(s->dpll, div, mult); |
1679 | c3d2689d | balrog | } |
1680 | c3d2689d | balrog | |
1681 | c3d2689d | balrog | /* Enter the desired mode. */
|
1682 | c3d2689d | balrog | s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); |
1683 | c3d2689d | balrog | |
1684 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
1685 | c3d2689d | balrog | s->mode |= 2;
|
1686 | c3d2689d | balrog | } else {
|
1687 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1688 | c3d2689d | balrog | } |
1689 | c3d2689d | balrog | } |
1690 | c3d2689d | balrog | |
1691 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_dpll_readfn[] = {
|
1692 | c3d2689d | balrog | omap_badwidth_read16, |
1693 | c3d2689d | balrog | omap_dpll_read, |
1694 | c3d2689d | balrog | omap_badwidth_read16, |
1695 | c3d2689d | balrog | }; |
1696 | c3d2689d | balrog | |
1697 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
|
1698 | c3d2689d | balrog | omap_badwidth_write16, |
1699 | c3d2689d | balrog | omap_dpll_write, |
1700 | c3d2689d | balrog | omap_badwidth_write16, |
1701 | c3d2689d | balrog | }; |
1702 | c3d2689d | balrog | |
1703 | c3d2689d | balrog | static void omap_dpll_reset(struct dpll_ctl_s *s) |
1704 | c3d2689d | balrog | { |
1705 | c3d2689d | balrog | s->mode = 0x2002;
|
1706 | c3d2689d | balrog | omap_clk_setrate(s->dpll, 1, 1); |
1707 | c3d2689d | balrog | } |
1708 | c3d2689d | balrog | |
1709 | c3d2689d | balrog | static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base, |
1710 | c3d2689d | balrog | omap_clk clk) |
1711 | c3d2689d | balrog | { |
1712 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn, |
1713 | c3d2689d | balrog | omap_dpll_writefn, s); |
1714 | c3d2689d | balrog | |
1715 | c3d2689d | balrog | s->base = base; |
1716 | c3d2689d | balrog | s->dpll = clk; |
1717 | c3d2689d | balrog | omap_dpll_reset(s); |
1718 | c3d2689d | balrog | |
1719 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
1720 | c3d2689d | balrog | } |
1721 | c3d2689d | balrog | |
1722 | c3d2689d | balrog | /* UARTs */
|
1723 | c3d2689d | balrog | struct omap_uart_s {
|
1724 | c3d2689d | balrog | SerialState *serial; /* TODO */
|
1725 | c3d2689d | balrog | }; |
1726 | c3d2689d | balrog | |
1727 | c3d2689d | balrog | static void omap_uart_reset(struct omap_uart_s *s) |
1728 | c3d2689d | balrog | { |
1729 | c3d2689d | balrog | } |
1730 | c3d2689d | balrog | |
1731 | c3d2689d | balrog | struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
1732 | c3d2689d | balrog | qemu_irq irq, omap_clk clk, CharDriverState *chr) |
1733 | c3d2689d | balrog | { |
1734 | c3d2689d | balrog | struct omap_uart_s *s = (struct omap_uart_s *) |
1735 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_uart_s)); |
1736 | c3d2689d | balrog | if (chr)
|
1737 | c3d2689d | balrog | s->serial = serial_mm_init(base, 2, irq, chr, 1); |
1738 | c3d2689d | balrog | return s;
|
1739 | c3d2689d | balrog | } |
1740 | c3d2689d | balrog | |
1741 | c3d2689d | balrog | /* MPU Clock/Reset/Power Mode Control */
|
1742 | c3d2689d | balrog | static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr) |
1743 | c3d2689d | balrog | { |
1744 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1745 | c3d2689d | balrog | int offset = addr - s->clkm.mpu_base;
|
1746 | c3d2689d | balrog | |
1747 | c3d2689d | balrog | switch (offset) {
|
1748 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
1749 | c3d2689d | balrog | return s->clkm.arm_ckctl;
|
1750 | c3d2689d | balrog | |
1751 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
1752 | c3d2689d | balrog | return s->clkm.arm_idlect1;
|
1753 | c3d2689d | balrog | |
1754 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
1755 | c3d2689d | balrog | return s->clkm.arm_idlect2;
|
1756 | c3d2689d | balrog | |
1757 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
1758 | c3d2689d | balrog | return s->clkm.arm_ewupct;
|
1759 | c3d2689d | balrog | |
1760 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
1761 | c3d2689d | balrog | return s->clkm.arm_rstct1;
|
1762 | c3d2689d | balrog | |
1763 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
1764 | c3d2689d | balrog | return s->clkm.arm_rstct2;
|
1765 | c3d2689d | balrog | |
1766 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
1767 | d8f699cb | balrog | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; |
1768 | c3d2689d | balrog | |
1769 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
1770 | c3d2689d | balrog | return s->clkm.arm_ckout1;
|
1771 | c3d2689d | balrog | |
1772 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
1773 | c3d2689d | balrog | break;
|
1774 | c3d2689d | balrog | } |
1775 | c3d2689d | balrog | |
1776 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1777 | c3d2689d | balrog | return 0; |
1778 | c3d2689d | balrog | } |
1779 | c3d2689d | balrog | |
1780 | c3d2689d | balrog | static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, |
1781 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1782 | c3d2689d | balrog | { |
1783 | c3d2689d | balrog | omap_clk clk; |
1784 | c3d2689d | balrog | |
1785 | c3d2689d | balrog | if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ |
1786 | c3d2689d | balrog | if (value & (1 << 14)) |
1787 | c3d2689d | balrog | /* Reserved */;
|
1788 | c3d2689d | balrog | else {
|
1789 | c3d2689d | balrog | clk = omap_findclk(s, "arminth_ck");
|
1790 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
1791 | c3d2689d | balrog | } |
1792 | c3d2689d | balrog | } |
1793 | c3d2689d | balrog | if (diff & (1 << 12)) { /* ARM_TIMXO */ |
1794 | c3d2689d | balrog | clk = omap_findclk(s, "armtim_ck");
|
1795 | c3d2689d | balrog | if (value & (1 << 12)) |
1796 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "clkin"));
|
1797 | c3d2689d | balrog | else
|
1798 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
1799 | c3d2689d | balrog | } |
1800 | c3d2689d | balrog | /* XXX: en_dspck */
|
1801 | c3d2689d | balrog | if (diff & (3 << 10)) { /* DSPMMUDIV */ |
1802 | c3d2689d | balrog | clk = omap_findclk(s, "dspmmu_ck");
|
1803 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); |
1804 | c3d2689d | balrog | } |
1805 | c3d2689d | balrog | if (diff & (3 << 8)) { /* TCDIV */ |
1806 | c3d2689d | balrog | clk = omap_findclk(s, "tc_ck");
|
1807 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); |
1808 | c3d2689d | balrog | } |
1809 | c3d2689d | balrog | if (diff & (3 << 6)) { /* DSPDIV */ |
1810 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
1811 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); |
1812 | c3d2689d | balrog | } |
1813 | c3d2689d | balrog | if (diff & (3 << 4)) { /* ARMDIV */ |
1814 | c3d2689d | balrog | clk = omap_findclk(s, "arm_ck");
|
1815 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); |
1816 | c3d2689d | balrog | } |
1817 | c3d2689d | balrog | if (diff & (3 << 2)) { /* LCDDIV */ |
1818 | c3d2689d | balrog | clk = omap_findclk(s, "lcd_ck");
|
1819 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); |
1820 | c3d2689d | balrog | } |
1821 | c3d2689d | balrog | if (diff & (3 << 0)) { /* PERDIV */ |
1822 | c3d2689d | balrog | clk = omap_findclk(s, "armper_ck");
|
1823 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); |
1824 | c3d2689d | balrog | } |
1825 | c3d2689d | balrog | } |
1826 | c3d2689d | balrog | |
1827 | c3d2689d | balrog | static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, |
1828 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1829 | c3d2689d | balrog | { |
1830 | c3d2689d | balrog | omap_clk clk; |
1831 | c3d2689d | balrog | |
1832 | c3d2689d | balrog | if (value & (1 << 11)) /* SETARM_IDLE */ |
1833 | c3d2689d | balrog | cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
1834 | c3d2689d | balrog | if (!(value & (1 << 10))) /* WKUP_MODE */ |
1835 | c3d2689d | balrog | qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
|
1836 | c3d2689d | balrog | |
1837 | c3d2689d | balrog | #define SET_CANIDLE(clock, bit) \
|
1838 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
1839 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
1840 | c3d2689d | balrog | omap_clk_canidle(clk, (value >> bit) & 1); \
|
1841 | c3d2689d | balrog | } |
1842 | c3d2689d | balrog | SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ |
1843 | c3d2689d | balrog | SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ |
1844 | c3d2689d | balrog | SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ |
1845 | c3d2689d | balrog | SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ |
1846 | c3d2689d | balrog | SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ |
1847 | c3d2689d | balrog | SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ |
1848 | c3d2689d | balrog | SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ |
1849 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ |
1850 | c3d2689d | balrog | SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ |
1851 | c3d2689d | balrog | SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ |
1852 | c3d2689d | balrog | SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ |
1853 | c3d2689d | balrog | SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ |
1854 | c3d2689d | balrog | SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ |
1855 | c3d2689d | balrog | SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ |
1856 | c3d2689d | balrog | } |
1857 | c3d2689d | balrog | |
1858 | c3d2689d | balrog | static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, |
1859 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1860 | c3d2689d | balrog | { |
1861 | c3d2689d | balrog | omap_clk clk; |
1862 | c3d2689d | balrog | |
1863 | c3d2689d | balrog | #define SET_ONOFF(clock, bit) \
|
1864 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
1865 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
1866 | c3d2689d | balrog | omap_clk_onoff(clk, (value >> bit) & 1); \
|
1867 | c3d2689d | balrog | } |
1868 | c3d2689d | balrog | SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ |
1869 | c3d2689d | balrog | SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ |
1870 | c3d2689d | balrog | SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ |
1871 | c3d2689d | balrog | SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ |
1872 | c3d2689d | balrog | SET_ONOFF("lb_ck", 4) /* EN_LBCK */ |
1873 | c3d2689d | balrog | SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ |
1874 | c3d2689d | balrog | SET_ONOFF("mpui_ck", 6) /* EN_APICK */ |
1875 | c3d2689d | balrog | SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ |
1876 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ |
1877 | c3d2689d | balrog | SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ |
1878 | c3d2689d | balrog | SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ |
1879 | c3d2689d | balrog | } |
1880 | c3d2689d | balrog | |
1881 | c3d2689d | balrog | static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, |
1882 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1883 | c3d2689d | balrog | { |
1884 | c3d2689d | balrog | omap_clk clk; |
1885 | c3d2689d | balrog | |
1886 | c3d2689d | balrog | if (diff & (3 << 4)) { /* TCLKOUT */ |
1887 | c3d2689d | balrog | clk = omap_findclk(s, "tclk_out");
|
1888 | c3d2689d | balrog | switch ((value >> 4) & 3) { |
1889 | c3d2689d | balrog | case 1: |
1890 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
|
1891 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1892 | c3d2689d | balrog | break;
|
1893 | c3d2689d | balrog | case 2: |
1894 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
1895 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1896 | c3d2689d | balrog | break;
|
1897 | c3d2689d | balrog | default:
|
1898 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
1899 | c3d2689d | balrog | } |
1900 | c3d2689d | balrog | } |
1901 | c3d2689d | balrog | if (diff & (3 << 2)) { /* DCLKOUT */ |
1902 | c3d2689d | balrog | clk = omap_findclk(s, "dclk_out");
|
1903 | c3d2689d | balrog | switch ((value >> 2) & 3) { |
1904 | c3d2689d | balrog | case 0: |
1905 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
|
1906 | c3d2689d | balrog | break;
|
1907 | c3d2689d | balrog | case 1: |
1908 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
|
1909 | c3d2689d | balrog | break;
|
1910 | c3d2689d | balrog | case 2: |
1911 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
|
1912 | c3d2689d | balrog | break;
|
1913 | c3d2689d | balrog | case 3: |
1914 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
1915 | c3d2689d | balrog | break;
|
1916 | c3d2689d | balrog | } |
1917 | c3d2689d | balrog | } |
1918 | c3d2689d | balrog | if (diff & (3 << 0)) { /* ACLKOUT */ |
1919 | c3d2689d | balrog | clk = omap_findclk(s, "aclk_out");
|
1920 | c3d2689d | balrog | switch ((value >> 0) & 3) { |
1921 | c3d2689d | balrog | case 1: |
1922 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
1923 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1924 | c3d2689d | balrog | break;
|
1925 | c3d2689d | balrog | case 2: |
1926 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
|
1927 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1928 | c3d2689d | balrog | break;
|
1929 | c3d2689d | balrog | case 3: |
1930 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
1931 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1932 | c3d2689d | balrog | break;
|
1933 | c3d2689d | balrog | default:
|
1934 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
1935 | c3d2689d | balrog | } |
1936 | c3d2689d | balrog | } |
1937 | c3d2689d | balrog | } |
1938 | c3d2689d | balrog | |
1939 | c3d2689d | balrog | static void omap_clkm_write(void *opaque, target_phys_addr_t addr, |
1940 | c3d2689d | balrog | uint32_t value) |
1941 | c3d2689d | balrog | { |
1942 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1943 | c3d2689d | balrog | int offset = addr - s->clkm.mpu_base;
|
1944 | c3d2689d | balrog | uint16_t diff; |
1945 | c3d2689d | balrog | omap_clk clk; |
1946 | c3d2689d | balrog | static const char *clkschemename[8] = { |
1947 | c3d2689d | balrog | "fully synchronous", "fully asynchronous", "synchronous scalable", |
1948 | c3d2689d | balrog | "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", |
1949 | c3d2689d | balrog | }; |
1950 | c3d2689d | balrog | |
1951 | c3d2689d | balrog | switch (offset) {
|
1952 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
1953 | c3d2689d | balrog | diff = s->clkm.arm_ckctl ^ value; |
1954 | c3d2689d | balrog | s->clkm.arm_ckctl = value & 0x7fff;
|
1955 | c3d2689d | balrog | omap_clkm_ckctl_update(s, diff, value); |
1956 | c3d2689d | balrog | return;
|
1957 | c3d2689d | balrog | |
1958 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
1959 | c3d2689d | balrog | diff = s->clkm.arm_idlect1 ^ value; |
1960 | c3d2689d | balrog | s->clkm.arm_idlect1 = value & 0x0fff;
|
1961 | c3d2689d | balrog | omap_clkm_idlect1_update(s, diff, value); |
1962 | c3d2689d | balrog | return;
|
1963 | c3d2689d | balrog | |
1964 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
1965 | c3d2689d | balrog | diff = s->clkm.arm_idlect2 ^ value; |
1966 | c3d2689d | balrog | s->clkm.arm_idlect2 = value & 0x07ff;
|
1967 | c3d2689d | balrog | omap_clkm_idlect2_update(s, diff, value); |
1968 | c3d2689d | balrog | return;
|
1969 | c3d2689d | balrog | |
1970 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
1971 | c3d2689d | balrog | diff = s->clkm.arm_ewupct ^ value; |
1972 | c3d2689d | balrog | s->clkm.arm_ewupct = value & 0x003f;
|
1973 | c3d2689d | balrog | return;
|
1974 | c3d2689d | balrog | |
1975 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
1976 | c3d2689d | balrog | diff = s->clkm.arm_rstct1 ^ value; |
1977 | c3d2689d | balrog | s->clkm.arm_rstct1 = value & 0x0007;
|
1978 | c3d2689d | balrog | if (value & 9) { |
1979 | c3d2689d | balrog | qemu_system_reset_request(); |
1980 | c3d2689d | balrog | s->clkm.cold_start = 0xa;
|
1981 | c3d2689d | balrog | } |
1982 | c3d2689d | balrog | if (diff & ~value & 4) { /* DSP_RST */ |
1983 | c3d2689d | balrog | omap_mpui_reset(s); |
1984 | c3d2689d | balrog | omap_tipb_bridge_reset(s->private_tipb); |
1985 | c3d2689d | balrog | omap_tipb_bridge_reset(s->public_tipb); |
1986 | c3d2689d | balrog | } |
1987 | c3d2689d | balrog | if (diff & 2) { /* DSP_EN */ |
1988 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
1989 | c3d2689d | balrog | omap_clk_canidle(clk, (~value >> 1) & 1); |
1990 | c3d2689d | balrog | } |
1991 | c3d2689d | balrog | return;
|
1992 | c3d2689d | balrog | |
1993 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
1994 | c3d2689d | balrog | s->clkm.arm_rstct2 = value & 0x0001;
|
1995 | c3d2689d | balrog | return;
|
1996 | c3d2689d | balrog | |
1997 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
1998 | c3d2689d | balrog | if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { |
1999 | c3d2689d | balrog | s->clkm.clocking_scheme = (value >> 11) & 7; |
2000 | c3d2689d | balrog | printf("%s: clocking scheme set to %s\n", __FUNCTION__,
|
2001 | c3d2689d | balrog | clkschemename[s->clkm.clocking_scheme]); |
2002 | c3d2689d | balrog | } |
2003 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
2004 | c3d2689d | balrog | return;
|
2005 | c3d2689d | balrog | |
2006 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
2007 | c3d2689d | balrog | diff = s->clkm.arm_ckout1 ^ value; |
2008 | c3d2689d | balrog | s->clkm.arm_ckout1 = value & 0x003f;
|
2009 | c3d2689d | balrog | omap_clkm_ckout1_update(s, diff, value); |
2010 | c3d2689d | balrog | return;
|
2011 | c3d2689d | balrog | |
2012 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
2013 | c3d2689d | balrog | default:
|
2014 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2015 | c3d2689d | balrog | } |
2016 | c3d2689d | balrog | } |
2017 | c3d2689d | balrog | |
2018 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_clkm_readfn[] = {
|
2019 | c3d2689d | balrog | omap_badwidth_read16, |
2020 | c3d2689d | balrog | omap_clkm_read, |
2021 | c3d2689d | balrog | omap_badwidth_read16, |
2022 | c3d2689d | balrog | }; |
2023 | c3d2689d | balrog | |
2024 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
|
2025 | c3d2689d | balrog | omap_badwidth_write16, |
2026 | c3d2689d | balrog | omap_clkm_write, |
2027 | c3d2689d | balrog | omap_badwidth_write16, |
2028 | c3d2689d | balrog | }; |
2029 | c3d2689d | balrog | |
2030 | c3d2689d | balrog | static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr) |
2031 | c3d2689d | balrog | { |
2032 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2033 | c3d2689d | balrog | int offset = addr - s->clkm.dsp_base;
|
2034 | c3d2689d | balrog | |
2035 | c3d2689d | balrog | switch (offset) {
|
2036 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
2037 | c3d2689d | balrog | return s->clkm.dsp_idlect1;
|
2038 | c3d2689d | balrog | |
2039 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
2040 | c3d2689d | balrog | return s->clkm.dsp_idlect2;
|
2041 | c3d2689d | balrog | |
2042 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
2043 | c3d2689d | balrog | return s->clkm.dsp_rstct2;
|
2044 | c3d2689d | balrog | |
2045 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
2046 | d8f699cb | balrog | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | |
2047 | c3d2689d | balrog | (s->env->halted << 6); /* Quite useless... */ |
2048 | c3d2689d | balrog | } |
2049 | c3d2689d | balrog | |
2050 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2051 | c3d2689d | balrog | return 0; |
2052 | c3d2689d | balrog | } |
2053 | c3d2689d | balrog | |
2054 | c3d2689d | balrog | static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, |
2055 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2056 | c3d2689d | balrog | { |
2057 | c3d2689d | balrog | omap_clk clk; |
2058 | c3d2689d | balrog | |
2059 | c3d2689d | balrog | SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ |
2060 | c3d2689d | balrog | } |
2061 | c3d2689d | balrog | |
2062 | c3d2689d | balrog | static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, |
2063 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2064 | c3d2689d | balrog | { |
2065 | c3d2689d | balrog | omap_clk clk; |
2066 | c3d2689d | balrog | |
2067 | c3d2689d | balrog | SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ |
2068 | c3d2689d | balrog | } |
2069 | c3d2689d | balrog | |
2070 | c3d2689d | balrog | static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, |
2071 | c3d2689d | balrog | uint32_t value) |
2072 | c3d2689d | balrog | { |
2073 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2074 | c3d2689d | balrog | int offset = addr - s->clkm.dsp_base;
|
2075 | c3d2689d | balrog | uint16_t diff; |
2076 | c3d2689d | balrog | |
2077 | c3d2689d | balrog | switch (offset) {
|
2078 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
2079 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
2080 | c3d2689d | balrog | s->clkm.dsp_idlect1 = value & 0x01f7;
|
2081 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, diff, value); |
2082 | c3d2689d | balrog | break;
|
2083 | c3d2689d | balrog | |
2084 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
2085 | c3d2689d | balrog | s->clkm.dsp_idlect2 = value & 0x0037;
|
2086 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
2087 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, diff, value); |
2088 | c3d2689d | balrog | break;
|
2089 | c3d2689d | balrog | |
2090 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
2091 | c3d2689d | balrog | s->clkm.dsp_rstct2 = value & 0x0001;
|
2092 | c3d2689d | balrog | break;
|
2093 | c3d2689d | balrog | |
2094 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
2095 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
2096 | c3d2689d | balrog | break;
|
2097 | c3d2689d | balrog | |
2098 | c3d2689d | balrog | default:
|
2099 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2100 | c3d2689d | balrog | } |
2101 | c3d2689d | balrog | } |
2102 | c3d2689d | balrog | |
2103 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
|
2104 | c3d2689d | balrog | omap_badwidth_read16, |
2105 | c3d2689d | balrog | omap_clkdsp_read, |
2106 | c3d2689d | balrog | omap_badwidth_read16, |
2107 | c3d2689d | balrog | }; |
2108 | c3d2689d | balrog | |
2109 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
|
2110 | c3d2689d | balrog | omap_badwidth_write16, |
2111 | c3d2689d | balrog | omap_clkdsp_write, |
2112 | c3d2689d | balrog | omap_badwidth_write16, |
2113 | c3d2689d | balrog | }; |
2114 | c3d2689d | balrog | |
2115 | c3d2689d | balrog | static void omap_clkm_reset(struct omap_mpu_state_s *s) |
2116 | c3d2689d | balrog | { |
2117 | c3d2689d | balrog | if (s->wdt && s->wdt->reset)
|
2118 | c3d2689d | balrog | s->clkm.cold_start = 0x6;
|
2119 | c3d2689d | balrog | s->clkm.clocking_scheme = 0;
|
2120 | c3d2689d | balrog | omap_clkm_ckctl_update(s, ~0, 0x3000); |
2121 | c3d2689d | balrog | s->clkm.arm_ckctl = 0x3000;
|
2122 | d8f699cb | balrog | omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); |
2123 | c3d2689d | balrog | s->clkm.arm_idlect1 = 0x0400;
|
2124 | d8f699cb | balrog | omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); |
2125 | c3d2689d | balrog | s->clkm.arm_idlect2 = 0x0100;
|
2126 | c3d2689d | balrog | s->clkm.arm_ewupct = 0x003f;
|
2127 | c3d2689d | balrog | s->clkm.arm_rstct1 = 0x0000;
|
2128 | c3d2689d | balrog | s->clkm.arm_rstct2 = 0x0000;
|
2129 | c3d2689d | balrog | s->clkm.arm_ckout1 = 0x0015;
|
2130 | c3d2689d | balrog | s->clkm.dpll1_mode = 0x2002;
|
2131 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); |
2132 | c3d2689d | balrog | s->clkm.dsp_idlect1 = 0x0040;
|
2133 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, ~0, 0x0000); |
2134 | c3d2689d | balrog | s->clkm.dsp_idlect2 = 0x0000;
|
2135 | c3d2689d | balrog | s->clkm.dsp_rstct2 = 0x0000;
|
2136 | c3d2689d | balrog | } |
2137 | c3d2689d | balrog | |
2138 | c3d2689d | balrog | static void omap_clkm_init(target_phys_addr_t mpu_base, |
2139 | c3d2689d | balrog | target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
|
2140 | c3d2689d | balrog | { |
2141 | c3d2689d | balrog | int iomemtype[2] = { |
2142 | c3d2689d | balrog | cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
|
2143 | c3d2689d | balrog | cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
|
2144 | c3d2689d | balrog | }; |
2145 | c3d2689d | balrog | |
2146 | c3d2689d | balrog | s->clkm.mpu_base = mpu_base; |
2147 | c3d2689d | balrog | s->clkm.dsp_base = dsp_base; |
2148 | d8f699cb | balrog | s->clkm.arm_idlect1 = 0x03ff;
|
2149 | d8f699cb | balrog | s->clkm.arm_idlect2 = 0x0100;
|
2150 | d8f699cb | balrog | s->clkm.dsp_idlect1 = 0x0002;
|
2151 | c3d2689d | balrog | omap_clkm_reset(s); |
2152 | d8f699cb | balrog | s->clkm.cold_start = 0x3a;
|
2153 | c3d2689d | balrog | |
2154 | c3d2689d | balrog | cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]); |
2155 | c3d2689d | balrog | cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]); |
2156 | c3d2689d | balrog | } |
2157 | c3d2689d | balrog | |
2158 | fe71e81a | balrog | /* MPU I/O */
|
2159 | fe71e81a | balrog | struct omap_mpuio_s {
|
2160 | fe71e81a | balrog | target_phys_addr_t base; |
2161 | fe71e81a | balrog | qemu_irq irq; |
2162 | fe71e81a | balrog | qemu_irq kbd_irq; |
2163 | fe71e81a | balrog | qemu_irq *in; |
2164 | fe71e81a | balrog | qemu_irq handler[16];
|
2165 | fe71e81a | balrog | qemu_irq wakeup; |
2166 | fe71e81a | balrog | |
2167 | fe71e81a | balrog | uint16_t inputs; |
2168 | fe71e81a | balrog | uint16_t outputs; |
2169 | fe71e81a | balrog | uint16_t dir; |
2170 | fe71e81a | balrog | uint16_t edge; |
2171 | fe71e81a | balrog | uint16_t mask; |
2172 | fe71e81a | balrog | uint16_t ints; |
2173 | fe71e81a | balrog | |
2174 | fe71e81a | balrog | uint16_t debounce; |
2175 | fe71e81a | balrog | uint16_t latch; |
2176 | fe71e81a | balrog | uint8_t event; |
2177 | fe71e81a | balrog | |
2178 | fe71e81a | balrog | uint8_t buttons[5];
|
2179 | fe71e81a | balrog | uint8_t row_latch; |
2180 | fe71e81a | balrog | uint8_t cols; |
2181 | fe71e81a | balrog | int kbd_mask;
|
2182 | fe71e81a | balrog | int clk;
|
2183 | fe71e81a | balrog | }; |
2184 | fe71e81a | balrog | |
2185 | fe71e81a | balrog | static void omap_mpuio_set(void *opaque, int line, int level) |
2186 | fe71e81a | balrog | { |
2187 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2188 | fe71e81a | balrog | uint16_t prev = s->inputs; |
2189 | fe71e81a | balrog | |
2190 | fe71e81a | balrog | if (level)
|
2191 | fe71e81a | balrog | s->inputs |= 1 << line;
|
2192 | fe71e81a | balrog | else
|
2193 | fe71e81a | balrog | s->inputs &= ~(1 << line);
|
2194 | fe71e81a | balrog | |
2195 | fe71e81a | balrog | if (((1 << line) & s->dir & ~s->mask) && s->clk) { |
2196 | fe71e81a | balrog | if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
|
2197 | fe71e81a | balrog | s->ints |= 1 << line;
|
2198 | fe71e81a | balrog | qemu_irq_raise(s->irq); |
2199 | fe71e81a | balrog | /* TODO: wakeup */
|
2200 | fe71e81a | balrog | } |
2201 | fe71e81a | balrog | if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ |
2202 | fe71e81a | balrog | (s->event >> 1) == line) /* PIN_SELECT */ |
2203 | fe71e81a | balrog | s->latch = s->inputs; |
2204 | fe71e81a | balrog | } |
2205 | fe71e81a | balrog | } |
2206 | fe71e81a | balrog | |
2207 | fe71e81a | balrog | static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) |
2208 | fe71e81a | balrog | { |
2209 | fe71e81a | balrog | int i;
|
2210 | fe71e81a | balrog | uint8_t *row, rows = 0, cols = ~s->cols;
|
2211 | fe71e81a | balrog | |
2212 | 38a34e1d | balrog | for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) |
2213 | fe71e81a | balrog | if (*row & cols)
|
2214 | 38a34e1d | balrog | rows |= i; |
2215 | fe71e81a | balrog | |
2216 | cf6d9118 | balrog | qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); |
2217 | cf6d9118 | balrog | s->row_latch = ~rows; |
2218 | fe71e81a | balrog | } |
2219 | fe71e81a | balrog | |
2220 | fe71e81a | balrog | static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr) |
2221 | fe71e81a | balrog | { |
2222 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2223 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2224 | fe71e81a | balrog | uint16_t ret; |
2225 | fe71e81a | balrog | |
2226 | fe71e81a | balrog | switch (offset) {
|
2227 | fe71e81a | balrog | case 0x00: /* INPUT_LATCH */ |
2228 | fe71e81a | balrog | return s->inputs;
|
2229 | fe71e81a | balrog | |
2230 | fe71e81a | balrog | case 0x04: /* OUTPUT_REG */ |
2231 | fe71e81a | balrog | return s->outputs;
|
2232 | fe71e81a | balrog | |
2233 | fe71e81a | balrog | case 0x08: /* IO_CNTL */ |
2234 | fe71e81a | balrog | return s->dir;
|
2235 | fe71e81a | balrog | |
2236 | fe71e81a | balrog | case 0x10: /* KBR_LATCH */ |
2237 | fe71e81a | balrog | return s->row_latch;
|
2238 | fe71e81a | balrog | |
2239 | fe71e81a | balrog | case 0x14: /* KBC_REG */ |
2240 | fe71e81a | balrog | return s->cols;
|
2241 | fe71e81a | balrog | |
2242 | fe71e81a | balrog | case 0x18: /* GPIO_EVENT_MODE_REG */ |
2243 | fe71e81a | balrog | return s->event;
|
2244 | fe71e81a | balrog | |
2245 | fe71e81a | balrog | case 0x1c: /* GPIO_INT_EDGE_REG */ |
2246 | fe71e81a | balrog | return s->edge;
|
2247 | fe71e81a | balrog | |
2248 | fe71e81a | balrog | case 0x20: /* KBD_INT */ |
2249 | cf6d9118 | balrog | return (~s->row_latch & 0x1f) && !s->kbd_mask; |
2250 | fe71e81a | balrog | |
2251 | fe71e81a | balrog | case 0x24: /* GPIO_INT */ |
2252 | fe71e81a | balrog | ret = s->ints; |
2253 | 8e129e07 | balrog | s->ints &= s->mask; |
2254 | 8e129e07 | balrog | if (ret)
|
2255 | 8e129e07 | balrog | qemu_irq_lower(s->irq); |
2256 | fe71e81a | balrog | return ret;
|
2257 | fe71e81a | balrog | |
2258 | fe71e81a | balrog | case 0x28: /* KBD_MASKIT */ |
2259 | fe71e81a | balrog | return s->kbd_mask;
|
2260 | fe71e81a | balrog | |
2261 | fe71e81a | balrog | case 0x2c: /* GPIO_MASKIT */ |
2262 | fe71e81a | balrog | return s->mask;
|
2263 | fe71e81a | balrog | |
2264 | fe71e81a | balrog | case 0x30: /* GPIO_DEBOUNCING_REG */ |
2265 | fe71e81a | balrog | return s->debounce;
|
2266 | fe71e81a | balrog | |
2267 | fe71e81a | balrog | case 0x34: /* GPIO_LATCH_REG */ |
2268 | fe71e81a | balrog | return s->latch;
|
2269 | fe71e81a | balrog | } |
2270 | fe71e81a | balrog | |
2271 | fe71e81a | balrog | OMAP_BAD_REG(addr); |
2272 | fe71e81a | balrog | return 0; |
2273 | fe71e81a | balrog | } |
2274 | fe71e81a | balrog | |
2275 | fe71e81a | balrog | static void omap_mpuio_write(void *opaque, target_phys_addr_t addr, |
2276 | fe71e81a | balrog | uint32_t value) |
2277 | fe71e81a | balrog | { |
2278 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2279 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2280 | fe71e81a | balrog | uint16_t diff; |
2281 | fe71e81a | balrog | int ln;
|
2282 | fe71e81a | balrog | |
2283 | fe71e81a | balrog | switch (offset) {
|
2284 | fe71e81a | balrog | case 0x04: /* OUTPUT_REG */ |
2285 | d8f699cb | balrog | diff = (s->outputs ^ value) & ~s->dir; |
2286 | fe71e81a | balrog | s->outputs = value; |
2287 | fe71e81a | balrog | while ((ln = ffs(diff))) {
|
2288 | fe71e81a | balrog | ln --; |
2289 | fe71e81a | balrog | if (s->handler[ln])
|
2290 | fe71e81a | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2291 | fe71e81a | balrog | diff &= ~(1 << ln);
|
2292 | fe71e81a | balrog | } |
2293 | fe71e81a | balrog | break;
|
2294 | fe71e81a | balrog | |
2295 | fe71e81a | balrog | case 0x08: /* IO_CNTL */ |
2296 | fe71e81a | balrog | diff = s->outputs & (s->dir ^ value); |
2297 | fe71e81a | balrog | s->dir = value; |
2298 | fe71e81a | balrog | |
2299 | fe71e81a | balrog | value = s->outputs & ~s->dir; |
2300 | fe71e81a | balrog | while ((ln = ffs(diff))) {
|
2301 | fe71e81a | balrog | ln --; |
2302 | fe71e81a | balrog | if (s->handler[ln])
|
2303 | fe71e81a | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2304 | fe71e81a | balrog | diff &= ~(1 << ln);
|
2305 | fe71e81a | balrog | } |
2306 | fe71e81a | balrog | break;
|
2307 | fe71e81a | balrog | |
2308 | fe71e81a | balrog | case 0x14: /* KBC_REG */ |
2309 | fe71e81a | balrog | s->cols = value; |
2310 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2311 | fe71e81a | balrog | break;
|
2312 | fe71e81a | balrog | |
2313 | fe71e81a | balrog | case 0x18: /* GPIO_EVENT_MODE_REG */ |
2314 | fe71e81a | balrog | s->event = value & 0x1f;
|
2315 | fe71e81a | balrog | break;
|
2316 | fe71e81a | balrog | |
2317 | fe71e81a | balrog | case 0x1c: /* GPIO_INT_EDGE_REG */ |
2318 | fe71e81a | balrog | s->edge = value; |
2319 | fe71e81a | balrog | break;
|
2320 | fe71e81a | balrog | |
2321 | fe71e81a | balrog | case 0x28: /* KBD_MASKIT */ |
2322 | fe71e81a | balrog | s->kbd_mask = value & 1;
|
2323 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2324 | fe71e81a | balrog | break;
|
2325 | fe71e81a | balrog | |
2326 | fe71e81a | balrog | case 0x2c: /* GPIO_MASKIT */ |
2327 | fe71e81a | balrog | s->mask = value; |
2328 | fe71e81a | balrog | break;
|
2329 | fe71e81a | balrog | |
2330 | fe71e81a | balrog | case 0x30: /* GPIO_DEBOUNCING_REG */ |
2331 | fe71e81a | balrog | s->debounce = value & 0x1ff;
|
2332 | fe71e81a | balrog | break;
|
2333 | fe71e81a | balrog | |
2334 | fe71e81a | balrog | case 0x00: /* INPUT_LATCH */ |
2335 | fe71e81a | balrog | case 0x10: /* KBR_LATCH */ |
2336 | fe71e81a | balrog | case 0x20: /* KBD_INT */ |
2337 | fe71e81a | balrog | case 0x24: /* GPIO_INT */ |
2338 | fe71e81a | balrog | case 0x34: /* GPIO_LATCH_REG */ |
2339 | fe71e81a | balrog | OMAP_RO_REG(addr); |
2340 | fe71e81a | balrog | return;
|
2341 | fe71e81a | balrog | |
2342 | fe71e81a | balrog | default:
|
2343 | fe71e81a | balrog | OMAP_BAD_REG(addr); |
2344 | fe71e81a | balrog | return;
|
2345 | fe71e81a | balrog | } |
2346 | fe71e81a | balrog | } |
2347 | fe71e81a | balrog | |
2348 | fe71e81a | balrog | static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
|
2349 | fe71e81a | balrog | omap_badwidth_read16, |
2350 | fe71e81a | balrog | omap_mpuio_read, |
2351 | fe71e81a | balrog | omap_badwidth_read16, |
2352 | fe71e81a | balrog | }; |
2353 | fe71e81a | balrog | |
2354 | fe71e81a | balrog | static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
|
2355 | fe71e81a | balrog | omap_badwidth_write16, |
2356 | fe71e81a | balrog | omap_mpuio_write, |
2357 | fe71e81a | balrog | omap_badwidth_write16, |
2358 | fe71e81a | balrog | }; |
2359 | fe71e81a | balrog | |
2360 | 9596ebb7 | pbrook | static void omap_mpuio_reset(struct omap_mpuio_s *s) |
2361 | fe71e81a | balrog | { |
2362 | fe71e81a | balrog | s->inputs = 0;
|
2363 | fe71e81a | balrog | s->outputs = 0;
|
2364 | fe71e81a | balrog | s->dir = ~0;
|
2365 | fe71e81a | balrog | s->event = 0;
|
2366 | fe71e81a | balrog | s->edge = 0;
|
2367 | fe71e81a | balrog | s->kbd_mask = 0;
|
2368 | fe71e81a | balrog | s->mask = 0;
|
2369 | fe71e81a | balrog | s->debounce = 0;
|
2370 | fe71e81a | balrog | s->latch = 0;
|
2371 | fe71e81a | balrog | s->ints = 0;
|
2372 | fe71e81a | balrog | s->row_latch = 0x1f;
|
2373 | 38a34e1d | balrog | s->clk = 1;
|
2374 | fe71e81a | balrog | } |
2375 | fe71e81a | balrog | |
2376 | fe71e81a | balrog | static void omap_mpuio_onoff(void *opaque, int line, int on) |
2377 | fe71e81a | balrog | { |
2378 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2379 | fe71e81a | balrog | |
2380 | fe71e81a | balrog | s->clk = on; |
2381 | fe71e81a | balrog | if (on)
|
2382 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2383 | fe71e81a | balrog | } |
2384 | fe71e81a | balrog | |
2385 | fe71e81a | balrog | struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
2386 | fe71e81a | balrog | qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
2387 | fe71e81a | balrog | omap_clk clk) |
2388 | fe71e81a | balrog | { |
2389 | fe71e81a | balrog | int iomemtype;
|
2390 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) |
2391 | fe71e81a | balrog | qemu_mallocz(sizeof(struct omap_mpuio_s)); |
2392 | fe71e81a | balrog | |
2393 | fe71e81a | balrog | s->base = base; |
2394 | fe71e81a | balrog | s->irq = gpio_int; |
2395 | fe71e81a | balrog | s->kbd_irq = kbd_int; |
2396 | fe71e81a | balrog | s->wakeup = wakeup; |
2397 | fe71e81a | balrog | s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
|
2398 | fe71e81a | balrog | omap_mpuio_reset(s); |
2399 | fe71e81a | balrog | |
2400 | fe71e81a | balrog | iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
|
2401 | fe71e81a | balrog | omap_mpuio_writefn, s); |
2402 | fe71e81a | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
2403 | fe71e81a | balrog | |
2404 | fe71e81a | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); |
2405 | fe71e81a | balrog | |
2406 | fe71e81a | balrog | return s;
|
2407 | fe71e81a | balrog | } |
2408 | fe71e81a | balrog | |
2409 | fe71e81a | balrog | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
|
2410 | fe71e81a | balrog | { |
2411 | fe71e81a | balrog | return s->in;
|
2412 | fe71e81a | balrog | } |
2413 | fe71e81a | balrog | |
2414 | fe71e81a | balrog | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) |
2415 | fe71e81a | balrog | { |
2416 | fe71e81a | balrog | if (line >= 16 || line < 0) |
2417 | fe71e81a | balrog | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
|
2418 | fe71e81a | balrog | s->handler[line] = handler; |
2419 | fe71e81a | balrog | } |
2420 | fe71e81a | balrog | |
2421 | fe71e81a | balrog | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) |
2422 | fe71e81a | balrog | { |
2423 | fe71e81a | balrog | if (row >= 5 || row < 0) |
2424 | fe71e81a | balrog | cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
|
2425 | fe71e81a | balrog | __FUNCTION__, col, row); |
2426 | fe71e81a | balrog | |
2427 | fe71e81a | balrog | if (down)
|
2428 | 38a34e1d | balrog | s->buttons[row] |= 1 << col;
|
2429 | fe71e81a | balrog | else
|
2430 | 38a34e1d | balrog | s->buttons[row] &= ~(1 << col);
|
2431 | fe71e81a | balrog | |
2432 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2433 | fe71e81a | balrog | } |
2434 | fe71e81a | balrog | |
2435 | 64330148 | balrog | /* General-Purpose I/O */
|
2436 | 64330148 | balrog | struct omap_gpio_s {
|
2437 | 64330148 | balrog | target_phys_addr_t base; |
2438 | 64330148 | balrog | qemu_irq irq; |
2439 | 64330148 | balrog | qemu_irq *in; |
2440 | 64330148 | balrog | qemu_irq handler[16];
|
2441 | 64330148 | balrog | |
2442 | 64330148 | balrog | uint16_t inputs; |
2443 | 64330148 | balrog | uint16_t outputs; |
2444 | 64330148 | balrog | uint16_t dir; |
2445 | 64330148 | balrog | uint16_t edge; |
2446 | 64330148 | balrog | uint16_t mask; |
2447 | 64330148 | balrog | uint16_t ints; |
2448 | d8f699cb | balrog | uint16_t pins; |
2449 | 64330148 | balrog | }; |
2450 | 64330148 | balrog | |
2451 | 64330148 | balrog | static void omap_gpio_set(void *opaque, int line, int level) |
2452 | 64330148 | balrog | { |
2453 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
2454 | 64330148 | balrog | uint16_t prev = s->inputs; |
2455 | 64330148 | balrog | |
2456 | 64330148 | balrog | if (level)
|
2457 | 64330148 | balrog | s->inputs |= 1 << line;
|
2458 | 64330148 | balrog | else
|
2459 | 64330148 | balrog | s->inputs &= ~(1 << line);
|
2460 | 64330148 | balrog | |
2461 | 64330148 | balrog | if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
|
2462 | 64330148 | balrog | (1 << line) & s->dir & ~s->mask) {
|
2463 | 64330148 | balrog | s->ints |= 1 << line;
|
2464 | 64330148 | balrog | qemu_irq_raise(s->irq); |
2465 | 64330148 | balrog | } |
2466 | 64330148 | balrog | } |
2467 | 64330148 | balrog | |
2468 | 64330148 | balrog | static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) |
2469 | 64330148 | balrog | { |
2470 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
2471 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2472 | 64330148 | balrog | |
2473 | 64330148 | balrog | switch (offset) {
|
2474 | 64330148 | balrog | case 0x00: /* DATA_INPUT */ |
2475 | d8f699cb | balrog | return s->inputs & s->pins;
|
2476 | 64330148 | balrog | |
2477 | 64330148 | balrog | case 0x04: /* DATA_OUTPUT */ |
2478 | 64330148 | balrog | return s->outputs;
|
2479 | 64330148 | balrog | |
2480 | 64330148 | balrog | case 0x08: /* DIRECTION_CONTROL */ |
2481 | 64330148 | balrog | return s->dir;
|
2482 | 64330148 | balrog | |
2483 | 64330148 | balrog | case 0x0c: /* INTERRUPT_CONTROL */ |
2484 | 64330148 | balrog | return s->edge;
|
2485 | 64330148 | balrog | |
2486 | 64330148 | balrog | case 0x10: /* INTERRUPT_MASK */ |
2487 | 64330148 | balrog | return s->mask;
|
2488 | 64330148 | balrog | |
2489 | 64330148 | balrog | case 0x14: /* INTERRUPT_STATUS */ |
2490 | 64330148 | balrog | return s->ints;
|
2491 | d8f699cb | balrog | |
2492 | d8f699cb | balrog | case 0x18: /* PIN_CONTROL (not in OMAP310) */ |
2493 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
2494 | d8f699cb | balrog | return s->pins;
|
2495 | 64330148 | balrog | } |
2496 | 64330148 | balrog | |
2497 | 64330148 | balrog | OMAP_BAD_REG(addr); |
2498 | 64330148 | balrog | return 0; |
2499 | 64330148 | balrog | } |
2500 | 64330148 | balrog | |
2501 | 64330148 | balrog | static void omap_gpio_write(void *opaque, target_phys_addr_t addr, |
2502 | 64330148 | balrog | uint32_t value) |
2503 | 64330148 | balrog | { |
2504 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
2505 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2506 | 64330148 | balrog | uint16_t diff; |
2507 | 64330148 | balrog | int ln;
|
2508 | 64330148 | balrog | |
2509 | 64330148 | balrog | switch (offset) {
|
2510 | 64330148 | balrog | case 0x00: /* DATA_INPUT */ |
2511 | 64330148 | balrog | OMAP_RO_REG(addr); |
2512 | 64330148 | balrog | return;
|
2513 | 64330148 | balrog | |
2514 | 64330148 | balrog | case 0x04: /* DATA_OUTPUT */ |
2515 | 66450b15 | balrog | diff = (s->outputs ^ value) & ~s->dir; |
2516 | 64330148 | balrog | s->outputs = value; |
2517 | 64330148 | balrog | while ((ln = ffs(diff))) {
|
2518 | 64330148 | balrog | ln --; |
2519 | 64330148 | balrog | if (s->handler[ln])
|
2520 | 64330148 | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2521 | 64330148 | balrog | diff &= ~(1 << ln);
|
2522 | 64330148 | balrog | } |
2523 | 64330148 | balrog | break;
|
2524 | 64330148 | balrog | |
2525 | 64330148 | balrog | case 0x08: /* DIRECTION_CONTROL */ |
2526 | 64330148 | balrog | diff = s->outputs & (s->dir ^ value); |
2527 | 64330148 | balrog | s->dir = value; |
2528 | 64330148 | balrog | |
2529 | 64330148 | balrog | value = s->outputs & ~s->dir; |
2530 | 64330148 | balrog | while ((ln = ffs(diff))) {
|
2531 | 64330148 | balrog | ln --; |
2532 | 64330148 | balrog | if (s->handler[ln])
|
2533 | 64330148 | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2534 | 64330148 | balrog | diff &= ~(1 << ln);
|
2535 | 64330148 | balrog | } |
2536 | 64330148 | balrog | break;
|
2537 | 64330148 | balrog | |
2538 | 64330148 | balrog | case 0x0c: /* INTERRUPT_CONTROL */ |
2539 | 64330148 | balrog | s->edge = value; |
2540 | 64330148 | balrog | break;
|
2541 | 64330148 | balrog | |
2542 | 64330148 | balrog | case 0x10: /* INTERRUPT_MASK */ |
2543 | 64330148 | balrog | s->mask = value; |
2544 | 64330148 | balrog | break;
|
2545 | 64330148 | balrog | |
2546 | 64330148 | balrog | case 0x14: /* INTERRUPT_STATUS */ |
2547 | 64330148 | balrog | s->ints &= ~value; |
2548 | 64330148 | balrog | if (!s->ints)
|
2549 | 64330148 | balrog | qemu_irq_lower(s->irq); |
2550 | 64330148 | balrog | break;
|
2551 | 64330148 | balrog | |
2552 | d8f699cb | balrog | case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ |
2553 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
2554 | d8f699cb | balrog | s->pins = value; |
2555 | d8f699cb | balrog | break;
|
2556 | d8f699cb | balrog | |
2557 | 64330148 | balrog | default:
|
2558 | 64330148 | balrog | OMAP_BAD_REG(addr); |
2559 | 64330148 | balrog | return;
|
2560 | 64330148 | balrog | } |
2561 | 64330148 | balrog | } |
2562 | 64330148 | balrog | |
2563 | 3efda49d | balrog | /* *Some* sources say the memory region is 32-bit. */
|
2564 | 64330148 | balrog | static CPUReadMemoryFunc *omap_gpio_readfn[] = {
|
2565 | 3efda49d | balrog | omap_badwidth_read16, |
2566 | 64330148 | balrog | omap_gpio_read, |
2567 | 3efda49d | balrog | omap_badwidth_read16, |
2568 | 64330148 | balrog | }; |
2569 | 64330148 | balrog | |
2570 | 64330148 | balrog | static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
|
2571 | 3efda49d | balrog | omap_badwidth_write16, |
2572 | 64330148 | balrog | omap_gpio_write, |
2573 | 3efda49d | balrog | omap_badwidth_write16, |
2574 | 64330148 | balrog | }; |
2575 | 64330148 | balrog | |
2576 | 9596ebb7 | pbrook | static void omap_gpio_reset(struct omap_gpio_s *s) |
2577 | 64330148 | balrog | { |
2578 | 64330148 | balrog | s->inputs = 0;
|
2579 | 64330148 | balrog | s->outputs = ~0;
|
2580 | 64330148 | balrog | s->dir = ~0;
|
2581 | 64330148 | balrog | s->edge = ~0;
|
2582 | 64330148 | balrog | s->mask = ~0;
|
2583 | 64330148 | balrog | s->ints = 0;
|
2584 | d8f699cb | balrog | s->pins = ~0;
|
2585 | 64330148 | balrog | } |
2586 | 64330148 | balrog | |
2587 | 64330148 | balrog | struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
|
2588 | 64330148 | balrog | qemu_irq irq, omap_clk clk) |
2589 | 64330148 | balrog | { |
2590 | 64330148 | balrog | int iomemtype;
|
2591 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) |
2592 | 64330148 | balrog | qemu_mallocz(sizeof(struct omap_gpio_s)); |
2593 | 64330148 | balrog | |
2594 | 64330148 | balrog | s->base = base; |
2595 | 64330148 | balrog | s->irq = irq; |
2596 | 64330148 | balrog | s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
|
2597 | 64330148 | balrog | omap_gpio_reset(s); |
2598 | 64330148 | balrog | |
2599 | 64330148 | balrog | iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
|
2600 | 64330148 | balrog | omap_gpio_writefn, s); |
2601 | 64330148 | balrog | cpu_register_physical_memory(s->base, 0x1000, iomemtype);
|
2602 | 64330148 | balrog | |
2603 | 64330148 | balrog | return s;
|
2604 | 64330148 | balrog | } |
2605 | 64330148 | balrog | |
2606 | 64330148 | balrog | qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
|
2607 | 64330148 | balrog | { |
2608 | 64330148 | balrog | return s->in;
|
2609 | 64330148 | balrog | } |
2610 | 64330148 | balrog | |
2611 | 64330148 | balrog | void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler) |
2612 | 64330148 | balrog | { |
2613 | 64330148 | balrog | if (line >= 16 || line < 0) |
2614 | 64330148 | balrog | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
|
2615 | 64330148 | balrog | s->handler[line] = handler; |
2616 | 64330148 | balrog | } |
2617 | 64330148 | balrog | |
2618 | d951f6ff | balrog | /* MicroWire Interface */
|
2619 | d951f6ff | balrog | struct omap_uwire_s {
|
2620 | d951f6ff | balrog | target_phys_addr_t base; |
2621 | d951f6ff | balrog | qemu_irq txirq; |
2622 | d951f6ff | balrog | qemu_irq rxirq; |
2623 | d951f6ff | balrog | qemu_irq txdrq; |
2624 | d951f6ff | balrog | |
2625 | d951f6ff | balrog | uint16_t txbuf; |
2626 | d951f6ff | balrog | uint16_t rxbuf; |
2627 | d951f6ff | balrog | uint16_t control; |
2628 | d951f6ff | balrog | uint16_t setup[5];
|
2629 | d951f6ff | balrog | |
2630 | d951f6ff | balrog | struct uwire_slave_s *chip[4]; |
2631 | d951f6ff | balrog | }; |
2632 | d951f6ff | balrog | |
2633 | d951f6ff | balrog | static void omap_uwire_transfer_start(struct omap_uwire_s *s) |
2634 | d951f6ff | balrog | { |
2635 | d951f6ff | balrog | int chipselect = (s->control >> 10) & 3; /* INDEX */ |
2636 | d951f6ff | balrog | struct uwire_slave_s *slave = s->chip[chipselect];
|
2637 | d951f6ff | balrog | |
2638 | d951f6ff | balrog | if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ |
2639 | d951f6ff | balrog | if (s->control & (1 << 12)) /* CS_CMD */ |
2640 | d951f6ff | balrog | if (slave && slave->send)
|
2641 | d951f6ff | balrog | slave->send(slave->opaque, |
2642 | d951f6ff | balrog | s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); |
2643 | d951f6ff | balrog | s->control &= ~(1 << 14); /* CSRB */ |
2644 | d951f6ff | balrog | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
2645 | d951f6ff | balrog | * a DRQ. When is the level IRQ supposed to be reset? */
|
2646 | d951f6ff | balrog | } |
2647 | d951f6ff | balrog | |
2648 | d951f6ff | balrog | if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ |
2649 | d951f6ff | balrog | if (s->control & (1 << 12)) /* CS_CMD */ |
2650 | d951f6ff | balrog | if (slave && slave->receive)
|
2651 | d951f6ff | balrog | s->rxbuf = slave->receive(slave->opaque); |
2652 | d951f6ff | balrog | s->control |= 1 << 15; /* RDRB */ |
2653 | d951f6ff | balrog | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
2654 | d951f6ff | balrog | * a DRQ. When is the level IRQ supposed to be reset? */
|
2655 | d951f6ff | balrog | } |
2656 | d951f6ff | balrog | } |
2657 | d951f6ff | balrog | |
2658 | d951f6ff | balrog | static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr) |
2659 | d951f6ff | balrog | { |
2660 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
2661 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2662 | d951f6ff | balrog | |
2663 | d951f6ff | balrog | switch (offset) {
|
2664 | d951f6ff | balrog | case 0x00: /* RDR */ |
2665 | d951f6ff | balrog | s->control &= ~(1 << 15); /* RDRB */ |
2666 | d951f6ff | balrog | return s->rxbuf;
|
2667 | d951f6ff | balrog | |
2668 | d951f6ff | balrog | case 0x04: /* CSR */ |
2669 | d951f6ff | balrog | return s->control;
|
2670 | d951f6ff | balrog | |
2671 | d951f6ff | balrog | case 0x08: /* SR1 */ |
2672 | d951f6ff | balrog | return s->setup[0]; |
2673 | d951f6ff | balrog | case 0x0c: /* SR2 */ |
2674 | d951f6ff | balrog | return s->setup[1]; |
2675 | d951f6ff | balrog | case 0x10: /* SR3 */ |
2676 | d951f6ff | balrog | return s->setup[2]; |
2677 | d951f6ff | balrog | case 0x14: /* SR4 */ |
2678 | d951f6ff | balrog | return s->setup[3]; |
2679 | d951f6ff | balrog | case 0x18: /* SR5 */ |
2680 | d951f6ff | balrog | return s->setup[4]; |
2681 | d951f6ff | balrog | } |
2682 | d951f6ff | balrog | |
2683 | d951f6ff | balrog | OMAP_BAD_REG(addr); |
2684 | d951f6ff | balrog | return 0; |
2685 | d951f6ff | balrog | } |
2686 | d951f6ff | balrog | |
2687 | d951f6ff | balrog | static void omap_uwire_write(void *opaque, target_phys_addr_t addr, |
2688 | d951f6ff | balrog | uint32_t value) |
2689 | d951f6ff | balrog | { |
2690 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
2691 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2692 | d951f6ff | balrog | |
2693 | d951f6ff | balrog | switch (offset) {
|
2694 | d951f6ff | balrog | case 0x00: /* TDR */ |
2695 | d951f6ff | balrog | s->txbuf = value; /* TD */
|
2696 | d951f6ff | balrog | if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ |
2697 | d951f6ff | balrog | ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ |
2698 | cf965d24 | balrog | (s->control & (1 << 12)))) { /* CS_CMD */ |
2699 | cf965d24 | balrog | s->control |= 1 << 14; /* CSRB */ |
2700 | d951f6ff | balrog | omap_uwire_transfer_start(s); |
2701 | cf965d24 | balrog | } |
2702 | d951f6ff | balrog | break;
|
2703 | d951f6ff | balrog | |
2704 | d951f6ff | balrog | case 0x04: /* CSR */ |
2705 | d951f6ff | balrog | s->control = value & 0x1fff;
|
2706 | d951f6ff | balrog | if (value & (1 << 13)) /* START */ |
2707 | d951f6ff | balrog | omap_uwire_transfer_start(s); |
2708 | d951f6ff | balrog | break;
|
2709 | d951f6ff | balrog | |
2710 | d951f6ff | balrog | case 0x08: /* SR1 */ |
2711 | d951f6ff | balrog | s->setup[0] = value & 0x003f; |
2712 | d951f6ff | balrog | break;
|
2713 | d951f6ff | balrog | |
2714 | d951f6ff | balrog | case 0x0c: /* SR2 */ |
2715 | d951f6ff | balrog | s->setup[1] = value & 0x0fc0; |
2716 | d951f6ff | balrog | break;
|
2717 | d951f6ff | balrog | |
2718 | d951f6ff | balrog | case 0x10: /* SR3 */ |
2719 | d951f6ff | balrog | s->setup[2] = value & 0x0003; |
2720 | d951f6ff | balrog | break;
|
2721 | d951f6ff | balrog | |
2722 | d951f6ff | balrog | case 0x14: /* SR4 */ |
2723 | d951f6ff | balrog | s->setup[3] = value & 0x0001; |
2724 | d951f6ff | balrog | break;
|
2725 | d951f6ff | balrog | |
2726 | d951f6ff | balrog | case 0x18: /* SR5 */ |
2727 | d951f6ff | balrog | s->setup[4] = value & 0x000f; |
2728 | d951f6ff | balrog | break;
|
2729 | d951f6ff | balrog | |
2730 | d951f6ff | balrog | default:
|
2731 | d951f6ff | balrog | OMAP_BAD_REG(addr); |
2732 | d951f6ff | balrog | return;
|
2733 | d951f6ff | balrog | } |
2734 | d951f6ff | balrog | } |
2735 | d951f6ff | balrog | |
2736 | d951f6ff | balrog | static CPUReadMemoryFunc *omap_uwire_readfn[] = {
|
2737 | d951f6ff | balrog | omap_badwidth_read16, |
2738 | d951f6ff | balrog | omap_uwire_read, |
2739 | d951f6ff | balrog | omap_badwidth_read16, |
2740 | d951f6ff | balrog | }; |
2741 | d951f6ff | balrog | |
2742 | d951f6ff | balrog | static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
|
2743 | d951f6ff | balrog | omap_badwidth_write16, |
2744 | d951f6ff | balrog | omap_uwire_write, |
2745 | d951f6ff | balrog | omap_badwidth_write16, |
2746 | d951f6ff | balrog | }; |
2747 | d951f6ff | balrog | |
2748 | 9596ebb7 | pbrook | static void omap_uwire_reset(struct omap_uwire_s *s) |
2749 | d951f6ff | balrog | { |
2750 | 66450b15 | balrog | s->control = 0;
|
2751 | d951f6ff | balrog | s->setup[0] = 0; |
2752 | d951f6ff | balrog | s->setup[1] = 0; |
2753 | d951f6ff | balrog | s->setup[2] = 0; |
2754 | d951f6ff | balrog | s->setup[3] = 0; |
2755 | d951f6ff | balrog | s->setup[4] = 0; |
2756 | d951f6ff | balrog | } |
2757 | d951f6ff | balrog | |
2758 | d951f6ff | balrog | struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
2759 | d951f6ff | balrog | qemu_irq *irq, qemu_irq dma, omap_clk clk) |
2760 | d951f6ff | balrog | { |
2761 | d951f6ff | balrog | int iomemtype;
|
2762 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) |
2763 | d951f6ff | balrog | qemu_mallocz(sizeof(struct omap_uwire_s)); |
2764 | d951f6ff | balrog | |
2765 | d951f6ff | balrog | s->base = base; |
2766 | d951f6ff | balrog | s->txirq = irq[0];
|
2767 | d951f6ff | balrog | s->rxirq = irq[1];
|
2768 | d951f6ff | balrog | s->txdrq = dma; |
2769 | d951f6ff | balrog | omap_uwire_reset(s); |
2770 | d951f6ff | balrog | |
2771 | d951f6ff | balrog | iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
|
2772 | d951f6ff | balrog | omap_uwire_writefn, s); |
2773 | d951f6ff | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
2774 | d951f6ff | balrog | |
2775 | d951f6ff | balrog | return s;
|
2776 | d951f6ff | balrog | } |
2777 | d951f6ff | balrog | |
2778 | d951f6ff | balrog | void omap_uwire_attach(struct omap_uwire_s *s, |
2779 | d951f6ff | balrog | struct uwire_slave_s *slave, int chipselect) |
2780 | d951f6ff | balrog | { |
2781 | d951f6ff | balrog | if (chipselect < 0 || chipselect > 3) |
2782 | d951f6ff | balrog | cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n", __FUNCTION__,
|
2783 | d951f6ff | balrog | chipselect); |
2784 | d951f6ff | balrog | |
2785 | d951f6ff | balrog | s->chip[chipselect] = slave; |
2786 | d951f6ff | balrog | } |
2787 | d951f6ff | balrog | |
2788 | 66450b15 | balrog | /* Pseudonoise Pulse-Width Light Modulator */
|
2789 | 9596ebb7 | pbrook | static void omap_pwl_update(struct omap_mpu_state_s *s) |
2790 | 66450b15 | balrog | { |
2791 | 66450b15 | balrog | int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0; |
2792 | 66450b15 | balrog | |
2793 | 66450b15 | balrog | if (output != s->pwl.output) {
|
2794 | 66450b15 | balrog | s->pwl.output = output; |
2795 | 66450b15 | balrog | printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
|
2796 | 66450b15 | balrog | } |
2797 | 66450b15 | balrog | } |
2798 | 66450b15 | balrog | |
2799 | 66450b15 | balrog | static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr) |
2800 | 66450b15 | balrog | { |
2801 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2802 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2803 | 66450b15 | balrog | |
2804 | 66450b15 | balrog | switch (offset) {
|
2805 | 66450b15 | balrog | case 0x00: /* PWL_LEVEL */ |
2806 | 66450b15 | balrog | return s->pwl.level;
|
2807 | 66450b15 | balrog | case 0x04: /* PWL_CTRL */ |
2808 | 66450b15 | balrog | return s->pwl.enable;
|
2809 | 66450b15 | balrog | } |
2810 | 66450b15 | balrog | OMAP_BAD_REG(addr); |
2811 | 66450b15 | balrog | return 0; |
2812 | 66450b15 | balrog | } |
2813 | 66450b15 | balrog | |
2814 | 66450b15 | balrog | static void omap_pwl_write(void *opaque, target_phys_addr_t addr, |
2815 | 66450b15 | balrog | uint32_t value) |
2816 | 66450b15 | balrog | { |
2817 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2818 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2819 | 66450b15 | balrog | |
2820 | 66450b15 | balrog | switch (offset) {
|
2821 | 66450b15 | balrog | case 0x00: /* PWL_LEVEL */ |
2822 | 66450b15 | balrog | s->pwl.level = value; |
2823 | 66450b15 | balrog | omap_pwl_update(s); |
2824 | 66450b15 | balrog | break;
|
2825 | 66450b15 | balrog | case 0x04: /* PWL_CTRL */ |
2826 | 66450b15 | balrog | s->pwl.enable = value & 1;
|
2827 | 66450b15 | balrog | omap_pwl_update(s); |
2828 | 66450b15 | balrog | break;
|
2829 | 66450b15 | balrog | default:
|
2830 | 66450b15 | balrog | OMAP_BAD_REG(addr); |
2831 | 66450b15 | balrog | return;
|
2832 | 66450b15 | balrog | } |
2833 | 66450b15 | balrog | } |
2834 | 66450b15 | balrog | |
2835 | 66450b15 | balrog | static CPUReadMemoryFunc *omap_pwl_readfn[] = {
|
2836 | 02645926 | balrog | omap_pwl_read, |
2837 | 66450b15 | balrog | omap_badwidth_read8, |
2838 | 66450b15 | balrog | omap_badwidth_read8, |
2839 | 66450b15 | balrog | }; |
2840 | 66450b15 | balrog | |
2841 | 66450b15 | balrog | static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
|
2842 | 02645926 | balrog | omap_pwl_write, |
2843 | 66450b15 | balrog | omap_badwidth_write8, |
2844 | 66450b15 | balrog | omap_badwidth_write8, |
2845 | 66450b15 | balrog | }; |
2846 | 66450b15 | balrog | |
2847 | 9596ebb7 | pbrook | static void omap_pwl_reset(struct omap_mpu_state_s *s) |
2848 | 66450b15 | balrog | { |
2849 | 66450b15 | balrog | s->pwl.output = 0;
|
2850 | 66450b15 | balrog | s->pwl.level = 0;
|
2851 | 66450b15 | balrog | s->pwl.enable = 0;
|
2852 | 66450b15 | balrog | s->pwl.clk = 1;
|
2853 | 66450b15 | balrog | omap_pwl_update(s); |
2854 | 66450b15 | balrog | } |
2855 | 66450b15 | balrog | |
2856 | 66450b15 | balrog | static void omap_pwl_clk_update(void *opaque, int line, int on) |
2857 | 66450b15 | balrog | { |
2858 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2859 | 66450b15 | balrog | |
2860 | 66450b15 | balrog | s->pwl.clk = on; |
2861 | 66450b15 | balrog | omap_pwl_update(s); |
2862 | 66450b15 | balrog | } |
2863 | 66450b15 | balrog | |
2864 | 66450b15 | balrog | static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
2865 | 66450b15 | balrog | omap_clk clk) |
2866 | 66450b15 | balrog | { |
2867 | 66450b15 | balrog | int iomemtype;
|
2868 | 66450b15 | balrog | |
2869 | 66450b15 | balrog | omap_pwl_reset(s); |
2870 | 66450b15 | balrog | |
2871 | 66450b15 | balrog | iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
|
2872 | 66450b15 | balrog | omap_pwl_writefn, s); |
2873 | b854bc19 | balrog | cpu_register_physical_memory(base, 0x800, iomemtype);
|
2874 | 66450b15 | balrog | |
2875 | 66450b15 | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); |
2876 | 66450b15 | balrog | } |
2877 | 66450b15 | balrog | |
2878 | f34c417b | balrog | /* Pulse-Width Tone module */
|
2879 | f34c417b | balrog | static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr) |
2880 | f34c417b | balrog | { |
2881 | f34c417b | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2882 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2883 | f34c417b | balrog | |
2884 | f34c417b | balrog | switch (offset) {
|
2885 | f34c417b | balrog | case 0x00: /* FRC */ |
2886 | f34c417b | balrog | return s->pwt.frc;
|
2887 | f34c417b | balrog | case 0x04: /* VCR */ |
2888 | f34c417b | balrog | return s->pwt.vrc;
|
2889 | f34c417b | balrog | case 0x08: /* GCR */ |
2890 | f34c417b | balrog | return s->pwt.gcr;
|
2891 | f34c417b | balrog | } |
2892 | f34c417b | balrog | OMAP_BAD_REG(addr); |
2893 | f34c417b | balrog | return 0; |
2894 | f34c417b | balrog | } |
2895 | f34c417b | balrog | |
2896 | f34c417b | balrog | static void omap_pwt_write(void *opaque, target_phys_addr_t addr, |
2897 | f34c417b | balrog | uint32_t value) |
2898 | f34c417b | balrog | { |
2899 | f34c417b | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2900 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2901 | f34c417b | balrog | |
2902 | f34c417b | balrog | switch (offset) {
|
2903 | f34c417b | balrog | case 0x00: /* FRC */ |
2904 | f34c417b | balrog | s->pwt.frc = value & 0x3f;
|
2905 | f34c417b | balrog | break;
|
2906 | f34c417b | balrog | case 0x04: /* VRC */ |
2907 | f34c417b | balrog | if ((value ^ s->pwt.vrc) & 1) { |
2908 | f34c417b | balrog | if (value & 1) |
2909 | f34c417b | balrog | printf("%s: %iHz buzz on\n", __FUNCTION__, (int) |
2910 | f34c417b | balrog | /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
|
2911 | f34c417b | balrog | ((omap_clk_getrate(s->pwt.clk) >> 3) /
|
2912 | f34c417b | balrog | /* Pre-multiplexer divider */
|
2913 | f34c417b | balrog | ((s->pwt.gcr & 2) ? 1 : 154) / |
2914 | f34c417b | balrog | /* Octave multiplexer */
|
2915 | f34c417b | balrog | (2 << (value & 3)) * |
2916 | f34c417b | balrog | /* 101/107 divider */
|
2917 | f34c417b | balrog | ((value & (1 << 2)) ? 101 : 107) * |
2918 | f34c417b | balrog | /* 49/55 divider */
|
2919 | f34c417b | balrog | ((value & (1 << 3)) ? 49 : 55) * |
2920 | f34c417b | balrog | /* 50/63 divider */
|
2921 | f34c417b | balrog | ((value & (1 << 4)) ? 50 : 63) * |
2922 | f34c417b | balrog | /* 80/127 divider */
|
2923 | f34c417b | balrog | ((value & (1 << 5)) ? 80 : 127) / |
2924 | f34c417b | balrog | (107 * 55 * 63 * 127))); |
2925 | f34c417b | balrog | else
|
2926 | f34c417b | balrog | printf("%s: silence!\n", __FUNCTION__);
|
2927 | f34c417b | balrog | } |
2928 | f34c417b | balrog | s->pwt.vrc = value & 0x7f;
|
2929 | f34c417b | balrog | break;
|
2930 | f34c417b | balrog | case 0x08: /* GCR */ |
2931 | f34c417b | balrog | s->pwt.gcr = value & 3;
|
2932 | f34c417b | balrog | break;
|
2933 | f34c417b | balrog | default:
|
2934 | f34c417b | balrog | OMAP_BAD_REG(addr); |
2935 | f34c417b | balrog | return;
|
2936 | f34c417b | balrog | } |
2937 | f34c417b | balrog | } |
2938 | f34c417b | balrog | |
2939 | f34c417b | balrog | static CPUReadMemoryFunc *omap_pwt_readfn[] = {
|
2940 | 02645926 | balrog | omap_pwt_read, |
2941 | f34c417b | balrog | omap_badwidth_read8, |
2942 | f34c417b | balrog | omap_badwidth_read8, |
2943 | f34c417b | balrog | }; |
2944 | f34c417b | balrog | |
2945 | f34c417b | balrog | static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
|
2946 | 02645926 | balrog | omap_pwt_write, |
2947 | f34c417b | balrog | omap_badwidth_write8, |
2948 | f34c417b | balrog | omap_badwidth_write8, |
2949 | f34c417b | balrog | }; |
2950 | f34c417b | balrog | |
2951 | 9596ebb7 | pbrook | static void omap_pwt_reset(struct omap_mpu_state_s *s) |
2952 | f34c417b | balrog | { |
2953 | f34c417b | balrog | s->pwt.frc = 0;
|
2954 | f34c417b | balrog | s->pwt.vrc = 0;
|
2955 | f34c417b | balrog | s->pwt.gcr = 0;
|
2956 | f34c417b | balrog | } |
2957 | f34c417b | balrog | |
2958 | f34c417b | balrog | static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
2959 | f34c417b | balrog | omap_clk clk) |
2960 | f34c417b | balrog | { |
2961 | f34c417b | balrog | int iomemtype;
|
2962 | f34c417b | balrog | |
2963 | f34c417b | balrog | s->pwt.clk = clk; |
2964 | f34c417b | balrog | omap_pwt_reset(s); |
2965 | f34c417b | balrog | |
2966 | f34c417b | balrog | iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
|
2967 | f34c417b | balrog | omap_pwt_writefn, s); |
2968 | b854bc19 | balrog | cpu_register_physical_memory(base, 0x800, iomemtype);
|
2969 | f34c417b | balrog | } |
2970 | f34c417b | balrog | |
2971 | 5c1c390f | balrog | /* Real-time Clock module */
|
2972 | 5c1c390f | balrog | struct omap_rtc_s {
|
2973 | 5c1c390f | balrog | target_phys_addr_t base; |
2974 | 5c1c390f | balrog | qemu_irq irq; |
2975 | 5c1c390f | balrog | qemu_irq alarm; |
2976 | 5c1c390f | balrog | QEMUTimer *clk; |
2977 | 5c1c390f | balrog | |
2978 | 5c1c390f | balrog | uint8_t interrupts; |
2979 | 5c1c390f | balrog | uint8_t status; |
2980 | 5c1c390f | balrog | int16_t comp_reg; |
2981 | 5c1c390f | balrog | int running;
|
2982 | 5c1c390f | balrog | int pm_am;
|
2983 | 5c1c390f | balrog | int auto_comp;
|
2984 | 5c1c390f | balrog | int round;
|
2985 | 5c1c390f | balrog | struct tm alarm_tm;
|
2986 | 5c1c390f | balrog | time_t alarm_ti; |
2987 | 5c1c390f | balrog | |
2988 | 5c1c390f | balrog | struct tm current_tm;
|
2989 | 5c1c390f | balrog | time_t ti; |
2990 | 5c1c390f | balrog | uint64_t tick; |
2991 | 5c1c390f | balrog | }; |
2992 | 5c1c390f | balrog | |
2993 | 5c1c390f | balrog | static void omap_rtc_interrupts_update(struct omap_rtc_s *s) |
2994 | 5c1c390f | balrog | { |
2995 | 106627d0 | balrog | /* s->alarm is level-triggered */
|
2996 | 5c1c390f | balrog | qemu_set_irq(s->alarm, (s->status >> 6) & 1); |
2997 | 5c1c390f | balrog | } |
2998 | 5c1c390f | balrog | |
2999 | 5c1c390f | balrog | static void omap_rtc_alarm_update(struct omap_rtc_s *s) |
3000 | 5c1c390f | balrog | { |
3001 | 5c1c390f | balrog | s->alarm_ti = mktime(&s->alarm_tm); |
3002 | 5c1c390f | balrog | if (s->alarm_ti == -1) |
3003 | 5c1c390f | balrog | printf("%s: conversion failed\n", __FUNCTION__);
|
3004 | 5c1c390f | balrog | } |
3005 | 5c1c390f | balrog | |
3006 | 5c1c390f | balrog | static inline uint8_t omap_rtc_bcd(int num) |
3007 | 5c1c390f | balrog | { |
3008 | 5c1c390f | balrog | return ((num / 10) << 4) | (num % 10); |
3009 | 5c1c390f | balrog | } |
3010 | 5c1c390f | balrog | |
3011 | 5c1c390f | balrog | static inline int omap_rtc_bin(uint8_t num) |
3012 | 5c1c390f | balrog | { |
3013 | 5c1c390f | balrog | return (num & 15) + 10 * (num >> 4); |
3014 | 5c1c390f | balrog | } |
3015 | 5c1c390f | balrog | |
3016 | 5c1c390f | balrog | static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr) |
3017 | 5c1c390f | balrog | { |
3018 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
3019 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3020 | 5c1c390f | balrog | uint8_t i; |
3021 | 5c1c390f | balrog | |
3022 | 5c1c390f | balrog | switch (offset) {
|
3023 | 5c1c390f | balrog | case 0x00: /* SECONDS_REG */ |
3024 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_sec);
|
3025 | 5c1c390f | balrog | |
3026 | 5c1c390f | balrog | case 0x04: /* MINUTES_REG */ |
3027 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_min);
|
3028 | 5c1c390f | balrog | |
3029 | 5c1c390f | balrog | case 0x08: /* HOURS_REG */ |
3030 | 5c1c390f | balrog | if (s->pm_am)
|
3031 | 5c1c390f | balrog | return ((s->current_tm.tm_hour > 11) << 7) | |
3032 | 5c1c390f | balrog | omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); |
3033 | 5c1c390f | balrog | else
|
3034 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_hour);
|
3035 | 5c1c390f | balrog | |
3036 | 5c1c390f | balrog | case 0x0c: /* DAYS_REG */ |
3037 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_mday);
|
3038 | 5c1c390f | balrog | |
3039 | 5c1c390f | balrog | case 0x10: /* MONTHS_REG */ |
3040 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_mon + 1); |
3041 | 5c1c390f | balrog | |
3042 | 5c1c390f | balrog | case 0x14: /* YEARS_REG */ |
3043 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_year % 100); |
3044 | 5c1c390f | balrog | |
3045 | 5c1c390f | balrog | case 0x18: /* WEEK_REG */ |
3046 | 5c1c390f | balrog | return s->current_tm.tm_wday;
|
3047 | 5c1c390f | balrog | |
3048 | 5c1c390f | balrog | case 0x20: /* ALARM_SECONDS_REG */ |
3049 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_sec);
|
3050 | 5c1c390f | balrog | |
3051 | 5c1c390f | balrog | case 0x24: /* ALARM_MINUTES_REG */ |
3052 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_min);
|
3053 | 5c1c390f | balrog | |
3054 | 5c1c390f | balrog | case 0x28: /* ALARM_HOURS_REG */ |
3055 | 5c1c390f | balrog | if (s->pm_am)
|
3056 | 5c1c390f | balrog | return ((s->alarm_tm.tm_hour > 11) << 7) | |
3057 | 5c1c390f | balrog | omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); |
3058 | 5c1c390f | balrog | else
|
3059 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_hour);
|
3060 | 5c1c390f | balrog | |
3061 | 5c1c390f | balrog | case 0x2c: /* ALARM_DAYS_REG */ |
3062 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_mday);
|
3063 | 5c1c390f | balrog | |
3064 | 5c1c390f | balrog | case 0x30: /* ALARM_MONTHS_REG */ |
3065 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_mon + 1); |
3066 | 5c1c390f | balrog | |
3067 | 5c1c390f | balrog | case 0x34: /* ALARM_YEARS_REG */ |
3068 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_year % 100); |
3069 | 5c1c390f | balrog | |
3070 | 5c1c390f | balrog | case 0x40: /* RTC_CTRL_REG */ |
3071 | 5c1c390f | balrog | return (s->pm_am << 3) | (s->auto_comp << 2) | |
3072 | 5c1c390f | balrog | (s->round << 1) | s->running;
|
3073 | 5c1c390f | balrog | |
3074 | 5c1c390f | balrog | case 0x44: /* RTC_STATUS_REG */ |
3075 | 5c1c390f | balrog | i = s->status; |
3076 | 5c1c390f | balrog | s->status &= ~0x3d;
|
3077 | 5c1c390f | balrog | return i;
|
3078 | 5c1c390f | balrog | |
3079 | 5c1c390f | balrog | case 0x48: /* RTC_INTERRUPTS_REG */ |
3080 | 5c1c390f | balrog | return s->interrupts;
|
3081 | 5c1c390f | balrog | |
3082 | 5c1c390f | balrog | case 0x4c: /* RTC_COMP_LSB_REG */ |
3083 | 5c1c390f | balrog | return ((uint16_t) s->comp_reg) & 0xff; |
3084 | 5c1c390f | balrog | |
3085 | 5c1c390f | balrog | case 0x50: /* RTC_COMP_MSB_REG */ |
3086 | 5c1c390f | balrog | return ((uint16_t) s->comp_reg) >> 8; |
3087 | 5c1c390f | balrog | } |
3088 | 5c1c390f | balrog | |
3089 | 5c1c390f | balrog | OMAP_BAD_REG(addr); |
3090 | 5c1c390f | balrog | return 0; |
3091 | 5c1c390f | balrog | } |
3092 | 5c1c390f | balrog | |
3093 | 5c1c390f | balrog | static void omap_rtc_write(void *opaque, target_phys_addr_t addr, |
3094 | 5c1c390f | balrog | uint32_t value) |
3095 | 5c1c390f | balrog | { |
3096 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
3097 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3098 | 5c1c390f | balrog | struct tm new_tm;
|
3099 | 5c1c390f | balrog | time_t ti[2];
|
3100 | 5c1c390f | balrog | |
3101 | 5c1c390f | balrog | switch (offset) {
|
3102 | 5c1c390f | balrog | case 0x00: /* SECONDS_REG */ |
3103 | 5c1c390f | balrog | #if ALMDEBUG
|
3104 | 5c1c390f | balrog | printf("RTC SEC_REG <-- %02x\n", value);
|
3105 | 5c1c390f | balrog | #endif
|
3106 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_sec; |
3107 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value); |
3108 | 5c1c390f | balrog | return;
|
3109 | 5c1c390f | balrog | |
3110 | 5c1c390f | balrog | case 0x04: /* MINUTES_REG */ |
3111 | 5c1c390f | balrog | #if ALMDEBUG
|
3112 | 5c1c390f | balrog | printf("RTC MIN_REG <-- %02x\n", value);
|
3113 | 5c1c390f | balrog | #endif
|
3114 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_min * 60;
|
3115 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 60;
|
3116 | 5c1c390f | balrog | return;
|
3117 | 5c1c390f | balrog | |
3118 | 5c1c390f | balrog | case 0x08: /* HOURS_REG */ |
3119 | 5c1c390f | balrog | #if ALMDEBUG
|
3120 | 5c1c390f | balrog | printf("RTC HRS_REG <-- %02x\n", value);
|
3121 | 5c1c390f | balrog | #endif
|
3122 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_hour * 3600;
|
3123 | 5c1c390f | balrog | if (s->pm_am) {
|
3124 | 5c1c390f | balrog | s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600; |
3125 | 5c1c390f | balrog | s->ti += ((value >> 7) & 1) * 43200; |
3126 | 5c1c390f | balrog | } else
|
3127 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value & 0x3f) * 3600; |
3128 | 5c1c390f | balrog | return;
|
3129 | 5c1c390f | balrog | |
3130 | 5c1c390f | balrog | case 0x0c: /* DAYS_REG */ |
3131 | 5c1c390f | balrog | #if ALMDEBUG
|
3132 | 5c1c390f | balrog | printf("RTC DAY_REG <-- %02x\n", value);
|
3133 | 5c1c390f | balrog | #endif
|
3134 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_mday * 86400;
|
3135 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 86400;
|
3136 | 5c1c390f | balrog | return;
|
3137 | 5c1c390f | balrog | |
3138 | 5c1c390f | balrog | case 0x10: /* MONTHS_REG */ |
3139 | 5c1c390f | balrog | #if ALMDEBUG
|
3140 | 5c1c390f | balrog | printf("RTC MTH_REG <-- %02x\n", value);
|
3141 | 5c1c390f | balrog | #endif
|
3142 | 5c1c390f | balrog | memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
3143 | 5c1c390f | balrog | new_tm.tm_mon = omap_rtc_bin(value); |
3144 | 5c1c390f | balrog | ti[0] = mktime(&s->current_tm);
|
3145 | 5c1c390f | balrog | ti[1] = mktime(&new_tm);
|
3146 | 5c1c390f | balrog | |
3147 | 5c1c390f | balrog | if (ti[0] != -1 && ti[1] != -1) { |
3148 | 5c1c390f | balrog | s->ti -= ti[0];
|
3149 | 5c1c390f | balrog | s->ti += ti[1];
|
3150 | 5c1c390f | balrog | } else {
|
3151 | 5c1c390f | balrog | /* A less accurate version */
|
3152 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_mon * 2592000;
|
3153 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 2592000;
|
3154 | 5c1c390f | balrog | } |
3155 | 5c1c390f | balrog | return;
|
3156 | 5c1c390f | balrog | |
3157 | 5c1c390f | balrog | case 0x14: /* YEARS_REG */ |
3158 | 5c1c390f | balrog | #if ALMDEBUG
|
3159 | 5c1c390f | balrog | printf("RTC YRS_REG <-- %02x\n", value);
|
3160 | 5c1c390f | balrog | #endif
|
3161 | 5c1c390f | balrog | memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
3162 | 5c1c390f | balrog | new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100);
|
3163 | 5c1c390f | balrog | ti[0] = mktime(&s->current_tm);
|
3164 | 5c1c390f | balrog | ti[1] = mktime(&new_tm);
|
3165 | 5c1c390f | balrog | |
3166 | 5c1c390f | balrog | if (ti[0] != -1 && ti[1] != -1) { |
3167 | 5c1c390f | balrog | s->ti -= ti[0];
|
3168 | 5c1c390f | balrog | s->ti += ti[1];
|
3169 | 5c1c390f | balrog | } else {
|
3170 | 5c1c390f | balrog | /* A less accurate version */
|
3171 | 5c1c390f | balrog | s->ti -= (s->current_tm.tm_year % 100) * 31536000; |
3172 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 31536000;
|
3173 | 5c1c390f | balrog | } |
3174 | 5c1c390f | balrog | return;
|
3175 | 5c1c390f | balrog | |
3176 | 5c1c390f | balrog | case 0x18: /* WEEK_REG */ |
3177 | 5c1c390f | balrog | return; /* Ignored */ |
3178 | 5c1c390f | balrog | |
3179 | 5c1c390f | balrog | case 0x20: /* ALARM_SECONDS_REG */ |
3180 | 5c1c390f | balrog | #if ALMDEBUG
|
3181 | 5c1c390f | balrog | printf("ALM SEC_REG <-- %02x\n", value);
|
3182 | 5c1c390f | balrog | #endif
|
3183 | 5c1c390f | balrog | s->alarm_tm.tm_sec = omap_rtc_bin(value); |
3184 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3185 | 5c1c390f | balrog | return;
|
3186 | 5c1c390f | balrog | |
3187 | 5c1c390f | balrog | case 0x24: /* ALARM_MINUTES_REG */ |
3188 | 5c1c390f | balrog | #if ALMDEBUG
|
3189 | 5c1c390f | balrog | printf("ALM MIN_REG <-- %02x\n", value);
|
3190 | 5c1c390f | balrog | #endif
|
3191 | 5c1c390f | balrog | s->alarm_tm.tm_min = omap_rtc_bin(value); |
3192 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3193 | 5c1c390f | balrog | return;
|
3194 | 5c1c390f | balrog | |
3195 | 5c1c390f | balrog | case 0x28: /* ALARM_HOURS_REG */ |
3196 | 5c1c390f | balrog | #if ALMDEBUG
|
3197 | 5c1c390f | balrog | printf("ALM HRS_REG <-- %02x\n", value);
|
3198 | 5c1c390f | balrog | #endif
|
3199 | 5c1c390f | balrog | if (s->pm_am)
|
3200 | 5c1c390f | balrog | s->alarm_tm.tm_hour = |
3201 | 5c1c390f | balrog | ((omap_rtc_bin(value & 0x3f)) % 12) + |
3202 | 5c1c390f | balrog | ((value >> 7) & 1) * 12; |
3203 | 5c1c390f | balrog | else
|
3204 | 5c1c390f | balrog | s->alarm_tm.tm_hour = omap_rtc_bin(value); |
3205 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3206 | 5c1c390f | balrog | return;
|
3207 | 5c1c390f | balrog | |
3208 | 5c1c390f | balrog | case 0x2c: /* ALARM_DAYS_REG */ |
3209 | 5c1c390f | balrog | #if ALMDEBUG
|
3210 | 5c1c390f | balrog | printf("ALM DAY_REG <-- %02x\n", value);
|
3211 | 5c1c390f | balrog | #endif
|
3212 | 5c1c390f | balrog | s->alarm_tm.tm_mday = omap_rtc_bin(value); |
3213 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3214 | 5c1c390f | balrog | return;
|
3215 | 5c1c390f | balrog | |
3216 | 5c1c390f | balrog | case 0x30: /* ALARM_MONTHS_REG */ |
3217 | 5c1c390f | balrog | #if ALMDEBUG
|
3218 | 5c1c390f | balrog | printf("ALM MON_REG <-- %02x\n", value);
|
3219 | 5c1c390f | balrog | #endif
|
3220 | 5c1c390f | balrog | s->alarm_tm.tm_mon = omap_rtc_bin(value); |
3221 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3222 | 5c1c390f | balrog | return;
|
3223 | 5c1c390f | balrog | |
3224 | 5c1c390f | balrog | case 0x34: /* ALARM_YEARS_REG */ |
3225 | 5c1c390f | balrog | #if ALMDEBUG
|
3226 | 5c1c390f | balrog | printf("ALM YRS_REG <-- %02x\n", value);
|
3227 | 5c1c390f | balrog | #endif
|
3228 | 5c1c390f | balrog | s->alarm_tm.tm_year = omap_rtc_bin(value); |
3229 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3230 | 5c1c390f | balrog | return;
|
3231 | 5c1c390f | balrog | |
3232 | 5c1c390f | balrog | case 0x40: /* RTC_CTRL_REG */ |
3233 | 5c1c390f | balrog | #if ALMDEBUG
|
3234 | 5c1c390f | balrog | printf("RTC CONTROL <-- %02x\n", value);
|
3235 | 5c1c390f | balrog | #endif
|
3236 | 5c1c390f | balrog | s->pm_am = (value >> 3) & 1; |
3237 | 5c1c390f | balrog | s->auto_comp = (value >> 2) & 1; |
3238 | 5c1c390f | balrog | s->round = (value >> 1) & 1; |
3239 | 5c1c390f | balrog | s->running = value & 1;
|
3240 | 5c1c390f | balrog | s->status &= 0xfd;
|
3241 | 5c1c390f | balrog | s->status |= s->running << 1;
|
3242 | 5c1c390f | balrog | return;
|
3243 | 5c1c390f | balrog | |
3244 | 5c1c390f | balrog | case 0x44: /* RTC_STATUS_REG */ |
3245 | 5c1c390f | balrog | #if ALMDEBUG
|
3246 | 5c1c390f | balrog | printf("RTC STATUSL <-- %02x\n", value);
|
3247 | 5c1c390f | balrog | #endif
|
3248 | 5c1c390f | balrog | s->status &= ~((value & 0xc0) ^ 0x80); |
3249 | 5c1c390f | balrog | omap_rtc_interrupts_update(s); |
3250 | 5c1c390f | balrog | return;
|
3251 | 5c1c390f | balrog | |
3252 | 5c1c390f | balrog | case 0x48: /* RTC_INTERRUPTS_REG */ |
3253 | 5c1c390f | balrog | #if ALMDEBUG
|
3254 | 5c1c390f | balrog | printf("RTC INTRS <-- %02x\n", value);
|
3255 | 5c1c390f | balrog | #endif
|
3256 | 5c1c390f | balrog | s->interrupts = value; |
3257 | 5c1c390f | balrog | return;
|
3258 | 5c1c390f | balrog | |
3259 | 5c1c390f | balrog | case 0x4c: /* RTC_COMP_LSB_REG */ |
3260 | 5c1c390f | balrog | #if ALMDEBUG
|
3261 | 5c1c390f | balrog | printf("RTC COMPLSB <-- %02x\n", value);
|
3262 | 5c1c390f | balrog | #endif
|
3263 | 5c1c390f | balrog | s->comp_reg &= 0xff00;
|
3264 | 5c1c390f | balrog | s->comp_reg |= 0x00ff & value;
|
3265 | 5c1c390f | balrog | return;
|
3266 | 5c1c390f | balrog | |
3267 | 5c1c390f | balrog | case 0x50: /* RTC_COMP_MSB_REG */ |
3268 | 5c1c390f | balrog | #if ALMDEBUG
|
3269 | 5c1c390f | balrog | printf("RTC COMPMSB <-- %02x\n", value);
|
3270 | 5c1c390f | balrog | #endif
|
3271 | 5c1c390f | balrog | s->comp_reg &= 0x00ff;
|
3272 | 5c1c390f | balrog | s->comp_reg |= 0xff00 & (value << 8); |
3273 | 5c1c390f | balrog | return;
|
3274 | 5c1c390f | balrog | |
3275 | 5c1c390f | balrog | default:
|
3276 | 5c1c390f | balrog | OMAP_BAD_REG(addr); |
3277 | 5c1c390f | balrog | return;
|
3278 | 5c1c390f | balrog | } |
3279 | 5c1c390f | balrog | } |
3280 | 5c1c390f | balrog | |
3281 | 5c1c390f | balrog | static CPUReadMemoryFunc *omap_rtc_readfn[] = {
|
3282 | 5c1c390f | balrog | omap_rtc_read, |
3283 | 5c1c390f | balrog | omap_badwidth_read8, |
3284 | 5c1c390f | balrog | omap_badwidth_read8, |
3285 | 5c1c390f | balrog | }; |
3286 | 5c1c390f | balrog | |
3287 | 5c1c390f | balrog | static CPUWriteMemoryFunc *omap_rtc_writefn[] = {
|
3288 | 5c1c390f | balrog | omap_rtc_write, |
3289 | 5c1c390f | balrog | omap_badwidth_write8, |
3290 | 5c1c390f | balrog | omap_badwidth_write8, |
3291 | 5c1c390f | balrog | }; |
3292 | 5c1c390f | balrog | |
3293 | 5c1c390f | balrog | static void omap_rtc_tick(void *opaque) |
3294 | 5c1c390f | balrog | { |
3295 | 5c1c390f | balrog | struct omap_rtc_s *s = opaque;
|
3296 | 5c1c390f | balrog | |
3297 | 5c1c390f | balrog | if (s->round) {
|
3298 | 5c1c390f | balrog | /* Round to nearest full minute. */
|
3299 | 5c1c390f | balrog | if (s->current_tm.tm_sec < 30) |
3300 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_sec; |
3301 | 5c1c390f | balrog | else
|
3302 | 5c1c390f | balrog | s->ti += 60 - s->current_tm.tm_sec;
|
3303 | 5c1c390f | balrog | |
3304 | 5c1c390f | balrog | s->round = 0;
|
3305 | 5c1c390f | balrog | } |
3306 | 5c1c390f | balrog | |
3307 | f6503059 | balrog | memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
|
3308 | 5c1c390f | balrog | |
3309 | 5c1c390f | balrog | if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { |
3310 | 5c1c390f | balrog | s->status |= 0x40;
|
3311 | 5c1c390f | balrog | omap_rtc_interrupts_update(s); |
3312 | 5c1c390f | balrog | } |
3313 | 5c1c390f | balrog | |
3314 | 5c1c390f | balrog | if (s->interrupts & 0x04) |
3315 | 5c1c390f | balrog | switch (s->interrupts & 3) { |
3316 | 5c1c390f | balrog | case 0: |
3317 | 5c1c390f | balrog | s->status |= 0x04;
|
3318 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
3319 | 5c1c390f | balrog | break;
|
3320 | 5c1c390f | balrog | case 1: |
3321 | 5c1c390f | balrog | if (s->current_tm.tm_sec)
|
3322 | 5c1c390f | balrog | break;
|
3323 | 5c1c390f | balrog | s->status |= 0x08;
|
3324 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
3325 | 5c1c390f | balrog | break;
|
3326 | 5c1c390f | balrog | case 2: |
3327 | 5c1c390f | balrog | if (s->current_tm.tm_sec || s->current_tm.tm_min)
|
3328 | 5c1c390f | balrog | break;
|
3329 | 5c1c390f | balrog | s->status |= 0x10;
|
3330 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
3331 | 5c1c390f | balrog | break;
|
3332 | 5c1c390f | balrog | case 3: |
3333 | 5c1c390f | balrog | if (s->current_tm.tm_sec ||
|
3334 | 5c1c390f | balrog | s->current_tm.tm_min || s->current_tm.tm_hour) |
3335 | 5c1c390f | balrog | break;
|
3336 | 5c1c390f | balrog | s->status |= 0x20;
|
3337 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
3338 | 5c1c390f | balrog | break;
|
3339 | 5c1c390f | balrog | } |
3340 | 5c1c390f | balrog | |
3341 | 5c1c390f | balrog | /* Move on */
|
3342 | 5c1c390f | balrog | if (s->running)
|
3343 | 5c1c390f | balrog | s->ti ++; |
3344 | 5c1c390f | balrog | s->tick += 1000;
|
3345 | 5c1c390f | balrog | |
3346 | 5c1c390f | balrog | /*
|
3347 | 5c1c390f | balrog | * Every full hour add a rough approximation of the compensation
|
3348 | 5c1c390f | balrog | * register to the 32kHz Timer (which drives the RTC) value.
|
3349 | 5c1c390f | balrog | */
|
3350 | 5c1c390f | balrog | if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
|
3351 | 5c1c390f | balrog | s->tick += s->comp_reg * 1000 / 32768; |
3352 | 5c1c390f | balrog | |
3353 | 5c1c390f | balrog | qemu_mod_timer(s->clk, s->tick); |
3354 | 5c1c390f | balrog | } |
3355 | 5c1c390f | balrog | |
3356 | 9596ebb7 | pbrook | static void omap_rtc_reset(struct omap_rtc_s *s) |
3357 | 5c1c390f | balrog | { |
3358 | f6503059 | balrog | struct tm tm;
|
3359 | f6503059 | balrog | |
3360 | 5c1c390f | balrog | s->interrupts = 0;
|
3361 | 5c1c390f | balrog | s->comp_reg = 0;
|
3362 | 5c1c390f | balrog | s->running = 0;
|
3363 | 5c1c390f | balrog | s->pm_am = 0;
|
3364 | 5c1c390f | balrog | s->auto_comp = 0;
|
3365 | 5c1c390f | balrog | s->round = 0;
|
3366 | 5c1c390f | balrog | s->tick = qemu_get_clock(rt_clock); |
3367 | 5c1c390f | balrog | memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); |
3368 | 5c1c390f | balrog | s->alarm_tm.tm_mday = 0x01;
|
3369 | 5c1c390f | balrog | s->status = 1 << 7; |
3370 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
3371 | f6503059 | balrog | s->ti = mktime(&tm); |
3372 | 5c1c390f | balrog | |
3373 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3374 | 5c1c390f | balrog | omap_rtc_tick(s); |
3375 | 5c1c390f | balrog | } |
3376 | 5c1c390f | balrog | |
3377 | 5c1c390f | balrog | struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
|
3378 | 5c1c390f | balrog | qemu_irq *irq, omap_clk clk) |
3379 | 5c1c390f | balrog | { |
3380 | 5c1c390f | balrog | int iomemtype;
|
3381 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) |
3382 | 5c1c390f | balrog | qemu_mallocz(sizeof(struct omap_rtc_s)); |
3383 | 5c1c390f | balrog | |
3384 | 5c1c390f | balrog | s->base = base; |
3385 | 5c1c390f | balrog | s->irq = irq[0];
|
3386 | 5c1c390f | balrog | s->alarm = irq[1];
|
3387 | 5c1c390f | balrog | s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s); |
3388 | 5c1c390f | balrog | |
3389 | 5c1c390f | balrog | omap_rtc_reset(s); |
3390 | 5c1c390f | balrog | |
3391 | 5c1c390f | balrog | iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
|
3392 | 5c1c390f | balrog | omap_rtc_writefn, s); |
3393 | 5c1c390f | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
3394 | 5c1c390f | balrog | |
3395 | 5c1c390f | balrog | return s;
|
3396 | 5c1c390f | balrog | } |
3397 | 5c1c390f | balrog | |
3398 | d8f699cb | balrog | /* Multi-channel Buffered Serial Port interfaces */
|
3399 | d8f699cb | balrog | struct omap_mcbsp_s {
|
3400 | d8f699cb | balrog | target_phys_addr_t base; |
3401 | d8f699cb | balrog | qemu_irq txirq; |
3402 | d8f699cb | balrog | qemu_irq rxirq; |
3403 | d8f699cb | balrog | qemu_irq txdrq; |
3404 | d8f699cb | balrog | qemu_irq rxdrq; |
3405 | d8f699cb | balrog | |
3406 | d8f699cb | balrog | uint16_t spcr[2];
|
3407 | d8f699cb | balrog | uint16_t rcr[2];
|
3408 | d8f699cb | balrog | uint16_t xcr[2];
|
3409 | d8f699cb | balrog | uint16_t srgr[2];
|
3410 | d8f699cb | balrog | uint16_t mcr[2];
|
3411 | d8f699cb | balrog | uint16_t pcr; |
3412 | d8f699cb | balrog | uint16_t rcer[8];
|
3413 | d8f699cb | balrog | uint16_t xcer[8];
|
3414 | d8f699cb | balrog | int tx_rate;
|
3415 | d8f699cb | balrog | int rx_rate;
|
3416 | d8f699cb | balrog | int tx_req;
|
3417 | 73560bc8 | balrog | int rx_req;
|
3418 | d8f699cb | balrog | |
3419 | d8f699cb | balrog | struct i2s_codec_s *codec;
|
3420 | 73560bc8 | balrog | QEMUTimer *source_timer; |
3421 | 73560bc8 | balrog | QEMUTimer *sink_timer; |
3422 | d8f699cb | balrog | }; |
3423 | d8f699cb | balrog | |
3424 | d8f699cb | balrog | static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) |
3425 | d8f699cb | balrog | { |
3426 | d8f699cb | balrog | int irq;
|
3427 | d8f699cb | balrog | |
3428 | d8f699cb | balrog | switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ |
3429 | d8f699cb | balrog | case 0: |
3430 | d8f699cb | balrog | irq = (s->spcr[0] >> 1) & 1; /* RRDY */ |
3431 | d8f699cb | balrog | break;
|
3432 | d8f699cb | balrog | case 3: |
3433 | d8f699cb | balrog | irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ |
3434 | d8f699cb | balrog | break;
|
3435 | d8f699cb | balrog | default:
|
3436 | d8f699cb | balrog | irq = 0;
|
3437 | d8f699cb | balrog | break;
|
3438 | d8f699cb | balrog | } |
3439 | d8f699cb | balrog | |
3440 | 106627d0 | balrog | if (irq)
|
3441 | 106627d0 | balrog | qemu_irq_pulse(s->rxirq); |
3442 | d8f699cb | balrog | |
3443 | d8f699cb | balrog | switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ |
3444 | d8f699cb | balrog | case 0: |
3445 | d8f699cb | balrog | irq = (s->spcr[1] >> 1) & 1; /* XRDY */ |
3446 | d8f699cb | balrog | break;
|
3447 | d8f699cb | balrog | case 3: |
3448 | d8f699cb | balrog | irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ |
3449 | d8f699cb | balrog | break;
|
3450 | d8f699cb | balrog | default:
|
3451 | d8f699cb | balrog | irq = 0;
|
3452 | d8f699cb | balrog | break;
|
3453 | d8f699cb | balrog | } |
3454 | d8f699cb | balrog | |
3455 | 106627d0 | balrog | if (irq)
|
3456 | 106627d0 | balrog | qemu_irq_pulse(s->txirq); |
3457 | d8f699cb | balrog | } |
3458 | d8f699cb | balrog | |
3459 | 73560bc8 | balrog | static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) |
3460 | d8f699cb | balrog | { |
3461 | 73560bc8 | balrog | if ((s->spcr[0] >> 1) & 1) /* RRDY */ |
3462 | 73560bc8 | balrog | s->spcr[0] |= 1 << 2; /* RFULL */ |
3463 | 73560bc8 | balrog | s->spcr[0] |= 1 << 1; /* RRDY */ |
3464 | 73560bc8 | balrog | qemu_irq_raise(s->rxdrq); |
3465 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
3466 | d8f699cb | balrog | } |
3467 | d8f699cb | balrog | |
3468 | 73560bc8 | balrog | static void omap_mcbsp_source_tick(void *opaque) |
3469 | d8f699cb | balrog | { |
3470 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3471 | 73560bc8 | balrog | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; |
3472 | 73560bc8 | balrog | |
3473 | 73560bc8 | balrog | if (!s->rx_rate)
|
3474 | d8f699cb | balrog | return;
|
3475 | 73560bc8 | balrog | if (s->rx_req)
|
3476 | 73560bc8 | balrog | printf("%s: Rx FIFO overrun\n", __FUNCTION__);
|
3477 | d8f699cb | balrog | |
3478 | 73560bc8 | balrog | s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; |
3479 | d8f699cb | balrog | |
3480 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
3481 | 73560bc8 | balrog | qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + ticks_per_sec); |
3482 | d8f699cb | balrog | } |
3483 | d8f699cb | balrog | |
3484 | d8f699cb | balrog | static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) |
3485 | d8f699cb | balrog | { |
3486 | 73560bc8 | balrog | if (!s->codec || !s->codec->rts)
|
3487 | 73560bc8 | balrog | omap_mcbsp_source_tick(s); |
3488 | 73560bc8 | balrog | else if (s->codec->in.len) { |
3489 | 73560bc8 | balrog | s->rx_req = s->codec->in.len; |
3490 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
3491 | d8f699cb | balrog | } |
3492 | d8f699cb | balrog | } |
3493 | d8f699cb | balrog | |
3494 | d8f699cb | balrog | static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) |
3495 | d8f699cb | balrog | { |
3496 | 73560bc8 | balrog | qemu_del_timer(s->source_timer); |
3497 | 73560bc8 | balrog | } |
3498 | 73560bc8 | balrog | |
3499 | 73560bc8 | balrog | static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) |
3500 | 73560bc8 | balrog | { |
3501 | d8f699cb | balrog | s->spcr[0] &= ~(1 << 1); /* RRDY */ |
3502 | d8f699cb | balrog | qemu_irq_lower(s->rxdrq); |
3503 | d8f699cb | balrog | omap_mcbsp_intr_update(s); |
3504 | d8f699cb | balrog | } |
3505 | d8f699cb | balrog | |
3506 | 73560bc8 | balrog | static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) |
3507 | 73560bc8 | balrog | { |
3508 | 73560bc8 | balrog | s->spcr[1] |= 1 << 1; /* XRDY */ |
3509 | 73560bc8 | balrog | qemu_irq_raise(s->txdrq); |
3510 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
3511 | 73560bc8 | balrog | } |
3512 | 73560bc8 | balrog | |
3513 | 73560bc8 | balrog | static void omap_mcbsp_sink_tick(void *opaque) |
3514 | d8f699cb | balrog | { |
3515 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3516 | 73560bc8 | balrog | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; |
3517 | 73560bc8 | balrog | |
3518 | 73560bc8 | balrog | if (!s->tx_rate)
|
3519 | d8f699cb | balrog | return;
|
3520 | 73560bc8 | balrog | if (s->tx_req)
|
3521 | 73560bc8 | balrog | printf("%s: Tx FIFO underrun\n", __FUNCTION__);
|
3522 | 73560bc8 | balrog | |
3523 | 73560bc8 | balrog | s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; |
3524 | 73560bc8 | balrog | |
3525 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
3526 | 73560bc8 | balrog | qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + ticks_per_sec); |
3527 | 73560bc8 | balrog | } |
3528 | 73560bc8 | balrog | |
3529 | 73560bc8 | balrog | static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) |
3530 | 73560bc8 | balrog | { |
3531 | 73560bc8 | balrog | if (!s->codec || !s->codec->cts)
|
3532 | 73560bc8 | balrog | omap_mcbsp_sink_tick(s); |
3533 | 73560bc8 | balrog | else if (s->codec->out.size) { |
3534 | 73560bc8 | balrog | s->tx_req = s->codec->out.size; |
3535 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
3536 | 73560bc8 | balrog | } |
3537 | 73560bc8 | balrog | } |
3538 | 73560bc8 | balrog | |
3539 | 73560bc8 | balrog | static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) |
3540 | 73560bc8 | balrog | { |
3541 | 73560bc8 | balrog | s->spcr[1] &= ~(1 << 1); /* XRDY */ |
3542 | 73560bc8 | balrog | qemu_irq_lower(s->txdrq); |
3543 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
3544 | 73560bc8 | balrog | if (s->codec && s->codec->cts)
|
3545 | 73560bc8 | balrog | s->codec->tx_swallow(s->codec->opaque); |
3546 | d8f699cb | balrog | } |
3547 | d8f699cb | balrog | |
3548 | d8f699cb | balrog | static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) |
3549 | d8f699cb | balrog | { |
3550 | 73560bc8 | balrog | s->tx_req = 0;
|
3551 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
3552 | 73560bc8 | balrog | qemu_del_timer(s->sink_timer); |
3553 | 73560bc8 | balrog | } |
3554 | 73560bc8 | balrog | |
3555 | 73560bc8 | balrog | static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) |
3556 | 73560bc8 | balrog | { |
3557 | 73560bc8 | balrog | int prev_rx_rate, prev_tx_rate;
|
3558 | 73560bc8 | balrog | int rx_rate = 0, tx_rate = 0; |
3559 | 73560bc8 | balrog | int cpu_rate = 1500000; /* XXX */ |
3560 | 73560bc8 | balrog | |
3561 | 73560bc8 | balrog | /* TODO: check CLKSTP bit */
|
3562 | 73560bc8 | balrog | if (s->spcr[1] & (1 << 6)) { /* GRST */ |
3563 | 73560bc8 | balrog | if (s->spcr[0] & (1 << 0)) { /* RRST */ |
3564 | 73560bc8 | balrog | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
3565 | 73560bc8 | balrog | (s->pcr & (1 << 8))) { /* CLKRM */ |
3566 | 73560bc8 | balrog | if (~s->pcr & (1 << 7)) /* SCLKME */ |
3567 | 73560bc8 | balrog | rx_rate = cpu_rate / |
3568 | 73560bc8 | balrog | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
3569 | 73560bc8 | balrog | } else
|
3570 | 73560bc8 | balrog | if (s->codec)
|
3571 | 73560bc8 | balrog | rx_rate = s->codec->rx_rate; |
3572 | 73560bc8 | balrog | } |
3573 | 73560bc8 | balrog | |
3574 | 73560bc8 | balrog | if (s->spcr[1] & (1 << 0)) { /* XRST */ |
3575 | 73560bc8 | balrog | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
3576 | 73560bc8 | balrog | (s->pcr & (1 << 9))) { /* CLKXM */ |
3577 | 73560bc8 | balrog | if (~s->pcr & (1 << 7)) /* SCLKME */ |
3578 | 73560bc8 | balrog | tx_rate = cpu_rate / |
3579 | 73560bc8 | balrog | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
3580 | 73560bc8 | balrog | } else
|
3581 | 73560bc8 | balrog | if (s->codec)
|
3582 | 73560bc8 | balrog | tx_rate = s->codec->tx_rate; |
3583 | 73560bc8 | balrog | } |
3584 | 73560bc8 | balrog | } |
3585 | 73560bc8 | balrog | prev_tx_rate = s->tx_rate; |
3586 | 73560bc8 | balrog | prev_rx_rate = s->rx_rate; |
3587 | 73560bc8 | balrog | s->tx_rate = tx_rate; |
3588 | 73560bc8 | balrog | s->rx_rate = rx_rate; |
3589 | 73560bc8 | balrog | |
3590 | 73560bc8 | balrog | if (s->codec)
|
3591 | 73560bc8 | balrog | s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); |
3592 | 73560bc8 | balrog | |
3593 | 73560bc8 | balrog | if (!prev_tx_rate && tx_rate)
|
3594 | 73560bc8 | balrog | omap_mcbsp_tx_start(s); |
3595 | 73560bc8 | balrog | else if (s->tx_rate && !tx_rate) |
3596 | 73560bc8 | balrog | omap_mcbsp_tx_stop(s); |
3597 | 73560bc8 | balrog | |
3598 | 73560bc8 | balrog | if (!prev_rx_rate && rx_rate)
|
3599 | 73560bc8 | balrog | omap_mcbsp_rx_start(s); |
3600 | 73560bc8 | balrog | else if (prev_tx_rate && !tx_rate) |
3601 | 73560bc8 | balrog | omap_mcbsp_rx_stop(s); |
3602 | d8f699cb | balrog | } |
3603 | d8f699cb | balrog | |
3604 | d8f699cb | balrog | static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr) |
3605 | d8f699cb | balrog | { |
3606 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3607 | d8f699cb | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3608 | d8f699cb | balrog | uint16_t ret; |
3609 | d8f699cb | balrog | |
3610 | d8f699cb | balrog | switch (offset) {
|
3611 | d8f699cb | balrog | case 0x00: /* DRR2 */ |
3612 | d8f699cb | balrog | if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ |
3613 | d8f699cb | balrog | return 0x0000; |
3614 | d8f699cb | balrog | /* Fall through. */
|
3615 | d8f699cb | balrog | case 0x02: /* DRR1 */ |
3616 | 73560bc8 | balrog | if (s->rx_req < 2) { |
3617 | d8f699cb | balrog | printf("%s: Rx FIFO underrun\n", __FUNCTION__);
|
3618 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
3619 | d8f699cb | balrog | } else {
|
3620 | 73560bc8 | balrog | s->tx_req -= 2;
|
3621 | 73560bc8 | balrog | if (s->codec && s->codec->in.len >= 2) { |
3622 | 73560bc8 | balrog | ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
|
3623 | 73560bc8 | balrog | ret |= s->codec->in.fifo[s->codec->in.start ++]; |
3624 | 73560bc8 | balrog | s->codec->in.len -= 2;
|
3625 | 73560bc8 | balrog | } else
|
3626 | 73560bc8 | balrog | ret = 0x0000;
|
3627 | 73560bc8 | balrog | if (!s->tx_req)
|
3628 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
3629 | d8f699cb | balrog | return ret;
|
3630 | d8f699cb | balrog | } |
3631 | d8f699cb | balrog | return 0x0000; |
3632 | d8f699cb | balrog | |
3633 | d8f699cb | balrog | case 0x04: /* DXR2 */ |
3634 | d8f699cb | balrog | case 0x06: /* DXR1 */ |
3635 | d8f699cb | balrog | return 0x0000; |
3636 | d8f699cb | balrog | |
3637 | d8f699cb | balrog | case 0x08: /* SPCR2 */ |
3638 | d8f699cb | balrog | return s->spcr[1]; |
3639 | d8f699cb | balrog | case 0x0a: /* SPCR1 */ |
3640 | d8f699cb | balrog | return s->spcr[0]; |
3641 | d8f699cb | balrog | case 0x0c: /* RCR2 */ |
3642 | d8f699cb | balrog | return s->rcr[1]; |
3643 | d8f699cb | balrog | case 0x0e: /* RCR1 */ |
3644 | d8f699cb | balrog | return s->rcr[0]; |
3645 | d8f699cb | balrog | case 0x10: /* XCR2 */ |
3646 | d8f699cb | balrog | return s->xcr[1]; |
3647 | d8f699cb | balrog | case 0x12: /* XCR1 */ |
3648 | d8f699cb | balrog | return s->xcr[0]; |
3649 | d8f699cb | balrog | case 0x14: /* SRGR2 */ |
3650 | d8f699cb | balrog | return s->srgr[1]; |
3651 | d8f699cb | balrog | case 0x16: /* SRGR1 */ |
3652 | d8f699cb | balrog | return s->srgr[0]; |
3653 | d8f699cb | balrog | case 0x18: /* MCR2 */ |
3654 | d8f699cb | balrog | return s->mcr[1]; |
3655 | d8f699cb | balrog | case 0x1a: /* MCR1 */ |
3656 | d8f699cb | balrog | return s->mcr[0]; |
3657 | d8f699cb | balrog | case 0x1c: /* RCERA */ |
3658 | d8f699cb | balrog | return s->rcer[0]; |
3659 | d8f699cb | balrog | case 0x1e: /* RCERB */ |
3660 | d8f699cb | balrog | return s->rcer[1]; |
3661 | d8f699cb | balrog | case 0x20: /* XCERA */ |
3662 | d8f699cb | balrog | return s->xcer[0]; |
3663 | d8f699cb | balrog | case 0x22: /* XCERB */ |
3664 | d8f699cb | balrog | return s->xcer[1]; |
3665 | d8f699cb | balrog | case 0x24: /* PCR0 */ |
3666 | d8f699cb | balrog | return s->pcr;
|
3667 | d8f699cb | balrog | case 0x26: /* RCERC */ |
3668 | d8f699cb | balrog | return s->rcer[2]; |
3669 | d8f699cb | balrog | case 0x28: /* RCERD */ |
3670 | d8f699cb | balrog | return s->rcer[3]; |
3671 | d8f699cb | balrog | case 0x2a: /* XCERC */ |
3672 | d8f699cb | balrog | return s->xcer[2]; |
3673 | d8f699cb | balrog | case 0x2c: /* XCERD */ |
3674 | d8f699cb | balrog | return s->xcer[3]; |
3675 | d8f699cb | balrog | case 0x2e: /* RCERE */ |
3676 | d8f699cb | balrog | return s->rcer[4]; |
3677 | d8f699cb | balrog | case 0x30: /* RCERF */ |
3678 | d8f699cb | balrog | return s->rcer[5]; |
3679 | d8f699cb | balrog | case 0x32: /* XCERE */ |
3680 | d8f699cb | balrog | return s->xcer[4]; |
3681 | d8f699cb | balrog | case 0x34: /* XCERF */ |
3682 | d8f699cb | balrog | return s->xcer[5]; |
3683 | d8f699cb | balrog | case 0x36: /* RCERG */ |
3684 | d8f699cb | balrog | return s->rcer[6]; |
3685 | d8f699cb | balrog | case 0x38: /* RCERH */ |
3686 | d8f699cb | balrog | return s->rcer[7]; |
3687 | d8f699cb | balrog | case 0x3a: /* XCERG */ |
3688 | d8f699cb | balrog | return s->xcer[6]; |
3689 | d8f699cb | balrog | case 0x3c: /* XCERH */ |
3690 | d8f699cb | balrog | return s->xcer[7]; |
3691 | d8f699cb | balrog | } |
3692 | d8f699cb | balrog | |
3693 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
3694 | d8f699cb | balrog | return 0; |
3695 | d8f699cb | balrog | } |
3696 | d8f699cb | balrog | |
3697 | 73560bc8 | balrog | static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr, |
3698 | d8f699cb | balrog | uint32_t value) |
3699 | d8f699cb | balrog | { |
3700 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3701 | d8f699cb | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3702 | d8f699cb | balrog | |
3703 | d8f699cb | balrog | switch (offset) {
|
3704 | d8f699cb | balrog | case 0x00: /* DRR2 */ |
3705 | d8f699cb | balrog | case 0x02: /* DRR1 */ |
3706 | d8f699cb | balrog | OMAP_RO_REG(addr); |
3707 | d8f699cb | balrog | return;
|
3708 | d8f699cb | balrog | |
3709 | d8f699cb | balrog | case 0x04: /* DXR2 */ |
3710 | d8f699cb | balrog | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ |
3711 | d8f699cb | balrog | return;
|
3712 | d8f699cb | balrog | /* Fall through. */
|
3713 | d8f699cb | balrog | case 0x06: /* DXR1 */ |
3714 | 73560bc8 | balrog | if (s->tx_req > 1) { |
3715 | 73560bc8 | balrog | s->tx_req -= 2;
|
3716 | 73560bc8 | balrog | if (s->codec && s->codec->cts) {
|
3717 | d8f699cb | balrog | s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; |
3718 | d8f699cb | balrog | s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; |
3719 | d8f699cb | balrog | } |
3720 | 73560bc8 | balrog | if (s->tx_req < 2) |
3721 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
3722 | d8f699cb | balrog | } else
|
3723 | d8f699cb | balrog | printf("%s: Tx FIFO overrun\n", __FUNCTION__);
|
3724 | d8f699cb | balrog | return;
|
3725 | d8f699cb | balrog | |
3726 | d8f699cb | balrog | case 0x08: /* SPCR2 */ |
3727 | d8f699cb | balrog | s->spcr[1] &= 0x0002; |
3728 | d8f699cb | balrog | s->spcr[1] |= 0x03f9 & value; |
3729 | d8f699cb | balrog | s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ |
3730 | 73560bc8 | balrog | if (~value & 1) /* XRST */ |
3731 | d8f699cb | balrog | s->spcr[1] &= ~6; |
3732 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
3733 | d8f699cb | balrog | return;
|
3734 | d8f699cb | balrog | case 0x0a: /* SPCR1 */ |
3735 | d8f699cb | balrog | s->spcr[0] &= 0x0006; |
3736 | d8f699cb | balrog | s->spcr[0] |= 0xf8f9 & value; |
3737 | d8f699cb | balrog | if (value & (1 << 15)) /* DLB */ |
3738 | d8f699cb | balrog | printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
|
3739 | d8f699cb | balrog | if (~value & 1) { /* RRST */ |
3740 | d8f699cb | balrog | s->spcr[0] &= ~6; |
3741 | 73560bc8 | balrog | s->rx_req = 0;
|
3742 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
3743 | d8f699cb | balrog | } |
3744 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
3745 | d8f699cb | balrog | return;
|
3746 | d8f699cb | balrog | |
3747 | d8f699cb | balrog | case 0x0c: /* RCR2 */ |
3748 | d8f699cb | balrog | s->rcr[1] = value & 0xffff; |
3749 | d8f699cb | balrog | return;
|
3750 | d8f699cb | balrog | case 0x0e: /* RCR1 */ |
3751 | d8f699cb | balrog | s->rcr[0] = value & 0x7fe0; |
3752 | d8f699cb | balrog | return;
|
3753 | d8f699cb | balrog | case 0x10: /* XCR2 */ |
3754 | d8f699cb | balrog | s->xcr[1] = value & 0xffff; |
3755 | d8f699cb | balrog | return;
|
3756 | d8f699cb | balrog | case 0x12: /* XCR1 */ |
3757 | d8f699cb | balrog | s->xcr[0] = value & 0x7fe0; |
3758 | d8f699cb | balrog | return;
|
3759 | d8f699cb | balrog | case 0x14: /* SRGR2 */ |
3760 | d8f699cb | balrog | s->srgr[1] = value & 0xffff; |
3761 | 73560bc8 | balrog | omap_mcbsp_req_update(s); |
3762 | d8f699cb | balrog | return;
|
3763 | d8f699cb | balrog | case 0x16: /* SRGR1 */ |
3764 | d8f699cb | balrog | s->srgr[0] = value & 0xffff; |
3765 | 73560bc8 | balrog | omap_mcbsp_req_update(s); |
3766 | d8f699cb | balrog | return;
|
3767 | d8f699cb | balrog | case 0x18: /* MCR2 */ |
3768 | d8f699cb | balrog | s->mcr[1] = value & 0x03e3; |
3769 | d8f699cb | balrog | if (value & 3) /* XMCM */ |
3770 | d8f699cb | balrog | printf("%s: Tx channel selection mode enable attempt\n",
|
3771 | d8f699cb | balrog | __FUNCTION__); |
3772 | d8f699cb | balrog | return;
|
3773 | d8f699cb | balrog | case 0x1a: /* MCR1 */ |
3774 | d8f699cb | balrog | s->mcr[0] = value & 0x03e1; |
3775 | d8f699cb | balrog | if (value & 1) /* RMCM */ |
3776 | d8f699cb | balrog | printf("%s: Rx channel selection mode enable attempt\n",
|
3777 | d8f699cb | balrog | __FUNCTION__); |
3778 | d8f699cb | balrog | return;
|
3779 | d8f699cb | balrog | case 0x1c: /* RCERA */ |
3780 | d8f699cb | balrog | s->rcer[0] = value & 0xffff; |
3781 | d8f699cb | balrog | return;
|
3782 | d8f699cb | balrog | case 0x1e: /* RCERB */ |
3783 | d8f699cb | balrog | s->rcer[1] = value & 0xffff; |
3784 | d8f699cb | balrog | return;
|
3785 | d8f699cb | balrog | case 0x20: /* XCERA */ |
3786 | d8f699cb | balrog | s->xcer[0] = value & 0xffff; |
3787 | d8f699cb | balrog | return;
|
3788 | d8f699cb | balrog | case 0x22: /* XCERB */ |
3789 | d8f699cb | balrog | s->xcer[1] = value & 0xffff; |
3790 | d8f699cb | balrog | return;
|
3791 | d8f699cb | balrog | case 0x24: /* PCR0 */ |
3792 | d8f699cb | balrog | s->pcr = value & 0x7faf;
|
3793 | d8f699cb | balrog | return;
|
3794 | d8f699cb | balrog | case 0x26: /* RCERC */ |
3795 | d8f699cb | balrog | s->rcer[2] = value & 0xffff; |
3796 | d8f699cb | balrog | return;
|
3797 | d8f699cb | balrog | case 0x28: /* RCERD */ |
3798 | d8f699cb | balrog | s->rcer[3] = value & 0xffff; |
3799 | d8f699cb | balrog | return;
|
3800 | d8f699cb | balrog | case 0x2a: /* XCERC */ |
3801 | d8f699cb | balrog | s->xcer[2] = value & 0xffff; |
3802 | d8f699cb | balrog | return;
|
3803 | d8f699cb | balrog | case 0x2c: /* XCERD */ |
3804 | d8f699cb | balrog | s->xcer[3] = value & 0xffff; |
3805 | d8f699cb | balrog | return;
|
3806 | d8f699cb | balrog | case 0x2e: /* RCERE */ |
3807 | d8f699cb | balrog | s->rcer[4] = value & 0xffff; |
3808 | d8f699cb | balrog | return;
|
3809 | d8f699cb | balrog | case 0x30: /* RCERF */ |
3810 | d8f699cb | balrog | s->rcer[5] = value & 0xffff; |
3811 | d8f699cb | balrog | return;
|
3812 | d8f699cb | balrog | case 0x32: /* XCERE */ |
3813 | d8f699cb | balrog | s->xcer[4] = value & 0xffff; |
3814 | d8f699cb | balrog | return;
|
3815 | d8f699cb | balrog | case 0x34: /* XCERF */ |
3816 | d8f699cb | balrog | s->xcer[5] = value & 0xffff; |
3817 | d8f699cb | balrog | return;
|
3818 | d8f699cb | balrog | case 0x36: /* RCERG */ |
3819 | d8f699cb | balrog | s->rcer[6] = value & 0xffff; |
3820 | d8f699cb | balrog | return;
|
3821 | d8f699cb | balrog | case 0x38: /* RCERH */ |
3822 | d8f699cb | balrog | s->rcer[7] = value & 0xffff; |
3823 | d8f699cb | balrog | return;
|
3824 | d8f699cb | balrog | case 0x3a: /* XCERG */ |
3825 | d8f699cb | balrog | s->xcer[6] = value & 0xffff; |
3826 | d8f699cb | balrog | return;
|
3827 | d8f699cb | balrog | case 0x3c: /* XCERH */ |
3828 | d8f699cb | balrog | s->xcer[7] = value & 0xffff; |
3829 | d8f699cb | balrog | return;
|
3830 | d8f699cb | balrog | } |
3831 | d8f699cb | balrog | |
3832 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
3833 | d8f699cb | balrog | } |
3834 | d8f699cb | balrog | |
3835 | 73560bc8 | balrog | static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr, |
3836 | 73560bc8 | balrog | uint32_t value) |
3837 | 73560bc8 | balrog | { |
3838 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3839 | 73560bc8 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3840 | 73560bc8 | balrog | |
3841 | 73560bc8 | balrog | if (offset == 0x04) { /* DXR */ |
3842 | 73560bc8 | balrog | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ |
3843 | 73560bc8 | balrog | return;
|
3844 | 73560bc8 | balrog | if (s->tx_req > 3) { |
3845 | 73560bc8 | balrog | s->tx_req -= 4;
|
3846 | 73560bc8 | balrog | if (s->codec && s->codec->cts) {
|
3847 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3848 | 73560bc8 | balrog | (value >> 24) & 0xff; |
3849 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3850 | 73560bc8 | balrog | (value >> 16) & 0xff; |
3851 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3852 | 73560bc8 | balrog | (value >> 8) & 0xff; |
3853 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3854 | 73560bc8 | balrog | (value >> 0) & 0xff; |
3855 | 73560bc8 | balrog | } |
3856 | 73560bc8 | balrog | if (s->tx_req < 4) |
3857 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
3858 | 73560bc8 | balrog | } else
|
3859 | 73560bc8 | balrog | printf("%s: Tx FIFO overrun\n", __FUNCTION__);
|
3860 | 73560bc8 | balrog | return;
|
3861 | 73560bc8 | balrog | } |
3862 | 73560bc8 | balrog | |
3863 | 73560bc8 | balrog | omap_badwidth_write16(opaque, addr, value); |
3864 | 73560bc8 | balrog | } |
3865 | 73560bc8 | balrog | |
3866 | d8f699cb | balrog | static CPUReadMemoryFunc *omap_mcbsp_readfn[] = {
|
3867 | d8f699cb | balrog | omap_badwidth_read16, |
3868 | d8f699cb | balrog | omap_mcbsp_read, |
3869 | d8f699cb | balrog | omap_badwidth_read16, |
3870 | d8f699cb | balrog | }; |
3871 | d8f699cb | balrog | |
3872 | d8f699cb | balrog | static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = {
|
3873 | d8f699cb | balrog | omap_badwidth_write16, |
3874 | 73560bc8 | balrog | omap_mcbsp_writeh, |
3875 | 73560bc8 | balrog | omap_mcbsp_writew, |
3876 | d8f699cb | balrog | }; |
3877 | d8f699cb | balrog | |
3878 | d8f699cb | balrog | static void omap_mcbsp_reset(struct omap_mcbsp_s *s) |
3879 | d8f699cb | balrog | { |
3880 | d8f699cb | balrog | memset(&s->spcr, 0, sizeof(s->spcr)); |
3881 | d8f699cb | balrog | memset(&s->rcr, 0, sizeof(s->rcr)); |
3882 | d8f699cb | balrog | memset(&s->xcr, 0, sizeof(s->xcr)); |
3883 | d8f699cb | balrog | s->srgr[0] = 0x0001; |
3884 | d8f699cb | balrog | s->srgr[1] = 0x2000; |
3885 | d8f699cb | balrog | memset(&s->mcr, 0, sizeof(s->mcr)); |
3886 | d8f699cb | balrog | memset(&s->pcr, 0, sizeof(s->pcr)); |
3887 | d8f699cb | balrog | memset(&s->rcer, 0, sizeof(s->rcer)); |
3888 | d8f699cb | balrog | memset(&s->xcer, 0, sizeof(s->xcer)); |
3889 | d8f699cb | balrog | s->tx_req = 0;
|
3890 | 73560bc8 | balrog | s->rx_req = 0;
|
3891 | d8f699cb | balrog | s->tx_rate = 0;
|
3892 | d8f699cb | balrog | s->rx_rate = 0;
|
3893 | 73560bc8 | balrog | qemu_del_timer(s->source_timer); |
3894 | 73560bc8 | balrog | qemu_del_timer(s->sink_timer); |
3895 | d8f699cb | balrog | } |
3896 | d8f699cb | balrog | |
3897 | d8f699cb | balrog | struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
|
3898 | d8f699cb | balrog | qemu_irq *irq, qemu_irq *dma, omap_clk clk) |
3899 | d8f699cb | balrog | { |
3900 | d8f699cb | balrog | int iomemtype;
|
3901 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) |
3902 | d8f699cb | balrog | qemu_mallocz(sizeof(struct omap_mcbsp_s)); |
3903 | d8f699cb | balrog | |
3904 | d8f699cb | balrog | s->base = base; |
3905 | d8f699cb | balrog | s->txirq = irq[0];
|
3906 | d8f699cb | balrog | s->rxirq = irq[1];
|
3907 | d8f699cb | balrog | s->txdrq = dma[0];
|
3908 | d8f699cb | balrog | s->rxdrq = dma[1];
|
3909 | 73560bc8 | balrog | s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s); |
3910 | 73560bc8 | balrog | s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s); |
3911 | d8f699cb | balrog | omap_mcbsp_reset(s); |
3912 | d8f699cb | balrog | |
3913 | d8f699cb | balrog | iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
|
3914 | d8f699cb | balrog | omap_mcbsp_writefn, s); |
3915 | d8f699cb | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
3916 | d8f699cb | balrog | |
3917 | d8f699cb | balrog | return s;
|
3918 | d8f699cb | balrog | } |
3919 | d8f699cb | balrog | |
3920 | 9596ebb7 | pbrook | static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) |
3921 | d8f699cb | balrog | { |
3922 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3923 | d8f699cb | balrog | |
3924 | 73560bc8 | balrog | if (s->rx_rate) {
|
3925 | 73560bc8 | balrog | s->rx_req = s->codec->in.len; |
3926 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
3927 | 73560bc8 | balrog | } |
3928 | d8f699cb | balrog | } |
3929 | d8f699cb | balrog | |
3930 | 9596ebb7 | pbrook | static void omap_mcbsp_i2s_start(void *opaque, int line, int level) |
3931 | d8f699cb | balrog | { |
3932 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3933 | d8f699cb | balrog | |
3934 | 73560bc8 | balrog | if (s->tx_rate) {
|
3935 | 73560bc8 | balrog | s->tx_req = s->codec->out.size; |
3936 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
3937 | 73560bc8 | balrog | } |
3938 | d8f699cb | balrog | } |
3939 | d8f699cb | balrog | |
3940 | d8f699cb | balrog | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave) |
3941 | d8f699cb | balrog | { |
3942 | d8f699cb | balrog | s->codec = slave; |
3943 | d8f699cb | balrog | slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0]; |
3944 | d8f699cb | balrog | slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0]; |
3945 | d8f699cb | balrog | } |
3946 | d8f699cb | balrog | |
3947 | f9d43072 | balrog | /* LED Pulse Generators */
|
3948 | f9d43072 | balrog | struct omap_lpg_s {
|
3949 | f9d43072 | balrog | target_phys_addr_t base; |
3950 | f9d43072 | balrog | QEMUTimer *tm; |
3951 | f9d43072 | balrog | |
3952 | f9d43072 | balrog | uint8_t control; |
3953 | f9d43072 | balrog | uint8_t power; |
3954 | f9d43072 | balrog | int64_t on; |
3955 | f9d43072 | balrog | int64_t period; |
3956 | f9d43072 | balrog | int clk;
|
3957 | f9d43072 | balrog | int cycle;
|
3958 | f9d43072 | balrog | }; |
3959 | f9d43072 | balrog | |
3960 | f9d43072 | balrog | static void omap_lpg_tick(void *opaque) |
3961 | f9d43072 | balrog | { |
3962 | f9d43072 | balrog | struct omap_lpg_s *s = opaque;
|
3963 | f9d43072 | balrog | |
3964 | f9d43072 | balrog | if (s->cycle)
|
3965 | f9d43072 | balrog | qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on); |
3966 | f9d43072 | balrog | else
|
3967 | f9d43072 | balrog | qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on); |
3968 | f9d43072 | balrog | |
3969 | f9d43072 | balrog | s->cycle = !s->cycle; |
3970 | f9d43072 | balrog | printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); |
3971 | f9d43072 | balrog | } |
3972 | f9d43072 | balrog | |
3973 | f9d43072 | balrog | static void omap_lpg_update(struct omap_lpg_s *s) |
3974 | f9d43072 | balrog | { |
3975 | f9d43072 | balrog | int64_t on, period = 1, ticks = 1000; |
3976 | f9d43072 | balrog | static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; |
3977 | f9d43072 | balrog | |
3978 | f9d43072 | balrog | if (~s->control & (1 << 6)) /* LPGRES */ |
3979 | f9d43072 | balrog | on = 0;
|
3980 | f9d43072 | balrog | else if (s->control & (1 << 7)) /* PERM_ON */ |
3981 | f9d43072 | balrog | on = period; |
3982 | f9d43072 | balrog | else {
|
3983 | f9d43072 | balrog | period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ |
3984 | f9d43072 | balrog | 256 / 32); |
3985 | f9d43072 | balrog | on = (s->clk && s->power) ? muldiv64(ticks, |
3986 | f9d43072 | balrog | per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ |
3987 | f9d43072 | balrog | } |
3988 | f9d43072 | balrog | |
3989 | f9d43072 | balrog | qemu_del_timer(s->tm); |
3990 | f9d43072 | balrog | if (on == period && s->on < s->period)
|
3991 | f9d43072 | balrog | printf("%s: LED is on\n", __FUNCTION__);
|
3992 | f9d43072 | balrog | else if (on == 0 && s->on) |
3993 | f9d43072 | balrog | printf("%s: LED is off\n", __FUNCTION__);
|
3994 | f9d43072 | balrog | else if (on && (on != s->on || period != s->period)) { |
3995 | f9d43072 | balrog | s->cycle = 0;
|
3996 | f9d43072 | balrog | s->on = on; |
3997 | f9d43072 | balrog | s->period = period; |
3998 | f9d43072 | balrog | omap_lpg_tick(s); |
3999 | f9d43072 | balrog | return;
|
4000 | f9d43072 | balrog | } |
4001 | f9d43072 | balrog | |
4002 | f9d43072 | balrog | s->on = on; |
4003 | f9d43072 | balrog | s->period = period; |
4004 | f9d43072 | balrog | } |
4005 | f9d43072 | balrog | |
4006 | f9d43072 | balrog | static void omap_lpg_reset(struct omap_lpg_s *s) |
4007 | f9d43072 | balrog | { |
4008 | f9d43072 | balrog | s->control = 0x00;
|
4009 | f9d43072 | balrog | s->power = 0x00;
|
4010 | f9d43072 | balrog | s->clk = 1;
|
4011 | f9d43072 | balrog | omap_lpg_update(s); |
4012 | f9d43072 | balrog | } |
4013 | f9d43072 | balrog | |
4014 | f9d43072 | balrog | static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr) |
4015 | f9d43072 | balrog | { |
4016 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
4017 | f9d43072 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
4018 | f9d43072 | balrog | |
4019 | f9d43072 | balrog | switch (offset) {
|
4020 | f9d43072 | balrog | case 0x00: /* LCR */ |
4021 | f9d43072 | balrog | return s->control;
|
4022 | f9d43072 | balrog | |
4023 | f9d43072 | balrog | case 0x04: /* PMR */ |
4024 | f9d43072 | balrog | return s->power;
|
4025 | f9d43072 | balrog | } |
4026 | f9d43072 | balrog | |
4027 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
4028 | f9d43072 | balrog | return 0; |
4029 | f9d43072 | balrog | } |
4030 | f9d43072 | balrog | |
4031 | f9d43072 | balrog | static void omap_lpg_write(void *opaque, target_phys_addr_t addr, |
4032 | f9d43072 | balrog | uint32_t value) |
4033 | f9d43072 | balrog | { |
4034 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
4035 | f9d43072 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
4036 | f9d43072 | balrog | |
4037 | f9d43072 | balrog | switch (offset) {
|
4038 | f9d43072 | balrog | case 0x00: /* LCR */ |
4039 | f9d43072 | balrog | if (~value & (1 << 6)) /* LPGRES */ |
4040 | f9d43072 | balrog | omap_lpg_reset(s); |
4041 | f9d43072 | balrog | s->control = value & 0xff;
|
4042 | f9d43072 | balrog | omap_lpg_update(s); |
4043 | f9d43072 | balrog | return;
|
4044 | f9d43072 | balrog | |
4045 | f9d43072 | balrog | case 0x04: /* PMR */ |
4046 | f9d43072 | balrog | s->power = value & 0x01;
|
4047 | f9d43072 | balrog | omap_lpg_update(s); |
4048 | f9d43072 | balrog | return;
|
4049 | f9d43072 | balrog | |
4050 | f9d43072 | balrog | default:
|
4051 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
4052 | f9d43072 | balrog | return;
|
4053 | f9d43072 | balrog | } |
4054 | f9d43072 | balrog | } |
4055 | f9d43072 | balrog | |
4056 | f9d43072 | balrog | static CPUReadMemoryFunc *omap_lpg_readfn[] = {
|
4057 | f9d43072 | balrog | omap_lpg_read, |
4058 | f9d43072 | balrog | omap_badwidth_read8, |
4059 | f9d43072 | balrog | omap_badwidth_read8, |
4060 | f9d43072 | balrog | }; |
4061 | f9d43072 | balrog | |
4062 | f9d43072 | balrog | static CPUWriteMemoryFunc *omap_lpg_writefn[] = {
|
4063 | f9d43072 | balrog | omap_lpg_write, |
4064 | f9d43072 | balrog | omap_badwidth_write8, |
4065 | f9d43072 | balrog | omap_badwidth_write8, |
4066 | f9d43072 | balrog | }; |
4067 | f9d43072 | balrog | |
4068 | f9d43072 | balrog | static void omap_lpg_clk_update(void *opaque, int line, int on) |
4069 | f9d43072 | balrog | { |
4070 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
4071 | f9d43072 | balrog | |
4072 | f9d43072 | balrog | s->clk = on; |
4073 | f9d43072 | balrog | omap_lpg_update(s); |
4074 | f9d43072 | balrog | } |
4075 | f9d43072 | balrog | |
4076 | f9d43072 | balrog | struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
|
4077 | f9d43072 | balrog | { |
4078 | f9d43072 | balrog | int iomemtype;
|
4079 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) |
4080 | f9d43072 | balrog | qemu_mallocz(sizeof(struct omap_lpg_s)); |
4081 | f9d43072 | balrog | |
4082 | f9d43072 | balrog | s->base = base; |
4083 | f9d43072 | balrog | s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s); |
4084 | f9d43072 | balrog | |
4085 | f9d43072 | balrog | omap_lpg_reset(s); |
4086 | f9d43072 | balrog | |
4087 | f9d43072 | balrog | iomemtype = cpu_register_io_memory(0, omap_lpg_readfn,
|
4088 | f9d43072 | balrog | omap_lpg_writefn, s); |
4089 | f9d43072 | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
4090 | f9d43072 | balrog | |
4091 | f9d43072 | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]); |
4092 | f9d43072 | balrog | |
4093 | f9d43072 | balrog | return s;
|
4094 | f9d43072 | balrog | } |
4095 | f9d43072 | balrog | |
4096 | f9d43072 | balrog | /* MPUI Peripheral Bridge configuration */
|
4097 | f9d43072 | balrog | static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr) |
4098 | f9d43072 | balrog | { |
4099 | f9d43072 | balrog | if (addr == OMAP_MPUI_BASE) /* CMR */ |
4100 | f9d43072 | balrog | return 0xfe4d; |
4101 | f9d43072 | balrog | |
4102 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
4103 | f9d43072 | balrog | return 0; |
4104 | f9d43072 | balrog | } |
4105 | f9d43072 | balrog | |
4106 | f9d43072 | balrog | static CPUReadMemoryFunc *omap_mpui_io_readfn[] = {
|
4107 | f9d43072 | balrog | omap_badwidth_read16, |
4108 | f9d43072 | balrog | omap_mpui_io_read, |
4109 | f9d43072 | balrog | omap_badwidth_read16, |
4110 | f9d43072 | balrog | }; |
4111 | f9d43072 | balrog | |
4112 | f9d43072 | balrog | static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = {
|
4113 | f9d43072 | balrog | omap_badwidth_write16, |
4114 | f9d43072 | balrog | omap_badwidth_write16, |
4115 | f9d43072 | balrog | omap_badwidth_write16, |
4116 | f9d43072 | balrog | }; |
4117 | f9d43072 | balrog | |
4118 | f9d43072 | balrog | static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu) |
4119 | f9d43072 | balrog | { |
4120 | f9d43072 | balrog | int iomemtype = cpu_register_io_memory(0, omap_mpui_io_readfn, |
4121 | f9d43072 | balrog | omap_mpui_io_writefn, mpu); |
4122 | f9d43072 | balrog | cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
|
4123 | f9d43072 | balrog | } |
4124 | f9d43072 | balrog | |
4125 | c3d2689d | balrog | /* General chip reset */
|
4126 | c3d2689d | balrog | static void omap_mpu_reset(void *opaque) |
4127 | c3d2689d | balrog | { |
4128 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
4129 | c3d2689d | balrog | |
4130 | c3d2689d | balrog | omap_inth_reset(mpu->ih[0]);
|
4131 | c3d2689d | balrog | omap_inth_reset(mpu->ih[1]);
|
4132 | c3d2689d | balrog | omap_dma_reset(mpu->dma); |
4133 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[0]);
|
4134 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[1]);
|
4135 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[2]);
|
4136 | c3d2689d | balrog | omap_wd_timer_reset(mpu->wdt); |
4137 | c3d2689d | balrog | omap_os_timer_reset(mpu->os_timer); |
4138 | c3d2689d | balrog | omap_lcdc_reset(mpu->lcd); |
4139 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
4140 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
4141 | c3d2689d | balrog | omap_mpui_reset(mpu); |
4142 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->private_tipb); |
4143 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->public_tipb); |
4144 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[0]);
|
4145 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[1]);
|
4146 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[2]);
|
4147 | d951f6ff | balrog | omap_uart_reset(mpu->uart[0]);
|
4148 | d951f6ff | balrog | omap_uart_reset(mpu->uart[1]);
|
4149 | d951f6ff | balrog | omap_uart_reset(mpu->uart[2]);
|
4150 | b30bb3a2 | balrog | omap_mmc_reset(mpu->mmc); |
4151 | fe71e81a | balrog | omap_mpuio_reset(mpu->mpuio); |
4152 | 64330148 | balrog | omap_gpio_reset(mpu->gpio); |
4153 | d951f6ff | balrog | omap_uwire_reset(mpu->microwire); |
4154 | 66450b15 | balrog | omap_pwl_reset(mpu); |
4155 | 4a2c8ac2 | balrog | omap_pwt_reset(mpu); |
4156 | 4a2c8ac2 | balrog | omap_i2c_reset(mpu->i2c); |
4157 | 5c1c390f | balrog | omap_rtc_reset(mpu->rtc); |
4158 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp1); |
4159 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp2); |
4160 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp3); |
4161 | f9d43072 | balrog | omap_lpg_reset(mpu->led[0]);
|
4162 | f9d43072 | balrog | omap_lpg_reset(mpu->led[1]);
|
4163 | 8ef6367e | balrog | omap_clkm_reset(mpu); |
4164 | c3d2689d | balrog | cpu_reset(mpu->env); |
4165 | c3d2689d | balrog | } |
4166 | c3d2689d | balrog | |
4167 | cf965d24 | balrog | static const struct omap_map_s { |
4168 | cf965d24 | balrog | target_phys_addr_t phys_dsp; |
4169 | cf965d24 | balrog | target_phys_addr_t phys_mpu; |
4170 | cf965d24 | balrog | uint32_t size; |
4171 | cf965d24 | balrog | const char *name; |
4172 | cf965d24 | balrog | } omap15xx_dsp_mm[] = { |
4173 | cf965d24 | balrog | /* Strobe 0 */
|
4174 | cf965d24 | balrog | { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ |
4175 | cf965d24 | balrog | { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ |
4176 | cf965d24 | balrog | { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ |
4177 | cf965d24 | balrog | { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ |
4178 | cf965d24 | balrog | { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ |
4179 | cf965d24 | balrog | { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ |
4180 | cf965d24 | balrog | { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ |
4181 | cf965d24 | balrog | { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ |
4182 | cf965d24 | balrog | { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ |
4183 | cf965d24 | balrog | { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ |
4184 | cf965d24 | balrog | { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ |
4185 | cf965d24 | balrog | { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ |
4186 | cf965d24 | balrog | { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ |
4187 | cf965d24 | balrog | { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ |
4188 | cf965d24 | balrog | { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ |
4189 | cf965d24 | balrog | { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ |
4190 | cf965d24 | balrog | { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ |
4191 | cf965d24 | balrog | /* Strobe 1 */
|
4192 | cf965d24 | balrog | { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ |
4193 | cf965d24 | balrog | |
4194 | cf965d24 | balrog | { 0 }
|
4195 | cf965d24 | balrog | }; |
4196 | cf965d24 | balrog | |
4197 | cf965d24 | balrog | static void omap_setup_dsp_mapping(const struct omap_map_s *map) |
4198 | cf965d24 | balrog | { |
4199 | cf965d24 | balrog | int io;
|
4200 | cf965d24 | balrog | |
4201 | cf965d24 | balrog | for (; map->phys_dsp; map ++) {
|
4202 | cf965d24 | balrog | io = cpu_get_physical_page_desc(map->phys_mpu); |
4203 | cf965d24 | balrog | |
4204 | cf965d24 | balrog | cpu_register_physical_memory(map->phys_dsp, map->size, io); |
4205 | cf965d24 | balrog | } |
4206 | cf965d24 | balrog | } |
4207 | cf965d24 | balrog | |
4208 | c3d2689d | balrog | static void omap_mpu_wakeup(void *opaque, int irq, int req) |
4209 | c3d2689d | balrog | { |
4210 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
4211 | c3d2689d | balrog | |
4212 | fe71e81a | balrog | if (mpu->env->halted)
|
4213 | fe71e81a | balrog | cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); |
4214 | c3d2689d | balrog | } |
4215 | c3d2689d | balrog | |
4216 | 089b7c0a | balrog | static const struct dma_irq_map omap_dma_irq_map[] = { |
4217 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH0_6 },
|
4218 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH1_7 },
|
4219 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH2_8 },
|
4220 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH3 },
|
4221 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH4 },
|
4222 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH5 },
|
4223 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH6 },
|
4224 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH7 },
|
4225 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH8 },
|
4226 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH9 },
|
4227 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH10 },
|
4228 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH11 },
|
4229 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH12 },
|
4230 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH13 },
|
4231 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH14 },
|
4232 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH15 }
|
4233 | 089b7c0a | balrog | }; |
4234 | 089b7c0a | balrog | |
4235 | b4e3104b | balrog | /* DMA ports for OMAP1 */
|
4236 | b4e3104b | balrog | static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, |
4237 | b4e3104b | balrog | target_phys_addr_t addr) |
4238 | b4e3104b | balrog | { |
4239 | b4e3104b | balrog | return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
|
4240 | b4e3104b | balrog | } |
4241 | b4e3104b | balrog | |
4242 | b4e3104b | balrog | static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, |
4243 | b4e3104b | balrog | target_phys_addr_t addr) |
4244 | b4e3104b | balrog | { |
4245 | b4e3104b | balrog | return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
|
4246 | b4e3104b | balrog | } |
4247 | b4e3104b | balrog | |
4248 | b4e3104b | balrog | static int omap_validate_imif_addr(struct omap_mpu_state_s *s, |
4249 | b4e3104b | balrog | target_phys_addr_t addr) |
4250 | b4e3104b | balrog | { |
4251 | b4e3104b | balrog | return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
|
4252 | b4e3104b | balrog | } |
4253 | b4e3104b | balrog | |
4254 | b4e3104b | balrog | static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, |
4255 | b4e3104b | balrog | target_phys_addr_t addr) |
4256 | b4e3104b | balrog | { |
4257 | b4e3104b | balrog | return addr >= 0xfffb0000 && addr < 0xffff0000; |
4258 | b4e3104b | balrog | } |
4259 | b4e3104b | balrog | |
4260 | b4e3104b | balrog | static int omap_validate_local_addr(struct omap_mpu_state_s *s, |
4261 | b4e3104b | balrog | target_phys_addr_t addr) |
4262 | b4e3104b | balrog | { |
4263 | b4e3104b | balrog | return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000; |
4264 | b4e3104b | balrog | } |
4265 | b4e3104b | balrog | |
4266 | b4e3104b | balrog | static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, |
4267 | b4e3104b | balrog | target_phys_addr_t addr) |
4268 | b4e3104b | balrog | { |
4269 | b4e3104b | balrog | return addr >= 0xe1010000 && addr < 0xe1020004; |
4270 | b4e3104b | balrog | } |
4271 | b4e3104b | balrog | |
4272 | c3d2689d | balrog | struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
4273 | c3d2689d | balrog | DisplayState *ds, const char *core) |
4274 | c3d2689d | balrog | { |
4275 | 089b7c0a | balrog | int i;
|
4276 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
4277 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
4278 | c3d2689d | balrog | ram_addr_t imif_base, emiff_base; |
4279 | 106627d0 | balrog | qemu_irq *cpu_irq; |
4280 | 089b7c0a | balrog | qemu_irq dma_irqs[6];
|
4281 | 9d413d1d | balrog | int sdindex;
|
4282 | 106627d0 | balrog | |
4283 | aaed909a | bellard | if (!core)
|
4284 | aaed909a | bellard | core = "ti925t";
|
4285 | c3d2689d | balrog | |
4286 | c3d2689d | balrog | /* Core */
|
4287 | c3d2689d | balrog | s->mpu_model = omap310; |
4288 | aaed909a | bellard | s->env = cpu_init(core); |
4289 | aaed909a | bellard | if (!s->env) {
|
4290 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
|
4291 | aaed909a | bellard | exit(1);
|
4292 | aaed909a | bellard | } |
4293 | c3d2689d | balrog | s->sdram_size = sdram_size; |
4294 | c3d2689d | balrog | s->sram_size = OMAP15XX_SRAM_SIZE; |
4295 | c3d2689d | balrog | |
4296 | fe71e81a | balrog | s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
4297 | fe71e81a | balrog | |
4298 | c3d2689d | balrog | /* Clocks */
|
4299 | c3d2689d | balrog | omap_clk_init(s); |
4300 | c3d2689d | balrog | |
4301 | c3d2689d | balrog | /* Memory-mapped stuff */
|
4302 | c3d2689d | balrog | cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size, |
4303 | c3d2689d | balrog | (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
4304 | c3d2689d | balrog | cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size, |
4305 | c3d2689d | balrog | (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); |
4306 | c3d2689d | balrog | |
4307 | c3d2689d | balrog | omap_clkm_init(0xfffece00, 0xe1008000, s); |
4308 | c3d2689d | balrog | |
4309 | 106627d0 | balrog | cpu_irq = arm_pic_init_cpu(s->env); |
4310 | 106627d0 | balrog | s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, |
4311 | 106627d0 | balrog | cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ], |
4312 | c3d2689d | balrog | omap_findclk(s, "arminth_ck"));
|
4313 | 106627d0 | balrog | s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, |
4314 | 106627d0 | balrog | s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL, |
4315 | c3d2689d | balrog | omap_findclk(s, "arminth_ck"));
|
4316 | c3d2689d | balrog | s->irq[0] = s->ih[0]->pins; |
4317 | c3d2689d | balrog | s->irq[1] = s->ih[1]->pins; |
4318 | c3d2689d | balrog | |
4319 | 089b7c0a | balrog | for (i = 0; i < 6; i ++) |
4320 | 089b7c0a | balrog | dma_irqs[i] = s->irq[omap_dma_irq_map[i].ih][omap_dma_irq_map[i].intr]; |
4321 | 089b7c0a | balrog | s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD], |
4322 | 089b7c0a | balrog | s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
|
4323 | 089b7c0a | balrog | |
4324 | c3d2689d | balrog | s->port[emiff ].addr_valid = omap_validate_emiff_addr; |
4325 | c3d2689d | balrog | s->port[emifs ].addr_valid = omap_validate_emifs_addr; |
4326 | c3d2689d | balrog | s->port[imif ].addr_valid = omap_validate_imif_addr; |
4327 | c3d2689d | balrog | s->port[tipb ].addr_valid = omap_validate_tipb_addr; |
4328 | c3d2689d | balrog | s->port[local ].addr_valid = omap_validate_local_addr; |
4329 | c3d2689d | balrog | s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; |
4330 | c3d2689d | balrog | |
4331 | c3d2689d | balrog | s->timer[0] = omap_mpu_timer_init(0xfffec500, |
4332 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER1],
|
4333 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
4334 | c3d2689d | balrog | s->timer[1] = omap_mpu_timer_init(0xfffec600, |
4335 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER2],
|
4336 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
4337 | c3d2689d | balrog | s->timer[2] = omap_mpu_timer_init(0xfffec700, |
4338 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER3],
|
4339 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
4340 | c3d2689d | balrog | |
4341 | c3d2689d | balrog | s->wdt = omap_wd_timer_init(0xfffec800,
|
4342 | c3d2689d | balrog | s->irq[0][OMAP_INT_WD_TIMER],
|
4343 | c3d2689d | balrog | omap_findclk(s, "armwdt_ck"));
|
4344 | c3d2689d | balrog | |
4345 | c3d2689d | balrog | s->os_timer = omap_os_timer_init(0xfffb9000,
|
4346 | c3d2689d | balrog | s->irq[1][OMAP_INT_OS_TIMER],
|
4347 | c3d2689d | balrog | omap_findclk(s, "clk32-kHz"));
|
4348 | c3d2689d | balrog | |
4349 | c3d2689d | balrog | s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL], |
4350 | b4e3104b | balrog | omap_dma_get_lcdch(s->dma), ds, imif_base, emiff_base, |
4351 | c3d2689d | balrog | omap_findclk(s, "lcd_ck"));
|
4352 | c3d2689d | balrog | |
4353 | c3d2689d | balrog | omap_ulpd_pm_init(0xfffe0800, s);
|
4354 | c3d2689d | balrog | omap_pin_cfg_init(0xfffe1000, s);
|
4355 | c3d2689d | balrog | omap_id_init(s); |
4356 | c3d2689d | balrog | |
4357 | c3d2689d | balrog | omap_mpui_init(0xfffec900, s);
|
4358 | c3d2689d | balrog | |
4359 | c3d2689d | balrog | s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
|
4360 | c3d2689d | balrog | s->irq[0][OMAP_INT_BRIDGE_PRIV],
|
4361 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
4362 | c3d2689d | balrog | s->public_tipb = omap_tipb_bridge_init(0xfffed300,
|
4363 | c3d2689d | balrog | s->irq[0][OMAP_INT_BRIDGE_PUB],
|
4364 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
4365 | c3d2689d | balrog | |
4366 | c3d2689d | balrog | omap_tcmi_init(0xfffecc00, s);
|
4367 | c3d2689d | balrog | |
4368 | d951f6ff | balrog | s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1], |
4369 | c3d2689d | balrog | omap_findclk(s, "uart1_ck"),
|
4370 | c3d2689d | balrog | serial_hds[0]);
|
4371 | d951f6ff | balrog | s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2], |
4372 | c3d2689d | balrog | omap_findclk(s, "uart2_ck"),
|
4373 | c3d2689d | balrog | serial_hds[0] ? serial_hds[1] : 0); |
4374 | d951f6ff | balrog | s->uart[2] = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3], |
4375 | c3d2689d | balrog | omap_findclk(s, "uart3_ck"),
|
4376 | c3d2689d | balrog | serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0); |
4377 | c3d2689d | balrog | |
4378 | c3d2689d | balrog | omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1")); |
4379 | c3d2689d | balrog | omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2")); |
4380 | c3d2689d | balrog | omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3")); |
4381 | c3d2689d | balrog | |
4382 | 9d413d1d | balrog | sdindex = drive_get_index(IF_SD, 0, 0); |
4383 | 9d413d1d | balrog | if (sdindex == -1) { |
4384 | e4bcb14c | ths | fprintf(stderr, "qemu: missing SecureDigital device\n");
|
4385 | e4bcb14c | ths | exit(1);
|
4386 | e4bcb14c | ths | } |
4387 | 9d413d1d | balrog | s->mmc = omap_mmc_init(0xfffb7800, drives_table[sdindex].bdrv,
|
4388 | 9d413d1d | balrog | s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
|
4389 | 9d413d1d | balrog | omap_findclk(s, "mmc_ck"));
|
4390 | b30bb3a2 | balrog | |
4391 | fe71e81a | balrog | s->mpuio = omap_mpuio_init(0xfffb5000,
|
4392 | fe71e81a | balrog | s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO], |
4393 | fe71e81a | balrog | s->wakeup, omap_findclk(s, "clk32-kHz"));
|
4394 | fe71e81a | balrog | |
4395 | 3efda49d | balrog | s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1], |
4396 | 66450b15 | balrog | omap_findclk(s, "arm_gpio_ck"));
|
4397 | 64330148 | balrog | |
4398 | d951f6ff | balrog | s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX], |
4399 | d951f6ff | balrog | s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
|
4400 | d951f6ff | balrog | |
4401 | d8f699cb | balrog | omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck")); |
4402 | d8f699cb | balrog | omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck")); |
4403 | 66450b15 | balrog | |
4404 | 4a2c8ac2 | balrog | s->i2c = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C], |
4405 | 4a2c8ac2 | balrog | &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
|
4406 | 4a2c8ac2 | balrog | |
4407 | 5c1c390f | balrog | s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER], |
4408 | 5c1c390f | balrog | omap_findclk(s, "clk32-kHz"));
|
4409 | 02645926 | balrog | |
4410 | d8f699cb | balrog | s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX], |
4411 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
|
4412 | d8f699cb | balrog | s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX], |
4413 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
|
4414 | d8f699cb | balrog | s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX], |
4415 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
|
4416 | d8f699cb | balrog | |
4417 | f9d43072 | balrog | s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz")); |
4418 | f9d43072 | balrog | s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz")); |
4419 | f9d43072 | balrog | |
4420 | 02645926 | balrog | /* Register mappings not currenlty implemented:
|
4421 | 02645926 | balrog | * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
|
4422 | 02645926 | balrog | * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
|
4423 | 02645926 | balrog | * USB W2FC fffb4000 - fffb47ff
|
4424 | 02645926 | balrog | * Camera Interface fffb6800 - fffb6fff
|
4425 | 02645926 | balrog | * USB Host fffba000 - fffba7ff
|
4426 | 02645926 | balrog | * FAC fffba800 - fffbafff
|
4427 | 02645926 | balrog | * HDQ/1-Wire fffbc000 - fffbc7ff
|
4428 | b854bc19 | balrog | * TIPB switches fffbc800 - fffbcfff
|
4429 | 02645926 | balrog | * Mailbox fffcf000 - fffcf7ff
|
4430 | 02645926 | balrog | * Local bus IF fffec100 - fffec1ff
|
4431 | 02645926 | balrog | * Local bus MMU fffec200 - fffec2ff
|
4432 | 02645926 | balrog | * DSP MMU fffed200 - fffed2ff
|
4433 | 02645926 | balrog | */
|
4434 | 02645926 | balrog | |
4435 | cf965d24 | balrog | omap_setup_dsp_mapping(omap15xx_dsp_mm); |
4436 | f9d43072 | balrog | omap_setup_mpui_io(s); |
4437 | cf965d24 | balrog | |
4438 | c3d2689d | balrog | qemu_register_reset(omap_mpu_reset, s); |
4439 | c3d2689d | balrog | |
4440 | c3d2689d | balrog | return s;
|
4441 | c3d2689d | balrog | } |