Archipelago » qemu

#define PC_I440FX_1_7_MACHINE_OPTIONS PC_I440FX_MACHINE_OPTIONS

static QEMUMachine pc_i440fx_machine_v1_7 = {

    PC_I440FX_1_7_MACHINE_OPTIONS,

    .name = "pc-i440fx-1.7",

    .alias = "pc",

    .init = pc_init_pci,

    .is_default = 1,

};

    .compat_props = (GlobalProperty[]) {

        PC_COMPAT_1_6,

        { /* end of list */ }

    },

    qemu_register_machine(&pc_i440fx_machine_v1_7);

#define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS

static QEMUMachine pc_q35_machine_v1_7 = {

    PC_Q35_1_7_MACHINE_OPTIONS,

    .name = "pc-q35-1.7",

    .alias = "q35",

    .init = pc_q35_init,

};

    .compat_props = (GlobalProperty[]) {

        PC_COMPAT_1_6,

        { /* end of list */ }

    },

    qemu_register_machine(&pc_q35_machine_v1_7);

    QEMUTimer *mit_timer;      /* Mitigation timer. */

    bool mit_timer_on;         /* Mitigation timer is running. */

    bool mit_irq_level;        /* Tracks interrupt pin level. */

    uint32_t mit_ide;          /* Tracks E1000_TXD_CMD_IDE bit. */

#define E1000_FLAG_MIT_BIT 1

#define E1000_FLAG_MIT (1 << E1000_FLAG_MIT_BIT)

    defreg(VET),        defreg(RDTR),   defreg(RADV),   defreg(TADV),

    defreg(ITR),

/* Helper function, *curr == 0 means the value is not set */

static inline void

mit_update_delay(uint32_t *curr, uint32_t value)

{

    if (value && (*curr == 0 || value < *curr)) {

        *curr = value;

    }

}

    uint32_t pending_ints;

    uint32_t mit_delay;

    pending_ints = (s->mac_reg[IMS] & s->mac_reg[ICR]);

    if (!s->mit_irq_level && pending_ints) {

        /*

         * Here we detect a potential raising edge. We postpone raising the

         * interrupt line if we are inside the mitigation delay window

         * (s->mit_timer_on == 1).

         * We provide a partial implementation of interrupt mitigation,

         * emulating only RADV, TADV and ITR (lower 16 bits, 1024ns units for

         * RADV and TADV, 256ns units for ITR). RDTR is only used to enable

         * RADV; relative timers based on TIDV and RDTR are not implemented.

         */

        if (s->mit_timer_on) {

            return;

        }

        if (s->compat_flags & E1000_FLAG_MIT) {

            /* Compute the next mitigation delay according to pending

             * interrupts and the current values of RADV (provided

             * RDTR!=0), TADV and ITR.

             * Then rearm the timer.

             */

            mit_delay = 0;

            if (s->mit_ide &&

                    (pending_ints & (E1000_ICR_TXQE | E1000_ICR_TXDW))) {

                mit_update_delay(&mit_delay, s->mac_reg[TADV] * 4);

            }

            if (s->mac_reg[RDTR] && (pending_ints & E1000_ICS_RXT0)) {

                mit_update_delay(&mit_delay, s->mac_reg[RADV] * 4);

            }

            mit_update_delay(&mit_delay, s->mac_reg[ITR]);

            if (mit_delay) {

                s->mit_timer_on = 1;

                timer_mod(s->mit_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +

                          mit_delay * 256);

            }

            s->mit_ide = 0;

        }

    }

    s->mit_irq_level = (pending_ints != 0);

    qemu_set_irq(d->irq[0], s->mit_irq_level);

}

static void

e1000_mit_timer(void *opaque)

{

    E1000State *s = opaque;

    s->mit_timer_on = 0;

    /* Call set_interrupt_cause to update the irq level (if necessary). */

    set_interrupt_cause(s, 0, s->mac_reg[ICR]);

    timer_del(d->mit_timer);

    d->mit_timer_on = 0;

    d->mit_irq_level = 0;

    d->mit_ide = 0;

    s->mit_ide |= (txd_lower & E1000_TXD_CMD_IDE);

    getreg(TDLEN),      getreg(RDLEN),  getreg(RDTR),   getreg(RADV),

    getreg(TADV),       getreg(ITR),

    [RDTR] = set_16bit, [RADV] = set_16bit,     [TADV] = set_16bit,

    [ITR] = set_16bit,

    /* If the mitigation timer is active, emulate a timeout now. */

    if (s->mit_timer_on) {

        e1000_mit_timer(s);

    }

    if (!(s->compat_flags & E1000_FLAG_MIT)) {

        s->mac_reg[ITR] = s->mac_reg[RDTR] = s->mac_reg[RADV] =

            s->mac_reg[TADV] = 0;

        s->mit_irq_level = false;

    }

    s->mit_ide = 0;

    s->mit_timer_on = false;

static bool e1000_mit_state_needed(void *opaque)

{

    E1000State *s = opaque;

    return s->compat_flags & E1000_FLAG_MIT;

}

static const VMStateDescription vmstate_e1000_mit_state = {

    .name = "e1000/mit_state",

    .version_id = 1,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields    = (VMStateField[]) {

        VMSTATE_UINT32(mac_reg[RDTR], E1000State),

        VMSTATE_UINT32(mac_reg[RADV], E1000State),

        VMSTATE_UINT32(mac_reg[TADV], E1000State),

        VMSTATE_UINT32(mac_reg[ITR], E1000State),

        VMSTATE_BOOL(mit_irq_level, E1000State),

        VMSTATE_END_OF_LIST()

    }

};

    },

    .subsections = (VMStateSubsection[]) {

        {

            .vmsd = &vmstate_e1000_mit_state,

            .needed = e1000_mit_state_needed,

        }, {

            /* empty */

        }

    timer_del(d->mit_timer);

    timer_free(d->mit_timer);

    d->mit_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000_mit_timer, d);

    DEFINE_PROP_BIT("mitigation", E1000State,

                    compat_flags, E1000_FLAG_MIT_BIT, true),

#define PC_COMPAT_1_6 \

        {\

            .driver   = "e1000",\

            .property = "mitigation",\

            .value    = "off",\

        }

        PC_COMPAT_1_6, \