Revision e99fd8af
| ID | e99fd8af63a1692a1159cba8fa4943f2589adf97 |
openpic: lower interrupt when reading the MSI register
This will stop things from breaking once it's properly treated as a
level-triggered interrupt. Note that it's the MPIC's MSI cascade
interrupts that are level-triggered; the individual MSIs are
edge-triggered.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
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