Revision e9aa6c21
| b/target-arm/helper.c | ||
|---|---|---|
| 56 | 56 |
return 0; |
| 57 | 57 |
} |
| 58 | 58 |
|
| 59 |
static const ARMCPRegInfo cp_reginfo[] = {
|
|
| 60 |
/* DBGDIDR: just RAZ. In particular this means the "debug architecture |
|
| 61 |
* version" bits will read as a reserved value, which should cause |
|
| 62 |
* Linux to not try to use the debug hardware. |
|
| 63 |
*/ |
|
| 64 |
{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
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|
| 65 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
|
| 66 |
REGINFO_SENTINEL |
|
| 67 |
}; |
|
| 68 |
|
|
| 69 |
static const ARMCPRegInfo v7_cp_reginfo[] = {
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|
| 70 |
/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
|
| 71 |
* debug components |
|
| 72 |
*/ |
|
| 73 |
{ .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
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|
| 74 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
|
| 75 |
{ .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
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|
| 76 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
|
| 77 |
REGINFO_SENTINEL |
|
| 78 |
}; |
|
| 79 |
|
|
| 59 | 80 |
void register_cp_regs_for_features(ARMCPU *cpu) |
| 60 | 81 |
{
|
| 61 | 82 |
/* Register all the coprocessor registers based on feature bits */ |
| ... | ... | |
| 65 | 86 |
return; |
| 66 | 87 |
} |
| 67 | 88 |
|
| 89 |
define_arm_cp_regs(cpu, cp_reginfo); |
|
| 90 |
if (arm_feature(env, ARM_FEATURE_V7)) {
|
|
| 91 |
define_arm_cp_regs(cpu, v7_cp_reginfo); |
|
| 92 |
} |
|
| 68 | 93 |
} |
| 69 | 94 |
|
| 70 | 95 |
ARMCPU *cpu_arm_init(const char *cpu_model) |
| b/target-arm/translate.c | ||
|---|---|---|
| 6364 | 6364 |
int rt = (insn >> 12) & 0xf; |
| 6365 | 6365 |
TCGv tmp; |
| 6366 | 6366 |
|
| 6367 |
/* Minimal set of debug registers, since we don't support debug */ |
|
| 6368 |
if (op1 == 0 && crn == 0 && op2 == 0) {
|
|
| 6369 |
switch (crm) {
|
|
| 6370 |
case 0: |
|
| 6371 |
/* DBGDIDR: just RAZ. In particular this means the |
|
| 6372 |
* "debug architecture version" bits will read as |
|
| 6373 |
* a reserved value, which should cause Linux to |
|
| 6374 |
* not try to use the debug hardware. |
|
| 6375 |
*/ |
|
| 6376 |
tmp = tcg_const_i32(0); |
|
| 6377 |
store_reg(s, rt, tmp); |
|
| 6378 |
return 0; |
|
| 6379 |
case 1: |
|
| 6380 |
case 2: |
|
| 6381 |
/* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we |
|
| 6382 |
* don't implement memory mapped debug components |
|
| 6383 |
*/ |
|
| 6384 |
if (ENABLE_ARCH_7) {
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|
| 6385 |
tmp = tcg_const_i32(0); |
|
| 6386 |
store_reg(s, rt, tmp); |
|
| 6387 |
return 0; |
|
| 6388 |
} |
|
| 6389 |
break; |
|
| 6390 |
default: |
|
| 6391 |
break; |
|
| 6392 |
} |
|
| 6393 |
} |
|
| 6394 |
|
|
| 6395 | 6367 |
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
|
| 6396 | 6368 |
if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
|
| 6397 | 6369 |
/* TEECR */ |
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