Revision e9aa6c21 target-arm/translate.c

b/target-arm/translate.c
6364 6364
    int rt = (insn >> 12) & 0xf;
6365 6365
    TCGv tmp;
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6367
    /* Minimal set of debug registers, since we don't support debug */
6368
    if (op1 == 0 && crn == 0 && op2 == 0) {
6369
        switch (crm) {
6370
        case 0:
6371
            /* DBGDIDR: just RAZ. In particular this means the
6372
             * "debug architecture version" bits will read as
6373
             * a reserved value, which should cause Linux to
6374
             * not try to use the debug hardware.
6375
             */
6376
            tmp = tcg_const_i32(0);
6377
            store_reg(s, rt, tmp);
6378
            return 0;
6379
        case 1:
6380
        case 2:
6381
            /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
6382
             * don't implement memory mapped debug components
6383
             */
6384
            if (ENABLE_ARCH_7) {
6385
                tmp = tcg_const_i32(0);
6386
                store_reg(s, rt, tmp);
6387
                return 0;
6388
            }
6389
            break;
6390
        default:
6391
            break;
6392
        }
6393
    }
6394

  
6395 6367
    if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
6396 6368
        if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
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            /* TEECR */

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