root / hw / arm_sysctl.c @ e9b43ea3
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1 | 5fafdf24 | ths | /*
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2 | e69954b9 | pbrook | * Status and system control registers for ARM RealView/Versatile boards.
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3 | e69954b9 | pbrook | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | e69954b9 | pbrook | * Written by Paul Brook
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6 | e69954b9 | pbrook | *
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7 | e69954b9 | pbrook | * This code is licenced under the GPL.
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8 | e69954b9 | pbrook | */
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9 | e69954b9 | pbrook | |
10 | 82634c2d | Paul Brook | #include "sysbus.h" |
11 | 9596ebb7 | pbrook | #include "primecell.h" |
12 | 87ecb68b | pbrook | #include "sysemu.h" |
13 | e69954b9 | pbrook | |
14 | e69954b9 | pbrook | #define LOCK_VALUE 0xa05f |
15 | e69954b9 | pbrook | |
16 | e69954b9 | pbrook | typedef struct { |
17 | 82634c2d | Paul Brook | SysBusDevice busdev; |
18 | e69954b9 | pbrook | uint32_t sys_id; |
19 | e69954b9 | pbrook | uint32_t leds; |
20 | e69954b9 | pbrook | uint16_t lockval; |
21 | e69954b9 | pbrook | uint32_t cfgdata1; |
22 | e69954b9 | pbrook | uint32_t cfgdata2; |
23 | e69954b9 | pbrook | uint32_t flags; |
24 | e69954b9 | pbrook | uint32_t nvflags; |
25 | e69954b9 | pbrook | uint32_t resetlevel; |
26 | e69954b9 | pbrook | } arm_sysctl_state; |
27 | e69954b9 | pbrook | |
28 | e69954b9 | pbrook | static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) |
29 | e69954b9 | pbrook | { |
30 | e69954b9 | pbrook | arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
31 | e69954b9 | pbrook | |
32 | e69954b9 | pbrook | switch (offset) {
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33 | e69954b9 | pbrook | case 0x00: /* ID */ |
34 | e69954b9 | pbrook | return s->sys_id;
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35 | e69954b9 | pbrook | case 0x04: /* SW */ |
36 | e69954b9 | pbrook | /* General purpose hardware switches.
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37 | e69954b9 | pbrook | We don't have a useful way of exposing these to the user. */
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38 | e69954b9 | pbrook | return 0; |
39 | e69954b9 | pbrook | case 0x08: /* LED */ |
40 | e69954b9 | pbrook | return s->leds;
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41 | e69954b9 | pbrook | case 0x20: /* LOCK */ |
42 | e69954b9 | pbrook | return s->lockval;
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43 | e69954b9 | pbrook | case 0x0c: /* OSC0 */ |
44 | e69954b9 | pbrook | case 0x10: /* OSC1 */ |
45 | e69954b9 | pbrook | case 0x14: /* OSC2 */ |
46 | e69954b9 | pbrook | case 0x18: /* OSC3 */ |
47 | e69954b9 | pbrook | case 0x1c: /* OSC4 */ |
48 | e69954b9 | pbrook | case 0x24: /* 100HZ */ |
49 | e69954b9 | pbrook | /* ??? Implement these. */
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50 | e69954b9 | pbrook | return 0; |
51 | e69954b9 | pbrook | case 0x28: /* CFGDATA1 */ |
52 | e69954b9 | pbrook | return s->cfgdata1;
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53 | e69954b9 | pbrook | case 0x2c: /* CFGDATA2 */ |
54 | e69954b9 | pbrook | return s->cfgdata2;
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55 | e69954b9 | pbrook | case 0x30: /* FLAGS */ |
56 | e69954b9 | pbrook | return s->flags;
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57 | e69954b9 | pbrook | case 0x38: /* NVFLAGS */ |
58 | e69954b9 | pbrook | return s->nvflags;
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59 | e69954b9 | pbrook | case 0x40: /* RESETCTL */ |
60 | e69954b9 | pbrook | return s->resetlevel;
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61 | e69954b9 | pbrook | case 0x44: /* PCICTL */ |
62 | e69954b9 | pbrook | return 1; |
63 | e69954b9 | pbrook | case 0x48: /* MCI */ |
64 | e69954b9 | pbrook | return 0; |
65 | e69954b9 | pbrook | case 0x4c: /* FLASH */ |
66 | e69954b9 | pbrook | return 0; |
67 | e69954b9 | pbrook | case 0x50: /* CLCD */ |
68 | e69954b9 | pbrook | return 0x1000; |
69 | e69954b9 | pbrook | case 0x54: /* CLCDSER */ |
70 | e69954b9 | pbrook | return 0; |
71 | e69954b9 | pbrook | case 0x58: /* BOOTCS */ |
72 | e69954b9 | pbrook | return 0; |
73 | e69954b9 | pbrook | case 0x5c: /* 24MHz */ |
74 | e69954b9 | pbrook | /* ??? not implemented. */
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75 | e69954b9 | pbrook | return 0; |
76 | e69954b9 | pbrook | case 0x60: /* MISC */ |
77 | e69954b9 | pbrook | return 0; |
78 | e69954b9 | pbrook | case 0x84: /* PROCID0 */ |
79 | e69954b9 | pbrook | /* ??? Don't know what the proper value for the core tile ID is. */
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80 | e69954b9 | pbrook | return 0x02000000; |
81 | e69954b9 | pbrook | case 0x88: /* PROCID1 */ |
82 | e69954b9 | pbrook | return 0xff000000; |
83 | e69954b9 | pbrook | case 0x64: /* DMAPSR0 */ |
84 | e69954b9 | pbrook | case 0x68: /* DMAPSR1 */ |
85 | e69954b9 | pbrook | case 0x6c: /* DMAPSR2 */ |
86 | e69954b9 | pbrook | case 0x70: /* IOSEL */ |
87 | e69954b9 | pbrook | case 0x74: /* PLDCTL */ |
88 | e69954b9 | pbrook | case 0x80: /* BUSID */ |
89 | e69954b9 | pbrook | case 0x8c: /* OSCRESET0 */ |
90 | e69954b9 | pbrook | case 0x90: /* OSCRESET1 */ |
91 | e69954b9 | pbrook | case 0x94: /* OSCRESET2 */ |
92 | e69954b9 | pbrook | case 0x98: /* OSCRESET3 */ |
93 | e69954b9 | pbrook | case 0x9c: /* OSCRESET4 */ |
94 | e69954b9 | pbrook | case 0xc0: /* SYS_TEST_OSC0 */ |
95 | e69954b9 | pbrook | case 0xc4: /* SYS_TEST_OSC1 */ |
96 | e69954b9 | pbrook | case 0xc8: /* SYS_TEST_OSC2 */ |
97 | e69954b9 | pbrook | case 0xcc: /* SYS_TEST_OSC3 */ |
98 | e69954b9 | pbrook | case 0xd0: /* SYS_TEST_OSC4 */ |
99 | e69954b9 | pbrook | return 0; |
100 | e69954b9 | pbrook | default:
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101 | e69954b9 | pbrook | printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset); |
102 | e69954b9 | pbrook | return 0; |
103 | e69954b9 | pbrook | } |
104 | e69954b9 | pbrook | } |
105 | e69954b9 | pbrook | |
106 | e69954b9 | pbrook | static void arm_sysctl_write(void *opaque, target_phys_addr_t offset, |
107 | e69954b9 | pbrook | uint32_t val) |
108 | e69954b9 | pbrook | { |
109 | e69954b9 | pbrook | arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
110 | e69954b9 | pbrook | |
111 | e69954b9 | pbrook | switch (offset) {
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112 | e69954b9 | pbrook | case 0x08: /* LED */ |
113 | e69954b9 | pbrook | s->leds = val; |
114 | e69954b9 | pbrook | case 0x0c: /* OSC0 */ |
115 | e69954b9 | pbrook | case 0x10: /* OSC1 */ |
116 | e69954b9 | pbrook | case 0x14: /* OSC2 */ |
117 | e69954b9 | pbrook | case 0x18: /* OSC3 */ |
118 | e69954b9 | pbrook | case 0x1c: /* OSC4 */ |
119 | e69954b9 | pbrook | /* ??? */
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120 | e69954b9 | pbrook | break;
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121 | e69954b9 | pbrook | case 0x20: /* LOCK */ |
122 | e69954b9 | pbrook | if (val == LOCK_VALUE)
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123 | e69954b9 | pbrook | s->lockval = val; |
124 | e69954b9 | pbrook | else
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125 | e69954b9 | pbrook | s->lockval = val & 0x7fff;
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126 | e69954b9 | pbrook | break;
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127 | e69954b9 | pbrook | case 0x28: /* CFGDATA1 */ |
128 | e69954b9 | pbrook | /* ??? Need to implement this. */
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129 | e69954b9 | pbrook | s->cfgdata1 = val; |
130 | e69954b9 | pbrook | break;
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131 | e69954b9 | pbrook | case 0x2c: /* CFGDATA2 */ |
132 | e69954b9 | pbrook | /* ??? Need to implement this. */
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133 | e69954b9 | pbrook | s->cfgdata2 = val; |
134 | e69954b9 | pbrook | break;
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135 | e69954b9 | pbrook | case 0x30: /* FLAGSSET */ |
136 | e69954b9 | pbrook | s->flags |= val; |
137 | e69954b9 | pbrook | break;
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138 | e69954b9 | pbrook | case 0x34: /* FLAGSCLR */ |
139 | e69954b9 | pbrook | s->flags &= ~val; |
140 | e69954b9 | pbrook | break;
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141 | e69954b9 | pbrook | case 0x38: /* NVFLAGSSET */ |
142 | e69954b9 | pbrook | s->nvflags |= val; |
143 | e69954b9 | pbrook | break;
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144 | e69954b9 | pbrook | case 0x3c: /* NVFLAGSCLR */ |
145 | e69954b9 | pbrook | s->nvflags &= ~val; |
146 | e69954b9 | pbrook | break;
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147 | e69954b9 | pbrook | case 0x40: /* RESETCTL */ |
148 | e69954b9 | pbrook | if (s->lockval == LOCK_VALUE) {
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149 | e69954b9 | pbrook | s->resetlevel = val; |
150 | e69954b9 | pbrook | if (val & 0x100) |
151 | f3d6b95e | pbrook | qemu_system_reset_request (); |
152 | e69954b9 | pbrook | } |
153 | e69954b9 | pbrook | break;
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154 | e69954b9 | pbrook | case 0x44: /* PCICTL */ |
155 | e69954b9 | pbrook | /* nothing to do. */
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156 | e69954b9 | pbrook | break;
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157 | e69954b9 | pbrook | case 0x4c: /* FLASH */ |
158 | e69954b9 | pbrook | case 0x50: /* CLCD */ |
159 | e69954b9 | pbrook | case 0x54: /* CLCDSER */ |
160 | e69954b9 | pbrook | case 0x64: /* DMAPSR0 */ |
161 | e69954b9 | pbrook | case 0x68: /* DMAPSR1 */ |
162 | e69954b9 | pbrook | case 0x6c: /* DMAPSR2 */ |
163 | e69954b9 | pbrook | case 0x70: /* IOSEL */ |
164 | e69954b9 | pbrook | case 0x74: /* PLDCTL */ |
165 | e69954b9 | pbrook | case 0x80: /* BUSID */ |
166 | e69954b9 | pbrook | case 0x84: /* PROCID0 */ |
167 | e69954b9 | pbrook | case 0x88: /* PROCID1 */ |
168 | e69954b9 | pbrook | case 0x8c: /* OSCRESET0 */ |
169 | e69954b9 | pbrook | case 0x90: /* OSCRESET1 */ |
170 | e69954b9 | pbrook | case 0x94: /* OSCRESET2 */ |
171 | e69954b9 | pbrook | case 0x98: /* OSCRESET3 */ |
172 | e69954b9 | pbrook | case 0x9c: /* OSCRESET4 */ |
173 | e69954b9 | pbrook | break;
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174 | e69954b9 | pbrook | default:
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175 | e69954b9 | pbrook | printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset); |
176 | e69954b9 | pbrook | return;
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177 | e69954b9 | pbrook | } |
178 | e69954b9 | pbrook | } |
179 | e69954b9 | pbrook | |
180 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const arm_sysctl_readfn[] = { |
181 | e69954b9 | pbrook | arm_sysctl_read, |
182 | e69954b9 | pbrook | arm_sysctl_read, |
183 | e69954b9 | pbrook | arm_sysctl_read |
184 | e69954b9 | pbrook | }; |
185 | e69954b9 | pbrook | |
186 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = { |
187 | e69954b9 | pbrook | arm_sysctl_write, |
188 | e69954b9 | pbrook | arm_sysctl_write, |
189 | e69954b9 | pbrook | arm_sysctl_write |
190 | e69954b9 | pbrook | }; |
191 | e69954b9 | pbrook | |
192 | 81a322d4 | Gerd Hoffmann | static int arm_sysctl_init1(SysBusDevice *dev) |
193 | e69954b9 | pbrook | { |
194 | 82634c2d | Paul Brook | arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); |
195 | e69954b9 | pbrook | int iomemtype;
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196 | e69954b9 | pbrook | |
197 | 9ee6e8bb | pbrook | /* The MPcore bootloader uses these flags to start secondary CPUs.
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198 | 9ee6e8bb | pbrook | We don't use a bootloader, so do this here. */
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199 | 9ee6e8bb | pbrook | s->flags = 3;
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200 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(arm_sysctl_readfn, |
201 | e69954b9 | pbrook | arm_sysctl_writefn, s); |
202 | 82634c2d | Paul Brook | sysbus_init_mmio(dev, 0x1000, iomemtype);
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203 | e69954b9 | pbrook | /* ??? Save/restore. */
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204 | 81a322d4 | Gerd Hoffmann | return 0; |
205 | e69954b9 | pbrook | } |
206 | 82634c2d | Paul Brook | |
207 | 82634c2d | Paul Brook | /* Legacy helper function. */
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208 | 82634c2d | Paul Brook | void arm_sysctl_init(uint32_t base, uint32_t sys_id)
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209 | 82634c2d | Paul Brook | { |
210 | 82634c2d | Paul Brook | DeviceState *dev; |
211 | 82634c2d | Paul Brook | |
212 | 82634c2d | Paul Brook | dev = qdev_create(NULL, "realview_sysctl"); |
213 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "sys_id", sys_id);
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214 | 82634c2d | Paul Brook | qdev_init(dev); |
215 | 82634c2d | Paul Brook | sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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216 | 82634c2d | Paul Brook | } |
217 | 82634c2d | Paul Brook | |
218 | ee6847d1 | Gerd Hoffmann | static SysBusDeviceInfo arm_sysctl_info = {
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219 | ee6847d1 | Gerd Hoffmann | .init = arm_sysctl_init1, |
220 | ee6847d1 | Gerd Hoffmann | .qdev.name = "realview_sysctl",
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221 | ee6847d1 | Gerd Hoffmann | .qdev.size = sizeof(arm_sysctl_state),
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222 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
223 | e325775b | Gerd Hoffmann | DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), |
224 | e325775b | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
225 | ee6847d1 | Gerd Hoffmann | } |
226 | ee6847d1 | Gerd Hoffmann | }; |
227 | ee6847d1 | Gerd Hoffmann | |
228 | 82634c2d | Paul Brook | static void arm_sysctl_register_devices(void) |
229 | 82634c2d | Paul Brook | { |
230 | ee6847d1 | Gerd Hoffmann | sysbus_register_withprop(&arm_sysctl_info); |
231 | 82634c2d | Paul Brook | } |
232 | 82634c2d | Paul Brook | |
233 | 82634c2d | Paul Brook | device_init(arm_sysctl_register_devices) |