Revision e9cd84b9
| b/target-ppc/translate_init.c | ||
|---|---|---|
| 2804 | 2804 |
#endif |
| 2805 | 2805 |
} |
| 2806 | 2806 |
|
| 2807 |
static void init_excp_e200 (CPUPPCState *env)
|
|
| 2807 |
static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
|
|
| 2808 | 2808 |
{
|
| 2809 | 2809 |
#if !defined(CONFIG_USER_ONLY) |
| 2810 | 2810 |
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; |
| ... | ... | |
| 2829 | 2829 |
env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; |
| 2830 | 2830 |
env->hreset_excp_prefix = 0x00000000UL; |
| 2831 | 2831 |
env->ivor_mask = 0x0000FFF7UL; |
| 2832 |
env->ivpr_mask = 0xFFFF0000UL;
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|
| 2832 |
env->ivpr_mask = ivpr_mask;
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|
| 2833 | 2833 |
/* Hardware reset vector */ |
| 2834 | 2834 |
env->hreset_vector = 0xFFFFFFFCUL; |
| 2835 | 2835 |
#endif |
| ... | ... | |
| 4307 | 4307 |
env->id_tlbs = 0; |
| 4308 | 4308 |
env->tlb_type = TLB_EMB; |
| 4309 | 4309 |
#endif |
| 4310 |
init_excp_e200(env); |
|
| 4310 |
init_excp_e200(env, 0xFFFF0000UL);
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|
| 4311 | 4311 |
env->dcache_line_size = 32; |
| 4312 | 4312 |
env->icache_line_size = 32; |
| 4313 | 4313 |
/* XXX: TODO: allocate internal IRQ controller */ |
| ... | ... | |
| 4434 | 4434 |
{
|
| 4435 | 4435 |
uint32_t tlbncfg[2]; |
| 4436 | 4436 |
uint64_t ivor_mask = 0x0000000F0000FFFFULL; |
| 4437 |
uint64_t ivpr_mask = 0xFFFF0000ULL; |
|
| 4437 | 4438 |
uint32_t l1cfg0 = 0x3800 /* 8 ways */ |
| 4438 | 4439 |
| 0x0020; /* 32 kb */ |
| 4439 | 4440 |
#if !defined(CONFIG_USER_ONLY) |
| ... | ... | |
| 4575 | 4576 |
} |
| 4576 | 4577 |
#endif |
| 4577 | 4578 |
|
| 4578 |
init_excp_e200(env); |
|
| 4579 |
init_excp_e200(env, ivpr_mask);
|
|
| 4579 | 4580 |
/* Allocate hardware IRQ controller */ |
| 4580 | 4581 |
ppce500_irq_init(env); |
| 4581 | 4582 |
} |
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