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/*
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 *  MIPS emulation micro-operations for qemu.
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 * 
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 *  Copyright (c) 2004-2005 Jocelyn Mayer
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 *  Copyright (c) 2006 Marius Groeger (FPU operations)
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "config.h"
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#include "exec.h"
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#ifndef CALL_FROM_TB0
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#define CALL_FROM_TB0(func) func();
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#endif
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#ifndef CALL_FROM_TB1
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#define CALL_FROM_TB1(func, arg0) func(arg0);
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#endif
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#ifndef CALL_FROM_TB1_CONST16
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#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0);
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#endif
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#ifndef CALL_FROM_TB2
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#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1);
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#endif
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#ifndef CALL_FROM_TB2_CONST16
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#define CALL_FROM_TB2_CONST16(func, arg0, arg1)     \
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CALL_FROM_TB2(func, arg0, arg1);
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#endif
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#ifndef CALL_FROM_TB3
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#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2);
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#endif
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#ifndef CALL_FROM_TB4
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#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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        func(arg0, arg1, arg2, arg3);
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#endif
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#define REG 1
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#include "op_template.c"
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#undef REG
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#define REG 2
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#include "op_template.c"
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#undef REG
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#define REG 3
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#include "op_template.c"
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#undef REG
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#define REG 4
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#include "op_template.c"
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#undef REG
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#define REG 5
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#include "op_template.c"
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#undef REG
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#define REG 6
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#include "op_template.c"
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#undef REG
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#define REG 7
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#include "op_template.c"
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#undef REG
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#define REG 8
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#include "op_template.c"
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#undef REG
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#define REG 9
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#include "op_template.c"
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#undef REG
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#define REG 10
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#include "op_template.c"
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#undef REG
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#define REG 11
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#include "op_template.c"
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#undef REG
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#define REG 12
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#include "op_template.c"
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#undef REG
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#define REG 13
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#include "op_template.c"
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#undef REG
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#define REG 14
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#include "op_template.c"
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#undef REG
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#define REG 15
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#include "op_template.c"
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#undef REG
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#define REG 16
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#include "op_template.c"
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#undef REG
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#define REG 17
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#include "op_template.c"
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#undef REG
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#define REG 18
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#include "op_template.c"
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#undef REG
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#define REG 19
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#include "op_template.c"
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#undef REG
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#define REG 20
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#include "op_template.c"
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#undef REG
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#define REG 21
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#include "op_template.c"
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#undef REG
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#define REG 22
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#include "op_template.c"
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#undef REG
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#define REG 23
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#include "op_template.c"
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#undef REG
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#define REG 24
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#include "op_template.c"
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#undef REG
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#define REG 25
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#include "op_template.c"
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#undef REG
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#define REG 26
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#include "op_template.c"
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#undef REG
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#define REG 27
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#include "op_template.c"
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#undef REG
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#define REG 28
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#include "op_template.c"
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#undef REG
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#define REG 29
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#include "op_template.c"
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#undef REG
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#define REG 30
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#include "op_template.c"
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#undef REG
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#define REG 31
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#include "op_template.c"
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#undef REG
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#define TN
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#include "op_template.c"
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#undef TN
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#define SFREG 0
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#define DFREG 0
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 1
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 2
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#define DFREG 2
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 3
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 4
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#define DFREG 4
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 5
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 6
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#define DFREG 6
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 7
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 8
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#define DFREG 8
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 9
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 10
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#define DFREG 10
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 11
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 12
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#define DFREG 12
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 13
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 14
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#define DFREG 14
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 15
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 16
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#define DFREG 16
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 17
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 18
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#define DFREG 18
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 19
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 20
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#define DFREG 20
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 21
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 22
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#define DFREG 22
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 23
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 24
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#define DFREG 24
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 25
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 26
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#define DFREG 26
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 27
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 28
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#define DFREG 28
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 29
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 30
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#define DFREG 30
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 31
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#include "fop_template.c"
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#undef SFREG
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#define FTN
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#include "fop_template.c"
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#undef FTN
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void op_dup_T0 (void)
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{
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    T2 = T0;
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    RETURN();
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}
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void op_load_HI (void)
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{
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    T0 = env->HI;
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    RETURN();
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}
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void op_store_HI (void)
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{
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    env->HI = T0;
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    RETURN();
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}
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void op_load_LO (void)
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{
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    T0 = env->LO;
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    RETURN();
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}
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void op_store_LO (void)
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{
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    env->LO = T0;
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    RETURN();
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}
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/* Load and store */
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#define MEMSUFFIX _raw
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#include "op_mem.c"
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_mem.c"
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_mem.c"
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#undef MEMSUFFIX
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#endif
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/* Arithmetic */
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void op_add (void)
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{
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    T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
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    RETURN();
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}
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void op_addo (void)
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{
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    target_ulong tmp;
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    tmp = (int32_t)T0;
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    T0 = (int32_t)T0 + (int32_t)T1;
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    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
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        /* operands of same sign, result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    T0 = (int32_t)T0;
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    RETURN();
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}
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void op_sub (void)
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{
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    T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
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    RETURN();
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}
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void op_subo (void)
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{
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    target_ulong tmp;
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    tmp = (int32_t)T0;
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    T0 = (int32_t)T0 - (int32_t)T1;
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    if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
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        /* operands of different sign, first operand and result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    T0 = (int32_t)T0;
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    RETURN();
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}
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void op_mul (void)
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{
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    T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
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    RETURN();
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}
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void op_div (void)
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{
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    if (T1 != 0) {
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        env->LO = (int32_t)((int32_t)T0 / (int32_t)T1);
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        env->HI = (int32_t)((int32_t)T0 % (int32_t)T1);
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    }
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    RETURN();
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}
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void op_divu (void)
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{
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    if (T1 != 0) {
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        env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1);
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        env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1);
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    }
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    RETURN();
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}
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#ifdef TARGET_MIPS64
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/* Arithmetic */
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void op_dadd (void)
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{
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    T0 += T1;
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    RETURN();
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}
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void op_daddo (void)
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{
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    target_long tmp;
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    tmp = T0;
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    T0 += T1;
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    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
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        /* operands of same sign, result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    RETURN();
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}
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void op_dsub (void)
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{
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    T0 -= T1;
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    RETURN();
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}
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void op_dsubo (void)
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{
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    target_long tmp;
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    tmp = T0;
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    T0 = (int64_t)T0 - (int64_t)T1;
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    if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
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        /* operands of different sign, first operand and result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    RETURN();
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}
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void op_dmul (void)
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{
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    T0 = (int64_t)T0 * (int64_t)T1;
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    RETURN();
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}
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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/* Those might call libgcc functions.  */
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void op_ddiv (void)
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{
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    do_ddiv();
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    RETURN();
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}
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void op_ddivu (void)
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{
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    do_ddivu();
446 c570fd16 ths
    RETURN();
447 c570fd16 ths
}
448 c570fd16 ths
#else
449 c570fd16 ths
void op_ddiv (void)
450 c570fd16 ths
{
451 c570fd16 ths
    if (T1 != 0) {
452 c570fd16 ths
        env->LO = (int64_t)T0 / (int64_t)T1;
453 c570fd16 ths
        env->HI = (int64_t)T0 % (int64_t)T1;
454 c570fd16 ths
    }
455 c570fd16 ths
    RETURN();
456 c570fd16 ths
}
457 c570fd16 ths
458 c570fd16 ths
void op_ddivu (void)
459 c570fd16 ths
{
460 c570fd16 ths
    if (T1 != 0) {
461 6af0bf9c bellard
        env->LO = T0 / T1;
462 6af0bf9c bellard
        env->HI = T0 % T1;
463 6af0bf9c bellard
    }
464 6af0bf9c bellard
    RETURN();
465 6af0bf9c bellard
}
466 c570fd16 ths
#endif
467 60aa19ab ths
#endif /* TARGET_MIPS64 */
468 6af0bf9c bellard
469 6af0bf9c bellard
/* Logical */
470 6af0bf9c bellard
void op_and (void)
471 6af0bf9c bellard
{
472 6af0bf9c bellard
    T0 &= T1;
473 6af0bf9c bellard
    RETURN();
474 6af0bf9c bellard
}
475 6af0bf9c bellard
476 6af0bf9c bellard
void op_nor (void)
477 6af0bf9c bellard
{
478 6af0bf9c bellard
    T0 = ~(T0 | T1);
479 6af0bf9c bellard
    RETURN();
480 6af0bf9c bellard
}
481 6af0bf9c bellard
482 6af0bf9c bellard
void op_or (void)
483 6af0bf9c bellard
{
484 6af0bf9c bellard
    T0 |= T1;
485 6af0bf9c bellard
    RETURN();
486 6af0bf9c bellard
}
487 6af0bf9c bellard
488 6af0bf9c bellard
void op_xor (void)
489 6af0bf9c bellard
{
490 6af0bf9c bellard
    T0 ^= T1;
491 6af0bf9c bellard
    RETURN();
492 6af0bf9c bellard
}
493 6af0bf9c bellard
494 6af0bf9c bellard
void op_sll (void)
495 6af0bf9c bellard
{
496 5a63bcb2 ths
    T0 = (int32_t)((uint32_t)T0 << T1);
497 6af0bf9c bellard
    RETURN();
498 6af0bf9c bellard
}
499 6af0bf9c bellard
500 6af0bf9c bellard
void op_sra (void)
501 6af0bf9c bellard
{
502 5a63bcb2 ths
    T0 = (int32_t)((int32_t)T0 >> T1);
503 6af0bf9c bellard
    RETURN();
504 6af0bf9c bellard
}
505 6af0bf9c bellard
506 6af0bf9c bellard
void op_srl (void)
507 6af0bf9c bellard
{
508 5a63bcb2 ths
    T0 = (int32_t)((uint32_t)T0 >> T1);
509 6af0bf9c bellard
    RETURN();
510 6af0bf9c bellard
}
511 6af0bf9c bellard
512 7a387fff ths
void op_rotr (void)
513 7a387fff ths
{
514 7a387fff ths
    target_ulong tmp;
515 7a387fff ths
516 7a387fff ths
    if (T1) {
517 5a63bcb2 ths
       tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
518 5a63bcb2 ths
       T0 = (int32_t)((uint32_t)T0 >> T1) | tmp;
519 5a63bcb2 ths
    }
520 7a387fff ths
    RETURN();
521 7a387fff ths
}
522 7a387fff ths
523 6af0bf9c bellard
void op_sllv (void)
524 6af0bf9c bellard
{
525 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
526 6af0bf9c bellard
    RETURN();
527 6af0bf9c bellard
}
528 6af0bf9c bellard
529 6af0bf9c bellard
void op_srav (void)
530 6af0bf9c bellard
{
531 5dc4b744 ths
    T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
532 6af0bf9c bellard
    RETURN();
533 6af0bf9c bellard
}
534 6af0bf9c bellard
535 6af0bf9c bellard
void op_srlv (void)
536 6af0bf9c bellard
{
537 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
538 6af0bf9c bellard
    RETURN();
539 6af0bf9c bellard
}
540 6af0bf9c bellard
541 7a387fff ths
void op_rotrv (void)
542 7a387fff ths
{
543 7a387fff ths
    target_ulong tmp;
544 7a387fff ths
545 7a387fff ths
    T0 &= 0x1F;
546 7a387fff ths
    if (T0) {
547 5dc4b744 ths
       tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
548 5dc4b744 ths
       T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
549 7a387fff ths
    } else
550 7a387fff ths
       T0 = T1;
551 7a387fff ths
    RETURN();
552 7a387fff ths
}
553 7a387fff ths
554 6af0bf9c bellard
void op_clo (void)
555 6af0bf9c bellard
{
556 6af0bf9c bellard
    int n;
557 6af0bf9c bellard
558 c570fd16 ths
    if (T0 == ~((target_ulong)0)) {
559 6af0bf9c bellard
        T0 = 32;
560 6af0bf9c bellard
    } else {
561 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
562 6af0bf9c bellard
            if (!(T0 & (1 << 31)))
563 6af0bf9c bellard
                break;
564 6af0bf9c bellard
            T0 = T0 << 1;
565 6af0bf9c bellard
        }
566 6af0bf9c bellard
        T0 = n;
567 6af0bf9c bellard
    }
568 6af0bf9c bellard
    RETURN();
569 6af0bf9c bellard
}
570 6af0bf9c bellard
571 6af0bf9c bellard
void op_clz (void)
572 6af0bf9c bellard
{
573 6af0bf9c bellard
    int n;
574 6af0bf9c bellard
575 6af0bf9c bellard
    if (T0 == 0) {
576 6af0bf9c bellard
        T0 = 32;
577 6af0bf9c bellard
    } else {
578 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
579 6af0bf9c bellard
            if (T0 & (1 << 31))
580 6af0bf9c bellard
                break;
581 6af0bf9c bellard
            T0 = T0 << 1;
582 6af0bf9c bellard
        }
583 6af0bf9c bellard
        T0 = n;
584 6af0bf9c bellard
    }
585 6af0bf9c bellard
    RETURN();
586 6af0bf9c bellard
}
587 6af0bf9c bellard
588 60aa19ab ths
#ifdef TARGET_MIPS64
589 c570fd16 ths
590 c570fd16 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
591 c570fd16 ths
/* Those might call libgcc functions.  */
592 c570fd16 ths
void op_dsll (void)
593 6af0bf9c bellard
{
594 c570fd16 ths
    CALL_FROM_TB0(do_dsll);
595 c570fd16 ths
    RETURN();
596 6af0bf9c bellard
}
597 6af0bf9c bellard
598 c570fd16 ths
void op_dsll32 (void)
599 6af0bf9c bellard
{
600 c570fd16 ths
    CALL_FROM_TB0(do_dsll32);
601 c570fd16 ths
    RETURN();
602 6af0bf9c bellard
}
603 6af0bf9c bellard
604 c570fd16 ths
void op_dsra (void)
605 6af0bf9c bellard
{
606 c570fd16 ths
    CALL_FROM_TB0(do_dsra);
607 6af0bf9c bellard
    RETURN();
608 6af0bf9c bellard
}
609 6af0bf9c bellard
610 c570fd16 ths
void op_dsra32 (void)
611 6af0bf9c bellard
{
612 c570fd16 ths
    CALL_FROM_TB0(do_dsra32);
613 6af0bf9c bellard
    RETURN();
614 6af0bf9c bellard
}
615 6af0bf9c bellard
616 c570fd16 ths
void op_dsrl (void)
617 6af0bf9c bellard
{
618 c570fd16 ths
    CALL_FROM_TB0(do_dsrl);
619 c570fd16 ths
    RETURN();
620 c570fd16 ths
}
621 6af0bf9c bellard
622 c570fd16 ths
void op_dsrl32 (void)
623 c570fd16 ths
{
624 c570fd16 ths
    CALL_FROM_TB0(do_dsrl32);
625 6af0bf9c bellard
    RETURN();
626 6af0bf9c bellard
}
627 6af0bf9c bellard
628 c570fd16 ths
void op_drotr (void)
629 6af0bf9c bellard
{
630 c570fd16 ths
    CALL_FROM_TB0(do_drotr);
631 c570fd16 ths
    RETURN();
632 c570fd16 ths
}
633 6af0bf9c bellard
634 c570fd16 ths
void op_drotr32 (void)
635 c570fd16 ths
{
636 c570fd16 ths
    CALL_FROM_TB0(do_drotr32);
637 6af0bf9c bellard
    RETURN();
638 6af0bf9c bellard
}
639 6af0bf9c bellard
640 c570fd16 ths
void op_dsllv (void)
641 6af0bf9c bellard
{
642 c570fd16 ths
    CALL_FROM_TB0(do_dsllv);
643 c570fd16 ths
    RETURN();
644 c570fd16 ths
}
645 6af0bf9c bellard
646 c570fd16 ths
void op_dsrav (void)
647 c570fd16 ths
{
648 c570fd16 ths
    CALL_FROM_TB0(do_dsrav);
649 6af0bf9c bellard
    RETURN();
650 6af0bf9c bellard
}
651 6af0bf9c bellard
652 c570fd16 ths
void op_dsrlv (void)
653 6af0bf9c bellard
{
654 c570fd16 ths
    CALL_FROM_TB0(do_dsrlv);
655 c570fd16 ths
    RETURN();
656 c570fd16 ths
}
657 6af0bf9c bellard
658 c570fd16 ths
void op_drotrv (void)
659 c570fd16 ths
{
660 c570fd16 ths
    CALL_FROM_TB0(do_drotrv);
661 6af0bf9c bellard
    RETURN();
662 6af0bf9c bellard
}
663 c570fd16 ths
664 c570fd16 ths
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
665 c570fd16 ths
666 c570fd16 ths
void op_dsll (void)
667 c570fd16 ths
{
668 c570fd16 ths
    T0 = T0 << T1;
669 c570fd16 ths
    RETURN();
670 c570fd16 ths
}
671 c570fd16 ths
672 c570fd16 ths
void op_dsll32 (void)
673 c570fd16 ths
{
674 c570fd16 ths
    T0 = T0 << (T1 + 32);
675 c570fd16 ths
    RETURN();
676 c570fd16 ths
}
677 c570fd16 ths
678 c570fd16 ths
void op_dsra (void)
679 c570fd16 ths
{
680 c570fd16 ths
    T0 = (int64_t)T0 >> T1;
681 c570fd16 ths
    RETURN();
682 c570fd16 ths
}
683 c570fd16 ths
684 c570fd16 ths
void op_dsra32 (void)
685 c570fd16 ths
{
686 c570fd16 ths
    T0 = (int64_t)T0 >> (T1 + 32);
687 c570fd16 ths
    RETURN();
688 c570fd16 ths
}
689 c570fd16 ths
690 c570fd16 ths
void op_dsrl (void)
691 c570fd16 ths
{
692 c570fd16 ths
    T0 = T0 >> T1;
693 c570fd16 ths
    RETURN();
694 c570fd16 ths
}
695 c570fd16 ths
696 c570fd16 ths
void op_dsrl32 (void)
697 c570fd16 ths
{
698 c570fd16 ths
    T0 = T0 >> (T1 + 32);
699 c570fd16 ths
    RETURN();
700 c570fd16 ths
}
701 c570fd16 ths
702 c570fd16 ths
void op_drotr (void)
703 c570fd16 ths
{
704 c570fd16 ths
    target_ulong tmp;
705 c570fd16 ths
706 c570fd16 ths
    if (T1) {
707 c570fd16 ths
       tmp = T0 << (0x40 - T1);
708 c570fd16 ths
       T0 = (T0 >> T1) | tmp;
709 5a63bcb2 ths
    }
710 c570fd16 ths
    RETURN();
711 c570fd16 ths
}
712 c570fd16 ths
713 c570fd16 ths
void op_drotr32 (void)
714 c570fd16 ths
{
715 c570fd16 ths
    target_ulong tmp;
716 c570fd16 ths
717 c570fd16 ths
    if (T1) {
718 c570fd16 ths
       tmp = T0 << (0x40 - (32 + T1));
719 c570fd16 ths
       T0 = (T0 >> (32 + T1)) | tmp;
720 5a63bcb2 ths
    }
721 c570fd16 ths
    RETURN();
722 c570fd16 ths
}
723 c570fd16 ths
724 c570fd16 ths
void op_dsllv (void)
725 c570fd16 ths
{
726 c570fd16 ths
    T0 = T1 << (T0 & 0x3F);
727 c570fd16 ths
    RETURN();
728 c570fd16 ths
}
729 c570fd16 ths
730 c570fd16 ths
void op_dsrav (void)
731 c570fd16 ths
{
732 c570fd16 ths
    T0 = (int64_t)T1 >> (T0 & 0x3F);
733 c570fd16 ths
    RETURN();
734 c570fd16 ths
}
735 c570fd16 ths
736 c570fd16 ths
void op_dsrlv (void)
737 c570fd16 ths
{
738 c570fd16 ths
    T0 = T1 >> (T0 & 0x3F);
739 c570fd16 ths
    RETURN();
740 c570fd16 ths
}
741 c570fd16 ths
742 c570fd16 ths
void op_drotrv (void)
743 c570fd16 ths
{
744 c570fd16 ths
    target_ulong tmp;
745 c570fd16 ths
746 c570fd16 ths
    T0 &= 0x3F;
747 c570fd16 ths
    if (T0) {
748 c570fd16 ths
       tmp = T1 << (0x40 - T0);
749 c570fd16 ths
       T0 = (T1 >> T0) | tmp;
750 c570fd16 ths
    } else
751 c570fd16 ths
       T0 = T1;
752 c570fd16 ths
    RETURN();
753 c570fd16 ths
}
754 c570fd16 ths
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
755 c570fd16 ths
756 c570fd16 ths
void op_dclo (void)
757 c570fd16 ths
{
758 c570fd16 ths
    int n;
759 c570fd16 ths
760 c570fd16 ths
    if (T0 == ~((target_ulong)0)) {
761 c570fd16 ths
        T0 = 64;
762 c570fd16 ths
    } else {
763 c570fd16 ths
        for (n = 0; n < 64; n++) {
764 c570fd16 ths
            if (!(T0 & (1ULL << 63)))
765 c570fd16 ths
                break;
766 c570fd16 ths
            T0 = T0 << 1;
767 c570fd16 ths
        }
768 c570fd16 ths
        T0 = n;
769 c570fd16 ths
    }
770 c570fd16 ths
    RETURN();
771 c570fd16 ths
}
772 c570fd16 ths
773 c570fd16 ths
void op_dclz (void)
774 c570fd16 ths
{
775 c570fd16 ths
    int n;
776 c570fd16 ths
777 c570fd16 ths
    if (T0 == 0) {
778 c570fd16 ths
        T0 = 64;
779 c570fd16 ths
    } else {
780 c570fd16 ths
        for (n = 0; n < 64; n++) {
781 c570fd16 ths
            if (T0 & (1ULL << 63))
782 c570fd16 ths
                break;
783 c570fd16 ths
            T0 = T0 << 1;
784 c570fd16 ths
        }
785 c570fd16 ths
        T0 = n;
786 c570fd16 ths
    }
787 c570fd16 ths
    RETURN();
788 c570fd16 ths
}
789 c570fd16 ths
#endif
790 c570fd16 ths
791 c570fd16 ths
/* 64 bits arithmetic */
792 c570fd16 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
793 6af0bf9c bellard
void op_mult (void)
794 6af0bf9c bellard
{
795 6af0bf9c bellard
    CALL_FROM_TB0(do_mult);
796 6af0bf9c bellard
    RETURN();
797 6af0bf9c bellard
}
798 6af0bf9c bellard
799 6af0bf9c bellard
void op_multu (void)
800 6af0bf9c bellard
{
801 6af0bf9c bellard
    CALL_FROM_TB0(do_multu);
802 6af0bf9c bellard
    RETURN();
803 6af0bf9c bellard
}
804 6af0bf9c bellard
805 6af0bf9c bellard
void op_madd (void)
806 6af0bf9c bellard
{
807 6af0bf9c bellard
    CALL_FROM_TB0(do_madd);
808 6af0bf9c bellard
    RETURN();
809 6af0bf9c bellard
}
810 6af0bf9c bellard
811 6af0bf9c bellard
void op_maddu (void)
812 6af0bf9c bellard
{
813 6af0bf9c bellard
    CALL_FROM_TB0(do_maddu);
814 6af0bf9c bellard
    RETURN();
815 6af0bf9c bellard
}
816 6af0bf9c bellard
817 6af0bf9c bellard
void op_msub (void)
818 6af0bf9c bellard
{
819 6af0bf9c bellard
    CALL_FROM_TB0(do_msub);
820 6af0bf9c bellard
    RETURN();
821 6af0bf9c bellard
}
822 6af0bf9c bellard
823 6af0bf9c bellard
void op_msubu (void)
824 6af0bf9c bellard
{
825 6af0bf9c bellard
    CALL_FROM_TB0(do_msubu);
826 6af0bf9c bellard
    RETURN();
827 6af0bf9c bellard
}
828 c570fd16 ths
829 c570fd16 ths
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
830 c570fd16 ths
831 c570fd16 ths
static inline uint64_t get_HILO (void)
832 c570fd16 ths
{
833 c570fd16 ths
    return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO);
834 c570fd16 ths
}
835 c570fd16 ths
836 c570fd16 ths
static inline void set_HILO (uint64_t HILO)
837 c570fd16 ths
{
838 5dc4b744 ths
    env->LO = (int32_t)(HILO & 0xFFFFFFFF);
839 5dc4b744 ths
    env->HI = (int32_t)(HILO >> 32);
840 c570fd16 ths
}
841 c570fd16 ths
842 c570fd16 ths
void op_mult (void)
843 c570fd16 ths
{
844 c570fd16 ths
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
845 c570fd16 ths
    RETURN();
846 c570fd16 ths
}
847 c570fd16 ths
848 c570fd16 ths
void op_multu (void)
849 c570fd16 ths
{
850 c570fd16 ths
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
851 c570fd16 ths
    RETURN();
852 c570fd16 ths
}
853 c570fd16 ths
854 c570fd16 ths
void op_madd (void)
855 c570fd16 ths
{
856 c570fd16 ths
    int64_t tmp;
857 c570fd16 ths
858 c570fd16 ths
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
859 c570fd16 ths
    set_HILO((int64_t)get_HILO() + tmp);
860 c570fd16 ths
    RETURN();
861 c570fd16 ths
}
862 c570fd16 ths
863 c570fd16 ths
void op_maddu (void)
864 c570fd16 ths
{
865 c570fd16 ths
    uint64_t tmp;
866 c570fd16 ths
867 c570fd16 ths
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
868 c570fd16 ths
    set_HILO(get_HILO() + tmp);
869 c570fd16 ths
    RETURN();
870 c570fd16 ths
}
871 c570fd16 ths
872 c570fd16 ths
void op_msub (void)
873 c570fd16 ths
{
874 c570fd16 ths
    int64_t tmp;
875 c570fd16 ths
876 c570fd16 ths
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
877 c570fd16 ths
    set_HILO((int64_t)get_HILO() - tmp);
878 c570fd16 ths
    RETURN();
879 c570fd16 ths
}
880 c570fd16 ths
881 c570fd16 ths
void op_msubu (void)
882 c570fd16 ths
{
883 c570fd16 ths
    uint64_t tmp;
884 c570fd16 ths
885 c570fd16 ths
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
886 c570fd16 ths
    set_HILO(get_HILO() - tmp);
887 c570fd16 ths
    RETURN();
888 c570fd16 ths
}
889 c570fd16 ths
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
890 c570fd16 ths
891 60aa19ab ths
#ifdef TARGET_MIPS64
892 c570fd16 ths
void op_dmult (void)
893 c570fd16 ths
{
894 c570fd16 ths
    CALL_FROM_TB0(do_dmult);
895 c570fd16 ths
    RETURN();
896 c570fd16 ths
}
897 c570fd16 ths
898 c570fd16 ths
void op_dmultu (void)
899 c570fd16 ths
{
900 c570fd16 ths
    CALL_FROM_TB0(do_dmultu);
901 c570fd16 ths
    RETURN();
902 c570fd16 ths
}
903 6af0bf9c bellard
#endif
904 6af0bf9c bellard
905 6af0bf9c bellard
/* Conditional moves */
906 6af0bf9c bellard
void op_movn (void)
907 6af0bf9c bellard
{
908 6af0bf9c bellard
    if (T1 != 0)
909 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
910 6af0bf9c bellard
    RETURN();
911 6af0bf9c bellard
}
912 6af0bf9c bellard
913 6af0bf9c bellard
void op_movz (void)
914 6af0bf9c bellard
{
915 6af0bf9c bellard
    if (T1 == 0)
916 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
917 6af0bf9c bellard
    RETURN();
918 6af0bf9c bellard
}
919 6af0bf9c bellard
920 7a387fff ths
void op_movf (void)
921 7a387fff ths
{
922 7a387fff ths
    if (!(env->fcr31 & PARAM1))
923 7a387fff ths
        env->gpr[PARAM2] = env->gpr[PARAM3];
924 7a387fff ths
    RETURN();
925 7a387fff ths
}
926 7a387fff ths
927 7a387fff ths
void op_movt (void)
928 7a387fff ths
{
929 7a387fff ths
    if (env->fcr31 & PARAM1)
930 7a387fff ths
        env->gpr[PARAM2] = env->gpr[PARAM3];
931 7a387fff ths
    RETURN();
932 7a387fff ths
}
933 7a387fff ths
934 6af0bf9c bellard
/* Tests */
935 6af0bf9c bellard
#define OP_COND(name, cond) \
936 6af0bf9c bellard
void glue(op_, name) (void) \
937 6af0bf9c bellard
{                           \
938 6af0bf9c bellard
    if (cond) {             \
939 6af0bf9c bellard
        T0 = 1;             \
940 6af0bf9c bellard
    } else {                \
941 6af0bf9c bellard
        T0 = 0;             \
942 6af0bf9c bellard
    }                       \
943 6af0bf9c bellard
    RETURN();               \
944 6af0bf9c bellard
}
945 6af0bf9c bellard
946 6af0bf9c bellard
OP_COND(eq, T0 == T1);
947 6af0bf9c bellard
OP_COND(ne, T0 != T1);
948 6af0bf9c bellard
OP_COND(ge, (int32_t)T0 >= (int32_t)T1);
949 6af0bf9c bellard
OP_COND(geu, T0 >= T1);
950 6af0bf9c bellard
OP_COND(lt, (int32_t)T0 < (int32_t)T1);
951 6af0bf9c bellard
OP_COND(ltu, T0 < T1);
952 6af0bf9c bellard
OP_COND(gez, (int32_t)T0 >= 0);
953 6af0bf9c bellard
OP_COND(gtz, (int32_t)T0 > 0);
954 6af0bf9c bellard
OP_COND(lez, (int32_t)T0 <= 0);
955 6af0bf9c bellard
OP_COND(ltz, (int32_t)T0 < 0);
956 6af0bf9c bellard
957 7a387fff ths
/* Branches */
958 6af0bf9c bellard
//#undef USE_DIRECT_JUMP
959 c53be334 bellard
960 c53be334 bellard
void OPPROTO op_goto_tb0(void)
961 c53be334 bellard
{
962 c53be334 bellard
    GOTO_TB(op_goto_tb0, PARAM1, 0);
963 7a387fff ths
    RETURN();
964 c53be334 bellard
}
965 c53be334 bellard
966 c53be334 bellard
void OPPROTO op_goto_tb1(void)
967 c53be334 bellard
{
968 c53be334 bellard
    GOTO_TB(op_goto_tb1, PARAM1, 1);
969 7a387fff ths
    RETURN();
970 c53be334 bellard
}
971 6af0bf9c bellard
972 6af0bf9c bellard
/* Branch to register */
973 6af0bf9c bellard
void op_save_breg_target (void)
974 6af0bf9c bellard
{
975 6af0bf9c bellard
    env->btarget = T2;
976 7a387fff ths
    RETURN();
977 6af0bf9c bellard
}
978 6af0bf9c bellard
979 6af0bf9c bellard
void op_restore_breg_target (void)
980 6af0bf9c bellard
{
981 6af0bf9c bellard
    T2 = env->btarget;
982 7a387fff ths
    RETURN();
983 6af0bf9c bellard
}
984 6af0bf9c bellard
985 6af0bf9c bellard
void op_breg (void)
986 6af0bf9c bellard
{
987 6af0bf9c bellard
    env->PC = T2;
988 6af0bf9c bellard
    RETURN();
989 6af0bf9c bellard
}
990 6af0bf9c bellard
991 6af0bf9c bellard
void op_save_btarget (void)
992 6af0bf9c bellard
{
993 6af0bf9c bellard
    env->btarget = PARAM1;
994 6af0bf9c bellard
    RETURN();
995 6af0bf9c bellard
}
996 6af0bf9c bellard
997 6af0bf9c bellard
/* Conditional branch */
998 6af0bf9c bellard
void op_set_bcond (void)
999 6af0bf9c bellard
{
1000 6af0bf9c bellard
    T2 = T0;
1001 6af0bf9c bellard
    RETURN();
1002 6af0bf9c bellard
}
1003 6af0bf9c bellard
1004 6af0bf9c bellard
void op_save_bcond (void)
1005 6af0bf9c bellard
{
1006 6af0bf9c bellard
    env->bcond = T2;
1007 6af0bf9c bellard
    RETURN();
1008 6af0bf9c bellard
}
1009 6af0bf9c bellard
1010 6af0bf9c bellard
void op_restore_bcond (void)
1011 6af0bf9c bellard
{
1012 6af0bf9c bellard
    T2 = env->bcond;
1013 6af0bf9c bellard
    RETURN();
1014 6af0bf9c bellard
}
1015 6af0bf9c bellard
1016 c53be334 bellard
void op_jnz_T2 (void)
1017 6af0bf9c bellard
{
1018 c53be334 bellard
    if (T2)
1019 c53be334 bellard
        GOTO_LABEL_PARAM(1);
1020 6af0bf9c bellard
    RETURN();
1021 6af0bf9c bellard
}
1022 6af0bf9c bellard
1023 6af0bf9c bellard
/* CP0 functions */
1024 873eb012 ths
void op_mfc0_index (void)
1025 6af0bf9c bellard
{
1026 9c2149c8 ths
    T0 = env->CP0_Index;
1027 873eb012 ths
    RETURN();
1028 873eb012 ths
}
1029 873eb012 ths
1030 873eb012 ths
void op_mfc0_random (void)
1031 873eb012 ths
{
1032 873eb012 ths
    CALL_FROM_TB0(do_mfc0_random);
1033 873eb012 ths
    RETURN();
1034 873eb012 ths
}
1035 873eb012 ths
1036 873eb012 ths
void op_mfc0_entrylo0 (void)
1037 873eb012 ths
{
1038 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryLo0;
1039 873eb012 ths
    RETURN();
1040 873eb012 ths
}
1041 873eb012 ths
1042 873eb012 ths
void op_mfc0_entrylo1 (void)
1043 873eb012 ths
{
1044 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryLo1;
1045 873eb012 ths
    RETURN();
1046 873eb012 ths
}
1047 873eb012 ths
1048 873eb012 ths
void op_mfc0_context (void)
1049 873eb012 ths
{
1050 9c2149c8 ths
    T0 = (int32_t)env->CP0_Context;
1051 873eb012 ths
    RETURN();
1052 873eb012 ths
}
1053 873eb012 ths
1054 873eb012 ths
void op_mfc0_pagemask (void)
1055 873eb012 ths
{
1056 9c2149c8 ths
    T0 = env->CP0_PageMask;
1057 873eb012 ths
    RETURN();
1058 873eb012 ths
}
1059 873eb012 ths
1060 7a387fff ths
void op_mfc0_pagegrain (void)
1061 7a387fff ths
{
1062 9c2149c8 ths
    T0 = env->CP0_PageGrain;
1063 7a387fff ths
    RETURN();
1064 7a387fff ths
}
1065 7a387fff ths
1066 873eb012 ths
void op_mfc0_wired (void)
1067 873eb012 ths
{
1068 9c2149c8 ths
    T0 = env->CP0_Wired;
1069 873eb012 ths
    RETURN();
1070 873eb012 ths
}
1071 873eb012 ths
1072 7a387fff ths
void op_mfc0_hwrena (void)
1073 7a387fff ths
{
1074 9c2149c8 ths
    T0 = env->CP0_HWREna;
1075 7a387fff ths
    RETURN();
1076 7a387fff ths
}
1077 7a387fff ths
1078 873eb012 ths
void op_mfc0_badvaddr (void)
1079 873eb012 ths
{
1080 9c2149c8 ths
    T0 = (int32_t)env->CP0_BadVAddr;
1081 873eb012 ths
    RETURN();
1082 873eb012 ths
}
1083 873eb012 ths
1084 873eb012 ths
void op_mfc0_count (void)
1085 873eb012 ths
{
1086 873eb012 ths
    CALL_FROM_TB0(do_mfc0_count);
1087 873eb012 ths
    RETURN();
1088 873eb012 ths
}
1089 873eb012 ths
1090 873eb012 ths
void op_mfc0_entryhi (void)
1091 873eb012 ths
{
1092 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryHi;
1093 873eb012 ths
    RETURN();
1094 873eb012 ths
}
1095 873eb012 ths
1096 873eb012 ths
void op_mfc0_compare (void)
1097 873eb012 ths
{
1098 9c2149c8 ths
    T0 = env->CP0_Compare;
1099 873eb012 ths
    RETURN();
1100 873eb012 ths
}
1101 873eb012 ths
1102 873eb012 ths
void op_mfc0_status (void)
1103 873eb012 ths
{
1104 9c2149c8 ths
    T0 = env->CP0_Status;
1105 873eb012 ths
    RETURN();
1106 873eb012 ths
}
1107 873eb012 ths
1108 7a387fff ths
void op_mfc0_intctl (void)
1109 7a387fff ths
{
1110 9c2149c8 ths
    T0 = env->CP0_IntCtl;
1111 7a387fff ths
    RETURN();
1112 7a387fff ths
}
1113 7a387fff ths
1114 7a387fff ths
void op_mfc0_srsctl (void)
1115 7a387fff ths
{
1116 9c2149c8 ths
    T0 = env->CP0_SRSCtl;
1117 9c2149c8 ths
    RETURN();
1118 9c2149c8 ths
}
1119 9c2149c8 ths
1120 9c2149c8 ths
void op_mfc0_srsmap (void)
1121 9c2149c8 ths
{
1122 9c2149c8 ths
    T0 = env->CP0_SRSMap;
1123 7a387fff ths
    RETURN();
1124 7a387fff ths
}
1125 7a387fff ths
1126 873eb012 ths
void op_mfc0_cause (void)
1127 873eb012 ths
{
1128 9c2149c8 ths
    T0 = env->CP0_Cause;
1129 873eb012 ths
    RETURN();
1130 873eb012 ths
}
1131 873eb012 ths
1132 873eb012 ths
void op_mfc0_epc (void)
1133 873eb012 ths
{
1134 9c2149c8 ths
    T0 = (int32_t)env->CP0_EPC;
1135 873eb012 ths
    RETURN();
1136 873eb012 ths
}
1137 873eb012 ths
1138 873eb012 ths
void op_mfc0_prid (void)
1139 873eb012 ths
{
1140 9c2149c8 ths
    T0 = env->CP0_PRid;
1141 873eb012 ths
    RETURN();
1142 873eb012 ths
}
1143 873eb012 ths
1144 7a387fff ths
void op_mfc0_ebase (void)
1145 7a387fff ths
{
1146 b29a0341 ths
    T0 = env->CP0_EBase;
1147 7a387fff ths
    RETURN();
1148 7a387fff ths
}
1149 7a387fff ths
1150 873eb012 ths
void op_mfc0_config0 (void)
1151 873eb012 ths
{
1152 9c2149c8 ths
    T0 = env->CP0_Config0;
1153 873eb012 ths
    RETURN();
1154 873eb012 ths
}
1155 873eb012 ths
1156 873eb012 ths
void op_mfc0_config1 (void)
1157 873eb012 ths
{
1158 9c2149c8 ths
    T0 = env->CP0_Config1;
1159 873eb012 ths
    RETURN();
1160 873eb012 ths
}
1161 873eb012 ths
1162 7a387fff ths
void op_mfc0_config2 (void)
1163 7a387fff ths
{
1164 9c2149c8 ths
    T0 = env->CP0_Config2;
1165 7a387fff ths
    RETURN();
1166 7a387fff ths
}
1167 7a387fff ths
1168 7a387fff ths
void op_mfc0_config3 (void)
1169 7a387fff ths
{
1170 9c2149c8 ths
    T0 = env->CP0_Config3;
1171 7a387fff ths
    RETURN();
1172 7a387fff ths
}
1173 7a387fff ths
1174 e397ee33 ths
void op_mfc0_config6 (void)
1175 e397ee33 ths
{
1176 e397ee33 ths
    T0 = env->CP0_Config6;
1177 e397ee33 ths
    RETURN();
1178 e397ee33 ths
}
1179 e397ee33 ths
1180 e397ee33 ths
void op_mfc0_config7 (void)
1181 e397ee33 ths
{
1182 e397ee33 ths
    T0 = env->CP0_Config7;
1183 e397ee33 ths
    RETURN();
1184 e397ee33 ths
}
1185 e397ee33 ths
1186 873eb012 ths
void op_mfc0_lladdr (void)
1187 873eb012 ths
{
1188 9c2149c8 ths
    T0 = (int32_t)env->CP0_LLAddr >> 4;
1189 873eb012 ths
    RETURN();
1190 873eb012 ths
}
1191 873eb012 ths
1192 7a387fff ths
void op_mfc0_watchlo0 (void)
1193 873eb012 ths
{
1194 5dc4b744 ths
    T0 = (int32_t)env->CP0_WatchLo;
1195 873eb012 ths
    RETURN();
1196 873eb012 ths
}
1197 873eb012 ths
1198 7a387fff ths
void op_mfc0_watchhi0 (void)
1199 873eb012 ths
{
1200 9c2149c8 ths
    T0 = env->CP0_WatchHi;
1201 873eb012 ths
    RETURN();
1202 873eb012 ths
}
1203 873eb012 ths
1204 7a387fff ths
void op_mfc0_xcontext (void)
1205 7a387fff ths
{
1206 9c2149c8 ths
    T0 = (int32_t)env->CP0_XContext;
1207 7a387fff ths
    RETURN();
1208 7a387fff ths
}
1209 7a387fff ths
1210 7a387fff ths
void op_mfc0_framemask (void)
1211 7a387fff ths
{
1212 7a387fff ths
    T0 = env->CP0_Framemask;
1213 7a387fff ths
    RETURN();
1214 7a387fff ths
}
1215 7a387fff ths
1216 873eb012 ths
void op_mfc0_debug (void)
1217 873eb012 ths
{
1218 9c2149c8 ths
    T0 = env->CP0_Debug;
1219 873eb012 ths
    if (env->hflags & MIPS_HFLAG_DM)
1220 873eb012 ths
        T0 |= 1 << CP0DB_DM;
1221 873eb012 ths
    RETURN();
1222 873eb012 ths
}
1223 873eb012 ths
1224 873eb012 ths
void op_mfc0_depc (void)
1225 873eb012 ths
{
1226 9c2149c8 ths
    T0 = (int32_t)env->CP0_DEPC;
1227 873eb012 ths
    RETURN();
1228 873eb012 ths
}
1229 873eb012 ths
1230 7a387fff ths
void op_mfc0_performance0 (void)
1231 7a387fff ths
{
1232 9c2149c8 ths
    T0 = env->CP0_Performance0;
1233 7a387fff ths
    RETURN();
1234 7a387fff ths
}
1235 7a387fff ths
1236 873eb012 ths
void op_mfc0_taglo (void)
1237 873eb012 ths
{
1238 9c2149c8 ths
    T0 = env->CP0_TagLo;
1239 873eb012 ths
    RETURN();
1240 873eb012 ths
}
1241 873eb012 ths
1242 873eb012 ths
void op_mfc0_datalo (void)
1243 873eb012 ths
{
1244 9c2149c8 ths
    T0 = env->CP0_DataLo;
1245 873eb012 ths
    RETURN();
1246 873eb012 ths
}
1247 873eb012 ths
1248 7a387fff ths
void op_mfc0_taghi (void)
1249 7a387fff ths
{
1250 9c2149c8 ths
    T0 = env->CP0_TagHi;
1251 7a387fff ths
    RETURN();
1252 7a387fff ths
}
1253 7a387fff ths
1254 7a387fff ths
void op_mfc0_datahi (void)
1255 7a387fff ths
{
1256 9c2149c8 ths
    T0 = env->CP0_DataHi;
1257 7a387fff ths
    RETURN();
1258 7a387fff ths
}
1259 7a387fff ths
1260 873eb012 ths
void op_mfc0_errorepc (void)
1261 873eb012 ths
{
1262 9c2149c8 ths
    T0 = (int32_t)env->CP0_ErrorEPC;
1263 873eb012 ths
    RETURN();
1264 873eb012 ths
}
1265 873eb012 ths
1266 873eb012 ths
void op_mfc0_desave (void)
1267 873eb012 ths
{
1268 9c2149c8 ths
    T0 = env->CP0_DESAVE;
1269 6af0bf9c bellard
    RETURN();
1270 6af0bf9c bellard
}
1271 6af0bf9c bellard
1272 8c0fdd85 ths
void op_mtc0_index (void)
1273 6af0bf9c bellard
{
1274 9c2149c8 ths
    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
1275 8c0fdd85 ths
    RETURN();
1276 8c0fdd85 ths
}
1277 8c0fdd85 ths
1278 8c0fdd85 ths
void op_mtc0_entrylo0 (void)
1279 8c0fdd85 ths
{
1280 7a387fff ths
    /* Large physaddr not implemented */
1281 7a387fff ths
    /* 1k pages not implemented */
1282 9c2149c8 ths
    env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
1283 8c0fdd85 ths
    RETURN();
1284 8c0fdd85 ths
}
1285 8c0fdd85 ths
1286 8c0fdd85 ths
void op_mtc0_entrylo1 (void)
1287 8c0fdd85 ths
{
1288 7a387fff ths
    /* Large physaddr not implemented */
1289 7a387fff ths
    /* 1k pages not implemented */
1290 9c2149c8 ths
    env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
1291 8c0fdd85 ths
    RETURN();
1292 8c0fdd85 ths
}
1293 8c0fdd85 ths
1294 8c0fdd85 ths
void op_mtc0_context (void)
1295 8c0fdd85 ths
{
1296 c50da3df ths
    env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & ~0x007FFFFF);
1297 8c0fdd85 ths
    RETURN();
1298 8c0fdd85 ths
}
1299 8c0fdd85 ths
1300 8c0fdd85 ths
void op_mtc0_pagemask (void)
1301 8c0fdd85 ths
{
1302 7a387fff ths
    /* 1k pages not implemented */
1303 7a387fff ths
    env->CP0_PageMask = T0 & 0x1FFFE000;
1304 7a387fff ths
    RETURN();
1305 7a387fff ths
}
1306 7a387fff ths
1307 7a387fff ths
void op_mtc0_pagegrain (void)
1308 7a387fff ths
{
1309 7a387fff ths
    /* SmartMIPS not implemented */
1310 7a387fff ths
    /* Large physaddr not implemented */
1311 7a387fff ths
    /* 1k pages not implemented */
1312 7a387fff ths
    env->CP0_PageGrain = 0;
1313 8c0fdd85 ths
    RETURN();
1314 8c0fdd85 ths
}
1315 8c0fdd85 ths
1316 8c0fdd85 ths
void op_mtc0_wired (void)
1317 8c0fdd85 ths
{
1318 7a387fff ths
    env->CP0_Wired = T0 & (MIPS_TLB_NB - 1);
1319 7a387fff ths
    RETURN();
1320 7a387fff ths
}
1321 7a387fff ths
1322 7a387fff ths
void op_mtc0_hwrena (void)
1323 7a387fff ths
{
1324 7a387fff ths
    env->CP0_HWREna = T0 & 0x0000000F;
1325 8c0fdd85 ths
    RETURN();
1326 8c0fdd85 ths
}
1327 8c0fdd85 ths
1328 8c0fdd85 ths
void op_mtc0_count (void)
1329 8c0fdd85 ths
{
1330 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1331 8c0fdd85 ths
    RETURN();
1332 8c0fdd85 ths
}
1333 8c0fdd85 ths
1334 8c0fdd85 ths
void op_mtc0_entryhi (void)
1335 8c0fdd85 ths
{
1336 0feef828 ths
    target_ulong old, val;
1337 8c0fdd85 ths
1338 7a387fff ths
    /* 1k pages not implemented */
1339 7a387fff ths
    /* Ignore MIPS64 TLB for now */
1340 925fd0f2 ths
    val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00;
1341 8c0fdd85 ths
    old = env->CP0_EntryHi;
1342 8c0fdd85 ths
    env->CP0_EntryHi = val;
1343 8c0fdd85 ths
    /* If the ASID changes, flush qemu's TLB.  */
1344 8c0fdd85 ths
    if ((old & 0xFF) != (val & 0xFF))
1345 8c0fdd85 ths
        CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1346 8c0fdd85 ths
    RETURN();
1347 8c0fdd85 ths
}
1348 8c0fdd85 ths
1349 8c0fdd85 ths
void op_mtc0_compare (void)
1350 8c0fdd85 ths
{
1351 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1352 8c0fdd85 ths
    RETURN();
1353 8c0fdd85 ths
}
1354 8c0fdd85 ths
1355 8c0fdd85 ths
void op_mtc0_status (void)
1356 8c0fdd85 ths
{
1357 4de9b249 ths
    uint32_t val, old;
1358 8c0fdd85 ths
1359 24c7b0e3 ths
    /* No 64bit FPU, no reverse endianness, no MDMX/DSP, no 64bit ops,
1360 24c7b0e3 ths
       no 64bit addressing implemented. */
1361 24c7b0e3 ths
    val = (int32_t)T0 & 0xF878FF17;
1362 8c0fdd85 ths
    old = env->CP0_Status;
1363 f41c52f1 ths
    if (!(val & (1 << CP0St_EXL)) &&
1364 f41c52f1 ths
        !(val & (1 << CP0St_ERL)) &&
1365 f41c52f1 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
1366 f41c52f1 ths
        (val & (1 << CP0St_UM)))
1367 f41c52f1 ths
        env->hflags |= MIPS_HFLAG_UM;
1368 8c0fdd85 ths
    env->CP0_Status = val;
1369 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
1370 f41c52f1 ths
        CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1371 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
1372 8c0fdd85 ths
    RETURN();
1373 8c0fdd85 ths
}
1374 8c0fdd85 ths
1375 7a387fff ths
void op_mtc0_intctl (void)
1376 7a387fff ths
{
1377 c090a8f4 ths
    /* vectored interrupts not implemented, timer on int 7,
1378 c090a8f4 ths
       no performance counters. */
1379 c090a8f4 ths
    env->CP0_IntCtl |= T0 & 0x000002e0;
1380 7a387fff ths
    RETURN();
1381 7a387fff ths
}
1382 7a387fff ths
1383 7a387fff ths
void op_mtc0_srsctl (void)
1384 7a387fff ths
{
1385 7a387fff ths
    /* shadow registers not implemented */
1386 7a387fff ths
    env->CP0_SRSCtl = 0;
1387 7a387fff ths
    RETURN();
1388 7a387fff ths
}
1389 7a387fff ths
1390 9c2149c8 ths
void op_mtc0_srsmap (void)
1391 9c2149c8 ths
{
1392 9c2149c8 ths
    /* shadow registers not implemented */
1393 9c2149c8 ths
    env->CP0_SRSMap = 0;
1394 9c2149c8 ths
    RETURN();
1395 9c2149c8 ths
}
1396 9c2149c8 ths
1397 8c0fdd85 ths
void op_mtc0_cause (void)
1398 8c0fdd85 ths
{
1399 39d51eb8 ths
    uint32_t mask = 0x00C00300;
1400 39d51eb8 ths
1401 39d51eb8 ths
    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
1402 39d51eb8 ths
        mask |= 1 << CP0Ca_DC;
1403 39d51eb8 ths
1404 39d51eb8 ths
    env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask);
1405 8c0fdd85 ths
1406 4de9b249 ths
    /* Handle the software interrupt as an hardware one, as they
1407 4de9b249 ths
       are very similar */
1408 4de9b249 ths
    if (T0 & CP0Ca_IP_mask) {
1409 4de9b249 ths
        CALL_FROM_TB1(cpu_mips_update_irq, env);
1410 8c0fdd85 ths
    }
1411 8c0fdd85 ths
    RETURN();
1412 8c0fdd85 ths
}
1413 8c0fdd85 ths
1414 8c0fdd85 ths
void op_mtc0_epc (void)
1415 8c0fdd85 ths
{
1416 9c2149c8 ths
    env->CP0_EPC = (int32_t)T0;
1417 8c0fdd85 ths
    RETURN();
1418 8c0fdd85 ths
}
1419 8c0fdd85 ths
1420 7a387fff ths
void op_mtc0_ebase (void)
1421 7a387fff ths
{
1422 7a387fff ths
    /* vectored interrupts not implemented */
1423 7a387fff ths
    /* Multi-CPU not implemented */
1424 b29a0341 ths
    env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1425 7a387fff ths
    RETURN();
1426 7a387fff ths
}
1427 7a387fff ths
1428 8c0fdd85 ths
void op_mtc0_config0 (void)
1429 8c0fdd85 ths
{
1430 8c0fdd85 ths
#if defined(MIPS_USES_R4K_TLB)
1431 7a387fff ths
     /* Fixed mapping MMU not implemented */
1432 7a387fff ths
    env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001);
1433 8c0fdd85 ths
#else
1434 7a387fff ths
    env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001);
1435 8c0fdd85 ths
#endif
1436 8c0fdd85 ths
    RETURN();
1437 8c0fdd85 ths
}
1438 8c0fdd85 ths
1439 7a387fff ths
void op_mtc0_config2 (void)
1440 7a387fff ths
{
1441 7a387fff ths
    /* tertiary/secondary caches not implemented */
1442 7a387fff ths
    env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1443 7a387fff ths
    RETURN();
1444 7a387fff ths
}
1445 7a387fff ths
1446 7a387fff ths
void op_mtc0_watchlo0 (void)
1447 8c0fdd85 ths
{
1448 4e7a4a4e ths
    /* Watch exceptions for instructions, data loads, data stores
1449 4e7a4a4e ths
       not implemented. */
1450 4e7a4a4e ths
    env->CP0_WatchLo = (int32_t)(T0 & ~0x7);
1451 8c0fdd85 ths
    RETURN();
1452 8c0fdd85 ths
}
1453 8c0fdd85 ths
1454 7a387fff ths
void op_mtc0_watchhi0 (void)
1455 8c0fdd85 ths
{
1456 4e7a4a4e ths
    env->CP0_WatchHi = (T0 & 0x40FF0FF8);
1457 4e7a4a4e ths
    env->CP0_WatchHi &= ~(env->CP0_WatchHi & T0 & 0x7);
1458 8c0fdd85 ths
    RETURN();
1459 8c0fdd85 ths
}
1460 8c0fdd85 ths
1461 7a387fff ths
void op_mtc0_xcontext (void)
1462 7a387fff ths
{
1463 9c2149c8 ths
    env->CP0_XContext = (int32_t)T0; /* XXX */
1464 7a387fff ths
    RETURN();
1465 7a387fff ths
}
1466 7a387fff ths
1467 7a387fff ths
void op_mtc0_framemask (void)
1468 7a387fff ths
{
1469 7a387fff ths
    env->CP0_Framemask = T0; /* XXX */
1470 7a387fff ths
    RETURN();
1471 7a387fff ths
}
1472 7a387fff ths
1473 8c0fdd85 ths
void op_mtc0_debug (void)
1474 8c0fdd85 ths
{
1475 8c0fdd85 ths
    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1476 8c0fdd85 ths
    if (T0 & (1 << CP0DB_DM))
1477 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_DM;
1478 8c0fdd85 ths
    else
1479 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_DM;
1480 8c0fdd85 ths
    RETURN();
1481 8c0fdd85 ths
}
1482 8c0fdd85 ths
1483 8c0fdd85 ths
void op_mtc0_depc (void)
1484 8c0fdd85 ths
{
1485 9c2149c8 ths
    env->CP0_DEPC = (int32_t)T0;
1486 8c0fdd85 ths
    RETURN();
1487 8c0fdd85 ths
}
1488 8c0fdd85 ths
1489 7a387fff ths
void op_mtc0_performance0 (void)
1490 7a387fff ths
{
1491 7a387fff ths
    env->CP0_Performance0 = T0; /* XXX */
1492 7a387fff ths
    RETURN();
1493 7a387fff ths
}
1494 7a387fff ths
1495 8c0fdd85 ths
void op_mtc0_taglo (void)
1496 8c0fdd85 ths
{
1497 9c2149c8 ths
    env->CP0_TagLo = T0 & 0xFFFFFCF6;
1498 8c0fdd85 ths
    RETURN();
1499 8c0fdd85 ths
}
1500 8c0fdd85 ths
1501 7a387fff ths
void op_mtc0_datalo (void)
1502 7a387fff ths
{
1503 7a387fff ths
    env->CP0_DataLo = T0; /* XXX */
1504 7a387fff ths
    RETURN();
1505 7a387fff ths
}
1506 7a387fff ths
1507 7a387fff ths
void op_mtc0_taghi (void)
1508 7a387fff ths
{
1509 7a387fff ths
    env->CP0_TagHi = T0; /* XXX */
1510 7a387fff ths
    RETURN();
1511 7a387fff ths
}
1512 7a387fff ths
1513 7a387fff ths
void op_mtc0_datahi (void)
1514 7a387fff ths
{
1515 7a387fff ths
    env->CP0_DataHi = T0; /* XXX */
1516 7a387fff ths
    RETURN();
1517 7a387fff ths
}
1518 7a387fff ths
1519 8c0fdd85 ths
void op_mtc0_errorepc (void)
1520 8c0fdd85 ths
{
1521 9c2149c8 ths
    env->CP0_ErrorEPC = (int32_t)T0;
1522 8c0fdd85 ths
    RETURN();
1523 8c0fdd85 ths
}
1524 8c0fdd85 ths
1525 8c0fdd85 ths
void op_mtc0_desave (void)
1526 8c0fdd85 ths
{
1527 8c0fdd85 ths
    env->CP0_DESAVE = T0;
1528 6af0bf9c bellard
    RETURN();
1529 6af0bf9c bellard
}
1530 6af0bf9c bellard
1531 9c2149c8 ths
void op_dmfc0_entrylo0 (void)
1532 9c2149c8 ths
{
1533 9c2149c8 ths
    T0 = env->CP0_EntryLo0;
1534 9c2149c8 ths
    RETURN();
1535 9c2149c8 ths
}
1536 9c2149c8 ths
1537 9c2149c8 ths
void op_dmfc0_entrylo1 (void)
1538 9c2149c8 ths
{
1539 9c2149c8 ths
    T0 = env->CP0_EntryLo1;
1540 9c2149c8 ths
    RETURN();
1541 9c2149c8 ths
}
1542 9c2149c8 ths
1543 9c2149c8 ths
void op_dmfc0_context (void)
1544 9c2149c8 ths
{
1545 9c2149c8 ths
    T0 = env->CP0_Context;
1546 9c2149c8 ths
    RETURN();
1547 9c2149c8 ths
}
1548 9c2149c8 ths
1549 9c2149c8 ths
void op_dmfc0_badvaddr (void)
1550 9c2149c8 ths
{
1551 9c2149c8 ths
    T0 = env->CP0_BadVAddr;
1552 9c2149c8 ths
    RETURN();
1553 9c2149c8 ths
}
1554 9c2149c8 ths
1555 9c2149c8 ths
void op_dmfc0_entryhi (void)
1556 9c2149c8 ths
{
1557 9c2149c8 ths
    T0 = env->CP0_EntryHi;
1558 9c2149c8 ths
    RETURN();
1559 9c2149c8 ths
}
1560 9c2149c8 ths
1561 9c2149c8 ths
void op_dmfc0_epc (void)
1562 9c2149c8 ths
{
1563 9c2149c8 ths
    T0 = env->CP0_EPC;
1564 9c2149c8 ths
    RETURN();
1565 9c2149c8 ths
}
1566 9c2149c8 ths
1567 9c2149c8 ths
void op_dmfc0_lladdr (void)
1568 9c2149c8 ths
{
1569 9c2149c8 ths
    T0 = env->CP0_LLAddr >> 4;
1570 9c2149c8 ths
    RETURN();
1571 9c2149c8 ths
}
1572 9c2149c8 ths
1573 9c2149c8 ths
void op_dmfc0_watchlo0 (void)
1574 9c2149c8 ths
{
1575 9c2149c8 ths
    T0 = env->CP0_WatchLo;
1576 9c2149c8 ths
    RETURN();
1577 9c2149c8 ths
}
1578 9c2149c8 ths
1579 9c2149c8 ths
void op_dmfc0_xcontext (void)
1580 9c2149c8 ths
{
1581 9c2149c8 ths
    T0 = env->CP0_XContext;
1582 9c2149c8 ths
    RETURN();
1583 9c2149c8 ths
}
1584 9c2149c8 ths
1585 9c2149c8 ths
void op_dmfc0_depc (void)
1586 9c2149c8 ths
{
1587 9c2149c8 ths
    T0 = env->CP0_DEPC;
1588 9c2149c8 ths
    RETURN();
1589 9c2149c8 ths
}
1590 9c2149c8 ths
1591 9c2149c8 ths
void op_dmfc0_errorepc (void)
1592 9c2149c8 ths
{
1593 9c2149c8 ths
    T0 = env->CP0_ErrorEPC;
1594 9c2149c8 ths
    RETURN();
1595 9c2149c8 ths
}
1596 9c2149c8 ths
1597 9c2149c8 ths
void op_dmtc0_entrylo0 (void)
1598 9c2149c8 ths
{
1599 9c2149c8 ths
    /* Large physaddr not implemented */
1600 9c2149c8 ths
    /* 1k pages not implemented */
1601 9c2149c8 ths
    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1602 9c2149c8 ths
    RETURN();
1603 9c2149c8 ths
}
1604 9c2149c8 ths
1605 9c2149c8 ths
void op_dmtc0_entrylo1 (void)
1606 9c2149c8 ths
{
1607 9c2149c8 ths
    /* Large physaddr not implemented */
1608 9c2149c8 ths
    /* 1k pages not implemented */
1609 9c2149c8 ths
    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1610 9c2149c8 ths
    RETURN();
1611 9c2149c8 ths
}
1612 9c2149c8 ths
1613 9c2149c8 ths
void op_dmtc0_context (void)
1614 9c2149c8 ths
{
1615 9c2149c8 ths
    env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
1616 9c2149c8 ths
    RETURN();
1617 9c2149c8 ths
}
1618 9c2149c8 ths
1619 9c2149c8 ths
void op_dmtc0_epc (void)
1620 9c2149c8 ths
{
1621 9c2149c8 ths
    env->CP0_EPC = T0;
1622 9c2149c8 ths
    RETURN();
1623 9c2149c8 ths
}
1624 9c2149c8 ths
1625 9c2149c8 ths
void op_dmtc0_watchlo0 (void)
1626 9c2149c8 ths
{
1627 4e7a4a4e ths
    /* Watch exceptions for instructions, data loads, data stores
1628 4e7a4a4e ths
       not implemented. */
1629 4e7a4a4e ths
    env->CP0_WatchLo = T0 & ~0x7;
1630 9c2149c8 ths
    RETURN();
1631 9c2149c8 ths
}
1632 9c2149c8 ths
1633 9c2149c8 ths
void op_dmtc0_xcontext (void)
1634 9c2149c8 ths
{
1635 9c2149c8 ths
    env->CP0_XContext = T0; /* XXX */
1636 9c2149c8 ths
    RETURN();
1637 9c2149c8 ths
}
1638 9c2149c8 ths
1639 9c2149c8 ths
void op_dmtc0_depc (void)
1640 9c2149c8 ths
{
1641 9c2149c8 ths
    env->CP0_DEPC = T0;
1642 9c2149c8 ths
    RETURN();
1643 9c2149c8 ths
}
1644 9c2149c8 ths
1645 9c2149c8 ths
void op_dmtc0_errorepc (void)
1646 9c2149c8 ths
{
1647 9c2149c8 ths
    env->CP0_ErrorEPC = T0;
1648 9c2149c8 ths
    RETURN();
1649 9c2149c8 ths
}
1650 9c2149c8 ths
1651 6ea83fed bellard
#if 0
1652 6ea83fed bellard
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1653 6ea83fed bellard
#else
1654 6ea83fed bellard
# define DEBUG_FPU_STATE() do { } while(0)
1655 6ea83fed bellard
#endif
1656 6ea83fed bellard
1657 24c7b0e3 ths
void op_cp0_enabled(void)
1658 24c7b0e3 ths
{
1659 24c7b0e3 ths
    if (!(env->CP0_Status & (1 << CP0St_CU0)) &&
1660 24c7b0e3 ths
        (env->hflags & MIPS_HFLAG_UM)) {
1661 1579a72e ths
        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0);
1662 24c7b0e3 ths
    }
1663 24c7b0e3 ths
    RETURN();
1664 24c7b0e3 ths
}
1665 24c7b0e3 ths
1666 6ea83fed bellard
void op_cp1_enabled(void)
1667 6ea83fed bellard
{
1668 6ea83fed bellard
    if (!(env->CP0_Status & (1 << CP0St_CU1))) {
1669 1579a72e ths
        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
1670 6ea83fed bellard
    }
1671 6ea83fed bellard
    RETURN();
1672 6ea83fed bellard
}
1673 6ea83fed bellard
1674 6ea83fed bellard
/* CP1 functions */
1675 6ea83fed bellard
void op_cfc1 (void)
1676 6ea83fed bellard
{
1677 6ea83fed bellard
    if (T1 == 0) {
1678 6ea83fed bellard
        T0 = env->fcr0;
1679 6ea83fed bellard
    }
1680 6ea83fed bellard
    else {
1681 6ea83fed bellard
        /* fetch fcr31, masking unused bits */
1682 6ea83fed bellard
        T0 = env->fcr31 & 0x0183FFFF;
1683 6ea83fed bellard
    }
1684 6ea83fed bellard
    DEBUG_FPU_STATE();
1685 6ea83fed bellard
    RETURN();
1686 6ea83fed bellard
}
1687 6ea83fed bellard
1688 6ea83fed bellard
/* convert MIPS rounding mode in FCR31 to IEEE library */
1689 6ea83fed bellard
unsigned int ieee_rm[] = { 
1690 6ea83fed bellard
    float_round_nearest_even,
1691 6ea83fed bellard
    float_round_to_zero,
1692 6ea83fed bellard
    float_round_up,
1693 6ea83fed bellard
    float_round_down
1694 6ea83fed bellard
};
1695 6ea83fed bellard
1696 6ea83fed bellard
#define RESTORE_ROUNDING_MODE \
1697 6ea83fed bellard
    set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
1698 6ea83fed bellard
1699 6ea83fed bellard
void op_ctc1 (void)
1700 6ea83fed bellard
{
1701 6ea83fed bellard
    if (T1 == 0) {
1702 6ea83fed bellard
        /* XXX should this throw an exception?
1703 6ea83fed bellard
         * don't write to FCR0.
1704 6ea83fed bellard
         * env->fcr0 = T0; 
1705 6ea83fed bellard
         */
1706 6ea83fed bellard
    }
1707 6ea83fed bellard
    else {
1708 6ea83fed bellard
        /* store new fcr31, masking unused bits */  
1709 6ea83fed bellard
        env->fcr31 = T0 & 0x0183FFFF;
1710 6ea83fed bellard
1711 6ea83fed bellard
        /* set rounding mode */
1712 6ea83fed bellard
        RESTORE_ROUNDING_MODE;
1713 6ea83fed bellard
1714 6ea83fed bellard
#ifndef CONFIG_SOFTFLOAT
1715 6ea83fed bellard
        /* no floating point exception for native float */
1716 6ea83fed bellard
        SET_FP_ENABLE(env->fcr31, 0);
1717 6ea83fed bellard
#endif
1718 6ea83fed bellard
    }
1719 6ea83fed bellard
    DEBUG_FPU_STATE();
1720 6ea83fed bellard
    RETURN();
1721 6ea83fed bellard
}
1722 6ea83fed bellard
1723 6ea83fed bellard
void op_mfc1 (void)
1724 6ea83fed bellard
{
1725 6ea83fed bellard
    T0 = WT0;
1726 6ea83fed bellard
    DEBUG_FPU_STATE();
1727 6ea83fed bellard
    RETURN();
1728 6ea83fed bellard
}
1729 6ea83fed bellard
1730 6ea83fed bellard
void op_mtc1 (void)
1731 6ea83fed bellard
{
1732 6ea83fed bellard
    WT0 = T0;
1733 6ea83fed bellard
    DEBUG_FPU_STATE();
1734 6ea83fed bellard
    RETURN();
1735 6ea83fed bellard
}
1736 6ea83fed bellard
1737 6ea83fed bellard
/* Float support.
1738 6ea83fed bellard
   Single precition routines have a "s" suffix, double precision a
1739 6ea83fed bellard
   "d" suffix.  */
1740 6ea83fed bellard
1741 6ea83fed bellard
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1742 6ea83fed bellard
1743 dd016883 bellard
FLOAT_OP(cvtd, s)
1744 dd016883 bellard
{
1745 00a709c7 ths
    FDT2 = float32_to_float64(FST0, &env->fp_status);
1746 dd016883 bellard
    DEBUG_FPU_STATE();
1747 dd016883 bellard
    RETURN();
1748 dd016883 bellard
}
1749 6ea83fed bellard
FLOAT_OP(cvtd, w)
1750 6ea83fed bellard
{
1751 6ea83fed bellard
    FDT2 = int32_to_float64(WT0, &env->fp_status);
1752 6ea83fed bellard
    DEBUG_FPU_STATE();
1753 6ea83fed bellard
    RETURN();
1754 6ea83fed bellard
}
1755 dd016883 bellard
FLOAT_OP(cvts, d)
1756 dd016883 bellard
{
1757 417f38f0 pbrook
    FST2 = float64_to_float32(FDT0, &env->fp_status);
1758 dd016883 bellard
    DEBUG_FPU_STATE();
1759 dd016883 bellard
    RETURN();
1760 dd016883 bellard
}
1761 6ea83fed bellard
FLOAT_OP(cvts, w)
1762 6ea83fed bellard
{
1763 6ea83fed bellard
    FST2 = int32_to_float32(WT0, &env->fp_status);
1764 6ea83fed bellard
    DEBUG_FPU_STATE();
1765 6ea83fed bellard
    RETURN();
1766 6ea83fed bellard
}
1767 6ea83fed bellard
FLOAT_OP(cvtw, s)
1768 6ea83fed bellard
{
1769 6ea83fed bellard
    WT2 = float32_to_int32(FST0, &env->fp_status);
1770 6ea83fed bellard
    DEBUG_FPU_STATE();
1771 6ea83fed bellard
    RETURN();
1772 6ea83fed bellard
}
1773 6ea83fed bellard
FLOAT_OP(cvtw, d)
1774 6ea83fed bellard
{
1775 6ea83fed bellard
    WT2 = float64_to_int32(FDT0, &env->fp_status);
1776 6ea83fed bellard
    DEBUG_FPU_STATE();
1777 6ea83fed bellard
    RETURN();
1778 6ea83fed bellard
}
1779 6ea83fed bellard
1780 6ea83fed bellard
FLOAT_OP(roundw, d)
1781 6ea83fed bellard
{
1782 6ea83fed bellard
    set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1783 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1784 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1785 6ea83fed bellard
1786 6ea83fed bellard
    DEBUG_FPU_STATE();
1787 6ea83fed bellard
    RETURN();
1788 6ea83fed bellard
}
1789 6ea83fed bellard
FLOAT_OP(roundw, s)
1790 6ea83fed bellard
{
1791 6ea83fed bellard
    set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1792 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1793 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1794 6ea83fed bellard
    DEBUG_FPU_STATE();
1795 6ea83fed bellard
    RETURN();
1796 6ea83fed bellard
}
1797 6ea83fed bellard
1798 6ea83fed bellard
FLOAT_OP(truncw, d)
1799 6ea83fed bellard
{
1800 6ea83fed bellard
    WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status);
1801 6ea83fed bellard
    DEBUG_FPU_STATE();
1802 6ea83fed bellard
    RETURN();
1803 6ea83fed bellard
}
1804 6ea83fed bellard
FLOAT_OP(truncw, s)
1805 6ea83fed bellard
{
1806 6ea83fed bellard
    WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status);
1807 6ea83fed bellard
    DEBUG_FPU_STATE();
1808 6ea83fed bellard
    RETURN();
1809 6ea83fed bellard
}
1810 6ea83fed bellard
1811 6ea83fed bellard
FLOAT_OP(ceilw, d)
1812 6ea83fed bellard
{
1813 6ea83fed bellard
    set_float_rounding_mode(float_round_up, &env->fp_status);
1814 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1815 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1816 6ea83fed bellard
1817 6ea83fed bellard
    DEBUG_FPU_STATE();
1818 6ea83fed bellard
    RETURN();
1819 6ea83fed bellard
}
1820 6ea83fed bellard
FLOAT_OP(ceilw, s)
1821 6ea83fed bellard
{
1822 6ea83fed bellard
    set_float_rounding_mode(float_round_up, &env->fp_status);
1823 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1824 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1825 6ea83fed bellard
    DEBUG_FPU_STATE();
1826 6ea83fed bellard
    RETURN();
1827 6ea83fed bellard
}
1828 6ea83fed bellard
1829 6ea83fed bellard
FLOAT_OP(floorw, d)
1830 6ea83fed bellard
{
1831 6ea83fed bellard
    set_float_rounding_mode(float_round_down, &env->fp_status);
1832 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1833 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1834 6ea83fed bellard
1835 6ea83fed bellard
    DEBUG_FPU_STATE();
1836 6ea83fed bellard
    RETURN();
1837 6ea83fed bellard
}
1838 6ea83fed bellard
FLOAT_OP(floorw, s)
1839 6ea83fed bellard
{
1840 6ea83fed bellard
    set_float_rounding_mode(float_round_down, &env->fp_status);
1841 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1842 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1843 6ea83fed bellard
    DEBUG_FPU_STATE();
1844 6ea83fed bellard
    RETURN();
1845 6ea83fed bellard
}
1846 6ea83fed bellard
1847 6ea83fed bellard
/* binary operations */
1848 6ea83fed bellard
#define FLOAT_BINOP(name) \
1849 6ea83fed bellard
FLOAT_OP(name, d)         \
1850 6ea83fed bellard
{                         \
1851 6ea83fed bellard
    FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status);    \
1852 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1853 6ea83fed bellard
}                         \
1854 6ea83fed bellard
FLOAT_OP(name, s)         \
1855 6ea83fed bellard
{                         \
1856 6ea83fed bellard
    FST2 = float32_ ## name (FST0, FST1, &env->fp_status);    \
1857 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1858 6ea83fed bellard
}
1859 6ea83fed bellard
FLOAT_BINOP(add)
1860 6ea83fed bellard
FLOAT_BINOP(sub)
1861 6ea83fed bellard
FLOAT_BINOP(mul)
1862 6ea83fed bellard
FLOAT_BINOP(div)
1863 6ea83fed bellard
#undef FLOAT_BINOP
1864 6ea83fed bellard
1865 6ea83fed bellard
/* unary operations, modifying fp status  */
1866 6ea83fed bellard
#define FLOAT_UNOP(name)  \
1867 6ea83fed bellard
FLOAT_OP(name, d)         \
1868 6ea83fed bellard
{                         \
1869 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0, &env->fp_status);   \
1870 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1871 6ea83fed bellard
}                         \
1872 6ea83fed bellard
FLOAT_OP(name, s)         \
1873 6ea83fed bellard
{                         \
1874 6ea83fed bellard
    FST2 = float32_ ## name(FST0, &env->fp_status);   \
1875 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1876 6ea83fed bellard
}
1877 6ea83fed bellard
FLOAT_UNOP(sqrt)
1878 6ea83fed bellard
#undef FLOAT_UNOP
1879 6ea83fed bellard
1880 6ea83fed bellard
/* unary operations, not modifying fp status  */
1881 6ea83fed bellard
#define FLOAT_UNOP(name)  \
1882 6ea83fed bellard
FLOAT_OP(name, d)         \
1883 6ea83fed bellard
{                         \
1884 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0);   \
1885 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1886 6ea83fed bellard
}                         \
1887 6ea83fed bellard
FLOAT_OP(name, s)         \
1888 6ea83fed bellard
{                         \
1889 6ea83fed bellard
    FST2 = float32_ ## name(FST0);   \
1890 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1891 6ea83fed bellard
}
1892 6ea83fed bellard
FLOAT_UNOP(abs)
1893 6ea83fed bellard
FLOAT_UNOP(chs)
1894 6ea83fed bellard
#undef FLOAT_UNOP
1895 6ea83fed bellard
1896 6ea83fed bellard
FLOAT_OP(mov, d)
1897 6ea83fed bellard
{
1898 6ea83fed bellard
    FDT2 = FDT0;
1899 6ea83fed bellard
    DEBUG_FPU_STATE();
1900 6ea83fed bellard
    RETURN();
1901 6ea83fed bellard
}
1902 6ea83fed bellard
FLOAT_OP(mov, s)
1903 6ea83fed bellard
{
1904 6ea83fed bellard
    FST2 = FST0;
1905 6ea83fed bellard
    DEBUG_FPU_STATE();
1906 6ea83fed bellard
    RETURN();
1907 6ea83fed bellard
}
1908 6ea83fed bellard
1909 6ea83fed bellard
#ifdef CONFIG_SOFTFLOAT
1910 6ea83fed bellard
#define clear_invalid() do {                                \
1911 6ea83fed bellard
    int flags = get_float_exception_flags(&env->fp_status); \
1912 6ea83fed bellard
    flags &= ~float_flag_invalid;                           \
1913 6ea83fed bellard
    set_float_exception_flags(flags, &env->fp_status);      \
1914 6ea83fed bellard
} while(0)
1915 6ea83fed bellard
#else
1916 6ea83fed bellard
#define clear_invalid() do { } while(0)
1917 6ea83fed bellard
#endif
1918 6ea83fed bellard
1919 6ea83fed bellard
extern void dump_fpu_s(CPUState *env);
1920 6ea83fed bellard
1921 6ea83fed bellard
#define FOP_COND(fmt, op, sig, cond)           \
1922 6ea83fed bellard
void op_cmp_ ## fmt ## _ ## op (void)          \
1923 6ea83fed bellard
{                                              \
1924 6ea83fed bellard
    if (cond)                                  \
1925 6ea83fed bellard
        SET_FP_COND(env->fcr31);               \
1926 6ea83fed bellard
    else                                       \
1927 6ea83fed bellard
        CLEAR_FP_COND(env->fcr31);             \
1928 6ea83fed bellard
    if (!sig)                                  \
1929 6ea83fed bellard
        clear_invalid();                       \
1930 6ea83fed bellard
    /*CALL_FROM_TB1(dump_fpu_s, env);*/ \
1931 6ea83fed bellard
    DEBUG_FPU_STATE();                         \
1932 6ea83fed bellard
    RETURN();                                  \
1933 6ea83fed bellard
}
1934 6ea83fed bellard
1935 569f5d66 bellard
int float64_is_unordered(float64 a, float64 b STATUS_PARAM)
1936 6ea83fed bellard
{
1937 6ea83fed bellard
    if (float64_is_nan(a) || float64_is_nan(b)) {
1938 6ea83fed bellard
        float_raise(float_flag_invalid, status);
1939 6ea83fed bellard
        return 1;
1940 6ea83fed bellard
    }
1941 6ea83fed bellard
    else {
1942 6ea83fed bellard
        return 0;
1943 6ea83fed bellard
    }
1944 6ea83fed bellard
}
1945 6ea83fed bellard
1946 6ea83fed bellard
FOP_COND(d, f,   0,                                                      0) 
1947 6ea83fed bellard
FOP_COND(d, un,  0, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1948 6ea83fed bellard
FOP_COND(d, eq,  0,                                                      float64_eq(FDT0, FDT1, &env->fp_status))
1949 6ea83fed bellard
FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1950 6ea83fed bellard
FOP_COND(d, olt, 0,                                                      float64_lt(FDT0, FDT1, &env->fp_status))
1951 6ea83fed bellard
FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1952 6ea83fed bellard
FOP_COND(d, ole, 0,                                                      float64_le(FDT0, FDT1, &env->fp_status))
1953 6ea83fed bellard
FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1954 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1955 6ea83fed bellard
 * but float*_is_unordered() is still called
1956 6ea83fed bellard
 */
1957 6ea83fed bellard
FOP_COND(d, sf,  1,                                                      (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0))
1958 6ea83fed bellard
FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1959 6ea83fed bellard
FOP_COND(d, seq, 1,                                                      float64_eq(FDT0, FDT1, &env->fp_status))
1960 6ea83fed bellard
FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1961 6ea83fed bellard
FOP_COND(d, lt,  1,                                                      float64_lt(FDT0, FDT1, &env->fp_status))
1962 6ea83fed bellard
FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1963 6ea83fed bellard
FOP_COND(d, le,  1,                                                      float64_le(FDT0, FDT1, &env->fp_status))
1964 6ea83fed bellard
FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1965 6ea83fed bellard
1966 6ea83fed bellard
flag float32_is_unordered(float32 a, float32 b STATUS_PARAM)
1967 6ea83fed bellard
{
1968 6ea83fed bellard
    extern flag float32_is_nan( float32 a );
1969 6ea83fed bellard
    if (float32_is_nan(a) || float32_is_nan(b)) {
1970 6ea83fed bellard
        float_raise(float_flag_invalid, status);
1971 6ea83fed bellard
        return 1;
1972 6ea83fed bellard
    }
1973 6ea83fed bellard
    else {
1974 6ea83fed bellard
        return 0;
1975 6ea83fed bellard
    }
1976 6ea83fed bellard
}
1977 6ea83fed bellard
1978 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1979 6ea83fed bellard
 * but float*_is_unordered() is still called
1980 6ea83fed bellard
 */
1981 6ea83fed bellard
FOP_COND(s, f,   0,                                                      0) 
1982 6ea83fed bellard
FOP_COND(s, un,  0, float32_is_unordered(FST1, FST0, &env->fp_status))
1983 6ea83fed bellard
FOP_COND(s, eq,  0,                                                      float32_eq(FST0, FST1, &env->fp_status))
1984 6ea83fed bellard
FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1985 6ea83fed bellard
FOP_COND(s, olt, 0,                                                      float32_lt(FST0, FST1, &env->fp_status))
1986 6ea83fed bellard
FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1987 6ea83fed bellard
FOP_COND(s, ole, 0,                                                      float32_le(FST0, FST1, &env->fp_status))
1988 6ea83fed bellard
FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1989 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1990 6ea83fed bellard
 * but float*_is_unordered() is still called
1991 6ea83fed bellard
 */
1992 6ea83fed bellard
FOP_COND(s, sf,  1,                                                      (float32_is_unordered(FST0, FST1, &env->fp_status), 0))
1993 6ea83fed bellard
FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status))
1994 6ea83fed bellard
FOP_COND(s, seq, 1,                                                      float32_eq(FST0, FST1, &env->fp_status))
1995 6ea83fed bellard
FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1996 6ea83fed bellard
FOP_COND(s, lt,  1,                                                      float32_lt(FST0, FST1, &env->fp_status))
1997 6ea83fed bellard
FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1998 6ea83fed bellard
FOP_COND(s, le,  1,                                                      float32_le(FST0, FST1, &env->fp_status))
1999 6ea83fed bellard
FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
2000 6ea83fed bellard
2001 6ea83fed bellard
void op_bc1f (void)
2002 6ea83fed bellard
{
2003 6ea83fed bellard
    T0 = ! IS_FP_COND_SET(env->fcr31);
2004 6ea83fed bellard
    DEBUG_FPU_STATE();
2005 6ea83fed bellard
    RETURN();
2006 6ea83fed bellard
}
2007 6ea83fed bellard
2008 6ea83fed bellard
void op_bc1t (void)
2009 6ea83fed bellard
{
2010 6ea83fed bellard
    T0 = IS_FP_COND_SET(env->fcr31);
2011 6ea83fed bellard
    DEBUG_FPU_STATE();
2012 6ea83fed bellard
    RETURN();
2013 6ea83fed bellard
}
2014 6ea83fed bellard
2015 6af0bf9c bellard
#if defined(MIPS_USES_R4K_TLB)
2016 6af0bf9c bellard
void op_tlbwi (void)
2017 6af0bf9c bellard
{
2018 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbwi);
2019 6af0bf9c bellard
    RETURN();
2020 6af0bf9c bellard
}
2021 6af0bf9c bellard
2022 6af0bf9c bellard
void op_tlbwr (void)
2023 6af0bf9c bellard
{
2024 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbwr);
2025 6af0bf9c bellard
    RETURN();
2026 6af0bf9c bellard
}
2027 6af0bf9c bellard
2028 6af0bf9c bellard
void op_tlbp (void)
2029 6af0bf9c bellard
{
2030 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbp);
2031 6af0bf9c bellard
    RETURN();
2032 6af0bf9c bellard
}
2033 6af0bf9c bellard
2034 6af0bf9c bellard
void op_tlbr (void)
2035 6af0bf9c bellard
{
2036 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbr);
2037 6af0bf9c bellard
    RETURN();
2038 6af0bf9c bellard
}
2039 6af0bf9c bellard
#endif
2040 6af0bf9c bellard
2041 6af0bf9c bellard
/* Specials */
2042 6f5b89a0 ths
#if defined (CONFIG_USER_ONLY)
2043 6f5b89a0 ths
void op_tls_value (void)
2044 6f5b89a0 ths
{
2045 6f5b89a0 ths
  T0 = env->tls_value;
2046 6f5b89a0 ths
}
2047 6f5b89a0 ths
#endif
2048 6f5b89a0 ths
2049 6af0bf9c bellard
void op_pmon (void)
2050 6af0bf9c bellard
{
2051 6af0bf9c bellard
    CALL_FROM_TB1(do_pmon, PARAM1);
2052 7a387fff ths
    RETURN();
2053 7a387fff ths
}
2054 7a387fff ths
2055 7a387fff ths
void op_di (void)
2056 7a387fff ths
{
2057 7a387fff ths
    T0 = env->CP0_Status;
2058 4de9b249 ths
    env->CP0_Status = T0 & ~(1 << CP0St_IE);
2059 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2060 7a387fff ths
    RETURN();
2061 7a387fff ths
}
2062 7a387fff ths
2063 7a387fff ths
void op_ei (void)
2064 7a387fff ths
{
2065 7a387fff ths
    T0 = env->CP0_Status;
2066 4de9b249 ths
    env->CP0_Status = T0 | (1 << CP0St_IE);
2067 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2068 7a387fff ths
    RETURN();
2069 6af0bf9c bellard
}
2070 6af0bf9c bellard
2071 6af0bf9c bellard
void op_trap (void)
2072 6af0bf9c bellard
{
2073 6af0bf9c bellard
    if (T0) {
2074 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);
2075 6af0bf9c bellard
    }
2076 6af0bf9c bellard
    RETURN();
2077 6af0bf9c bellard
}
2078 6af0bf9c bellard
2079 4ad40f36 bellard
void op_debug (void)
2080 4ad40f36 bellard
{
2081 7a387fff ths
    CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2082 7a387fff ths
    RETURN();
2083 4ad40f36 bellard
}
2084 4ad40f36 bellard
2085 6af0bf9c bellard
void op_set_lladdr (void)
2086 6af0bf9c bellard
{
2087 6af0bf9c bellard
    env->CP0_LLAddr = T2;
2088 7a387fff ths
    RETURN();
2089 6af0bf9c bellard
}
2090 6af0bf9c bellard
2091 f41c52f1 ths
void debug_pre_eret (void);
2092 f41c52f1 ths
void debug_post_eret (void);
2093 6af0bf9c bellard
void op_eret (void)
2094 6af0bf9c bellard
{
2095 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2096 f41c52f1 ths
        CALL_FROM_TB0(debug_pre_eret);
2097 24c7b0e3 ths
    if (env->CP0_Status & (1 << CP0St_ERL)) {
2098 6af0bf9c bellard
        env->PC = env->CP0_ErrorEPC;
2099 24c7b0e3 ths
        env->CP0_Status &= ~(1 << CP0St_ERL);
2100 51e11d9e bellard
    } else {
2101 6af0bf9c bellard
        env->PC = env->CP0_EPC;
2102 24c7b0e3 ths
        env->CP0_Status &= ~(1 << CP0St_EXL);
2103 51e11d9e bellard
    }
2104 24c7b0e3 ths
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2105 24c7b0e3 ths
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
2106 24c7b0e3 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
2107 24c7b0e3 ths
        (env->CP0_Status & (1 << CP0St_UM)))
2108 24c7b0e3 ths
        env->hflags |= MIPS_HFLAG_UM;
2109 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2110 f41c52f1 ths
        CALL_FROM_TB0(debug_post_eret);
2111 6af0bf9c bellard
    env->CP0_LLAddr = 1;
2112 7a387fff ths
    RETURN();
2113 6af0bf9c bellard
}
2114 6af0bf9c bellard
2115 6af0bf9c bellard
void op_deret (void)
2116 6af0bf9c bellard
{
2117 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2118 f41c52f1 ths
        CALL_FROM_TB0(debug_pre_eret);
2119 6af0bf9c bellard
    env->PC = env->CP0_DEPC;
2120 24c7b0e3 ths
    env->hflags |= MIPS_HFLAG_DM;
2121 24c7b0e3 ths
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2122 24c7b0e3 ths
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
2123 24c7b0e3 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
2124 24c7b0e3 ths
        (env->CP0_Status & (1 << CP0St_UM)))
2125 24c7b0e3 ths
        env->hflags |= MIPS_HFLAG_UM;
2126 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2127 f41c52f1 ths
        CALL_FROM_TB0(debug_post_eret);
2128 24c7b0e3 ths
    env->CP0_LLAddr = 1;
2129 7a387fff ths
    RETURN();
2130 7a387fff ths
}
2131 7a387fff ths
2132 7a387fff ths
void op_rdhwr_cpunum(void)
2133 7a387fff ths
{
2134 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2135 97428a4d ths
        (env->CP0_HWREna & (1 << 0)) ||
2136 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2137 1579a72e ths
        T0 = env->CP0_EBase & 0x3ff;
2138 7a387fff ths
    else
2139 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2140 7a387fff ths
    RETURN();
2141 7a387fff ths
}
2142 7a387fff ths
2143 7a387fff ths
void op_rdhwr_synci_step(void)
2144 7a387fff ths
{
2145 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2146 97428a4d ths
        (env->CP0_HWREna & (1 << 1)) ||
2147 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2148 1579a72e ths
        T0 = env->SYNCI_Step;
2149 7a387fff ths
    else
2150 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2151 7a387fff ths
    RETURN();
2152 7a387fff ths
}
2153 7a387fff ths
2154 7a387fff ths
void op_rdhwr_cc(void)
2155 7a387fff ths
{
2156 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2157 97428a4d ths
        (env->CP0_HWREna & (1 << 2)) ||
2158 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2159 1579a72e ths
        T0 = env->CP0_Count;
2160 7a387fff ths
    else
2161 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2162 7a387fff ths
    RETURN();
2163 7a387fff ths
}
2164 7a387fff ths
2165 7a387fff ths
void op_rdhwr_ccres(void)
2166 7a387fff ths
{
2167 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2168 97428a4d ths
        (env->CP0_HWREna & (1 << 3)) ||
2169 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2170 1579a72e ths
        T0 = env->CCRes;
2171 7a387fff ths
    else
2172 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2173 1579a72e ths
    RETURN();
2174 1579a72e ths
}
2175 1579a72e ths
2176 6af0bf9c bellard
void op_save_state (void)
2177 6af0bf9c bellard
{
2178 6af0bf9c bellard
    env->hflags = PARAM1;
2179 6af0bf9c bellard
    RETURN();
2180 6af0bf9c bellard
}
2181 6af0bf9c bellard
2182 6af0bf9c bellard
void op_save_pc (void)
2183 6af0bf9c bellard
{
2184 6af0bf9c bellard
    env->PC = PARAM1;
2185 6af0bf9c bellard
    RETURN();
2186 6af0bf9c bellard
}
2187 6af0bf9c bellard
2188 6af0bf9c bellard
void op_raise_exception (void)
2189 6af0bf9c bellard
{
2190 6af0bf9c bellard
    CALL_FROM_TB1(do_raise_exception, PARAM1);
2191 6af0bf9c bellard
    RETURN();
2192 6af0bf9c bellard
}
2193 6af0bf9c bellard
2194 6af0bf9c bellard
void op_raise_exception_err (void)
2195 6af0bf9c bellard
{
2196 6af0bf9c bellard
    CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
2197 6af0bf9c bellard
    RETURN();
2198 6af0bf9c bellard
}
2199 6af0bf9c bellard
2200 6af0bf9c bellard
void op_exit_tb (void)
2201 6af0bf9c bellard
{
2202 6af0bf9c bellard
    EXIT_TB();
2203 7a387fff ths
    RETURN();
2204 6af0bf9c bellard
}
2205 6af0bf9c bellard
2206 4ad40f36 bellard
void op_wait (void)
2207 4ad40f36 bellard
{
2208 4ad40f36 bellard
    env->halted = 1;
2209 4ad40f36 bellard
    CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
2210 7a387fff ths
    RETURN();
2211 7a387fff ths
}
2212 7a387fff ths
2213 7a387fff ths
/* Bitfield operations. */
2214 7a387fff ths
void op_ext(void)
2215 7a387fff ths
{
2216 7a387fff ths
    unsigned int pos = PARAM1;
2217 7a387fff ths
    unsigned int size = PARAM2;
2218 7a387fff ths
2219 f757d6ff ths
    T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
2220 7a387fff ths
    RETURN();
2221 7a387fff ths
}
2222 7a387fff ths
2223 7a387fff ths
void op_ins(void)
2224 7a387fff ths
{
2225 7a387fff ths
    unsigned int pos = PARAM1;
2226 7a387fff ths
    unsigned int size = PARAM2;
2227 f757d6ff ths
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2228 7a387fff ths
2229 c570fd16 ths
    T0 = (T2 & ~mask) | (((uint32_t)T1 << pos) & mask);
2230 7a387fff ths
    RETURN();
2231 7a387fff ths
}
2232 7a387fff ths
2233 7a387fff ths
void op_wsbh(void)
2234 7a387fff ths
{
2235 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
2236 7a387fff ths
    RETURN();
2237 7a387fff ths
}
2238 7a387fff ths
2239 60aa19ab ths
#ifdef TARGET_MIPS64
2240 c570fd16 ths
void op_dext(void)
2241 c570fd16 ths
{
2242 c570fd16 ths
    unsigned int pos = PARAM1;
2243 c570fd16 ths
    unsigned int size = PARAM2;
2244 c570fd16 ths
2245 f757d6ff ths
    T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
2246 c570fd16 ths
    RETURN();
2247 c570fd16 ths
}
2248 c570fd16 ths
2249 c570fd16 ths
void op_dins(void)
2250 c570fd16 ths
{
2251 c570fd16 ths
    unsigned int pos = PARAM1;
2252 c570fd16 ths
    unsigned int size = PARAM2;
2253 f757d6ff ths
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2254 c570fd16 ths
2255 c570fd16 ths
    T0 = (T2 & ~mask) | ((T1 << pos) & mask);
2256 c570fd16 ths
    RETURN();
2257 c570fd16 ths
}
2258 c570fd16 ths
2259 7a387fff ths
void op_dsbh(void)
2260 7a387fff ths
{
2261 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
2262 7a387fff ths
    RETURN();
2263 7a387fff ths
}
2264 7a387fff ths
2265 7a387fff ths
void op_dshd(void)
2266 7a387fff ths
{
2267 7a387fff ths
    T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
2268 7a387fff ths
    RETURN();
2269 7a387fff ths
}
2270 c570fd16 ths
#endif
2271 7a387fff ths
2272 7a387fff ths
void op_seb(void)
2273 7a387fff ths
{
2274 7a387fff ths
    T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
2275 7a387fff ths
    RETURN();
2276 7a387fff ths
}
2277 7a387fff ths
2278 7a387fff ths
void op_seh(void)
2279 7a387fff ths
{
2280 7a387fff ths
    T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
2281 7a387fff ths
    RETURN();
2282 4ad40f36 bellard
}