Revision e9ebed4d target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 350 | 350 |
// 'a' versions allowed to user depending on asi |
| 351 | 351 |
#if defined(CONFIG_USER_ONLY) |
| 352 | 352 |
#define supervisor(dc) 0 |
| 353 |
#define hypervisor(dc) 0 |
|
| 353 | 354 |
#define gen_op_ldst(name) gen_op_##name##_raw() |
| 354 | 355 |
#define OP_LD_TABLE(width) \ |
| 355 | 356 |
static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \ |
| ... | ... | |
| 405 | 406 |
} |
| 406 | 407 |
|
| 407 | 408 |
#define supervisor(dc) (dc->mem_idx == 1) |
| 409 |
#define hypervisor(dc) (dc->mem_idx == 2) |
|
| 408 | 410 |
#endif |
| 409 | 411 |
#else |
| 410 | 412 |
#if defined(CONFIG_USER_ONLY) |
| ... | ... | |
| 1218 | 1220 |
goto illegal_insn; |
| 1219 | 1221 |
} |
| 1220 | 1222 |
#if !defined(CONFIG_USER_ONLY) |
| 1223 |
} else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
|
|
| 1221 | 1224 |
#ifndef TARGET_SPARC64 |
| 1222 |
} else if (xop == 0x29) { /* rdpsr / V9 unimp */
|
|
| 1223 | 1225 |
if (!supervisor(dc)) |
| 1224 | 1226 |
goto priv_insn; |
| 1225 | 1227 |
gen_op_rdpsr(); |
| 1228 |
#else |
|
| 1229 |
if (!hypervisor(dc)) |
|
| 1230 |
goto priv_insn; |
|
| 1231 |
rs1 = GET_FIELD(insn, 13, 17); |
|
| 1232 |
switch (rs1) {
|
|
| 1233 |
case 0: // hpstate |
|
| 1234 |
// gen_op_rdhpstate(); |
|
| 1235 |
break; |
|
| 1236 |
case 1: // htstate |
|
| 1237 |
// gen_op_rdhtstate(); |
|
| 1238 |
break; |
|
| 1239 |
case 3: // hintp |
|
| 1240 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp)); |
|
| 1241 |
break; |
|
| 1242 |
case 5: // htba |
|
| 1243 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, htba)); |
|
| 1244 |
break; |
|
| 1245 |
case 6: // hver |
|
| 1246 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, hver)); |
|
| 1247 |
break; |
|
| 1248 |
case 31: // hstick_cmpr |
|
| 1249 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); |
|
| 1250 |
break; |
|
| 1251 |
default: |
|
| 1252 |
goto illegal_insn; |
|
| 1253 |
} |
|
| 1254 |
#endif |
|
| 1226 | 1255 |
gen_movl_T0_reg(rd); |
| 1227 | 1256 |
break; |
| 1228 |
#endif |
|
| 1229 | 1257 |
} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
|
| 1230 | 1258 |
if (!supervisor(dc)) |
| 1231 | 1259 |
goto priv_insn; |
| ... | ... | |
| 1277 | 1305 |
case 14: // wstate |
| 1278 | 1306 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); |
| 1279 | 1307 |
break; |
| 1308 |
case 16: // UA2005 gl |
|
| 1309 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, gl)); |
|
| 1310 |
break; |
|
| 1311 |
case 26: // UA2005 strand status |
|
| 1312 |
if (!hypervisor(dc)) |
|
| 1313 |
goto priv_insn; |
|
| 1314 |
gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr)); |
|
| 1315 |
break; |
|
| 1280 | 1316 |
case 31: // ver |
| 1281 | 1317 |
gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); |
| 1282 | 1318 |
break; |
| ... | ... | |
| 1997 | 2033 |
case 1: |
| 1998 | 2034 |
gen_op_restored(); |
| 1999 | 2035 |
break; |
| 2036 |
case 2: /* UA2005 allclean */ |
|
| 2037 |
case 3: /* UA2005 otherw */ |
|
| 2038 |
case 4: /* UA2005 normalw */ |
|
| 2039 |
case 5: /* UA2005 invalw */ |
|
| 2040 |
// XXX |
|
| 2000 | 2041 |
default: |
| 2001 | 2042 |
goto illegal_insn; |
| 2002 | 2043 |
} |
| ... | ... | |
| 2068 | 2109 |
case 14: // wstate |
| 2069 | 2110 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); |
| 2070 | 2111 |
break; |
| 2112 |
case 16: // UA2005 gl |
|
| 2113 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, gl)); |
|
| 2114 |
break; |
|
| 2115 |
case 26: // UA2005 strand status |
|
| 2116 |
if (!hypervisor(dc)) |
|
| 2117 |
goto priv_insn; |
|
| 2118 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr)); |
|
| 2119 |
break; |
|
| 2071 | 2120 |
default: |
| 2072 | 2121 |
goto illegal_insn; |
| 2073 | 2122 |
} |
| ... | ... | |
| 2076 | 2125 |
#endif |
| 2077 | 2126 |
} |
| 2078 | 2127 |
break; |
| 2079 |
#ifndef TARGET_SPARC64 |
|
| 2080 |
case 0x33: /* wrtbr, V9 unimp */ |
|
| 2128 |
case 0x33: /* wrtbr, UA2005 wrhpr */ |
|
| 2081 | 2129 |
{
|
| 2130 |
#ifndef TARGET_SPARC64 |
|
| 2082 | 2131 |
if (!supervisor(dc)) |
| 2083 | 2132 |
goto priv_insn; |
| 2084 | 2133 |
gen_op_xor_T1_T0(); |
| 2085 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
|
| 2134 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
|
| 2135 |
#else |
|
| 2136 |
if (!hypervisor(dc)) |
|
| 2137 |
goto priv_insn; |
|
| 2138 |
gen_op_xor_T1_T0(); |
|
| 2139 |
switch (rd) {
|
|
| 2140 |
case 0: // hpstate |
|
| 2141 |
// XXX gen_op_wrhpstate(); |
|
| 2142 |
save_state(dc); |
|
| 2143 |
gen_op_next_insn(); |
|
| 2144 |
gen_op_movl_T0_0(); |
|
| 2145 |
gen_op_exit_tb(); |
|
| 2146 |
dc->is_br = 1; |
|
| 2147 |
break; |
|
| 2148 |
case 1: // htstate |
|
| 2149 |
// XXX gen_op_wrhtstate(); |
|
| 2150 |
break; |
|
| 2151 |
case 3: // hintp |
|
| 2152 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp)); |
|
| 2153 |
break; |
|
| 2154 |
case 5: // htba |
|
| 2155 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); |
|
| 2156 |
break; |
|
| 2157 |
case 31: // hstick_cmpr |
|
| 2158 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); |
|
| 2159 |
break; |
|
| 2160 |
case 6: // hver readonly |
|
| 2161 |
default: |
|
| 2162 |
goto illegal_insn; |
|
| 2163 |
} |
|
| 2164 |
#endif |
|
| 2086 | 2165 |
} |
| 2087 | 2166 |
break; |
| 2088 | 2167 |
#endif |
| 2089 |
#endif |
|
| 2090 | 2168 |
#ifdef TARGET_SPARC64 |
| 2091 | 2169 |
case 0x2c: /* V9 movcc */ |
| 2092 | 2170 |
{
|
| ... | ... | |
| 2164 | 2242 |
int opf = GET_FIELD_SP(insn, 5, 13); |
| 2165 | 2243 |
rs1 = GET_FIELD(insn, 13, 17); |
| 2166 | 2244 |
rs2 = GET_FIELD(insn, 27, 31); |
| 2245 |
if (gen_trap_ifnofpu(dc)) |
|
| 2246 |
goto jmp_insn; |
|
| 2167 | 2247 |
|
| 2168 | 2248 |
switch (opf) {
|
| 2249 |
case 0x000: /* VIS I edge8cc */ |
|
| 2250 |
case 0x001: /* VIS II edge8n */ |
|
| 2251 |
case 0x002: /* VIS I edge8lcc */ |
|
| 2252 |
case 0x003: /* VIS II edge8ln */ |
|
| 2253 |
case 0x004: /* VIS I edge16cc */ |
|
| 2254 |
case 0x005: /* VIS II edge16n */ |
|
| 2255 |
case 0x006: /* VIS I edge16lcc */ |
|
| 2256 |
case 0x007: /* VIS II edge16ln */ |
|
| 2257 |
case 0x008: /* VIS I edge32cc */ |
|
| 2258 |
case 0x009: /* VIS II edge32n */ |
|
| 2259 |
case 0x00a: /* VIS I edge32lcc */ |
|
| 2260 |
case 0x00b: /* VIS II edge32ln */ |
|
| 2261 |
// XXX |
|
| 2262 |
goto illegal_insn; |
|
| 2263 |
case 0x010: /* VIS I array8 */ |
|
| 2264 |
gen_movl_reg_T0(rs1); |
|
| 2265 |
gen_movl_reg_T1(rs2); |
|
| 2266 |
gen_op_array8(); |
|
| 2267 |
gen_movl_T0_reg(rd); |
|
| 2268 |
break; |
|
| 2269 |
case 0x012: /* VIS I array16 */ |
|
| 2270 |
gen_movl_reg_T0(rs1); |
|
| 2271 |
gen_movl_reg_T1(rs2); |
|
| 2272 |
gen_op_array16(); |
|
| 2273 |
gen_movl_T0_reg(rd); |
|
| 2274 |
break; |
|
| 2275 |
case 0x014: /* VIS I array32 */ |
|
| 2276 |
gen_movl_reg_T0(rs1); |
|
| 2277 |
gen_movl_reg_T1(rs2); |
|
| 2278 |
gen_op_array32(); |
|
| 2279 |
gen_movl_T0_reg(rd); |
|
| 2280 |
break; |
|
| 2169 | 2281 |
case 0x018: /* VIS I alignaddr */ |
| 2170 |
if (gen_trap_ifnofpu(dc)) |
|
| 2171 |
goto jmp_insn; |
|
| 2172 | 2282 |
gen_movl_reg_T0(rs1); |
| 2173 | 2283 |
gen_movl_reg_T1(rs2); |
| 2174 | 2284 |
gen_op_alignaddr(); |
| 2175 | 2285 |
gen_movl_T0_reg(rd); |
| 2176 | 2286 |
break; |
| 2287 |
case 0x019: /* VIS II bmask */ |
|
| 2177 | 2288 |
case 0x01a: /* VIS I alignaddrl */ |
| 2178 |
if (gen_trap_ifnofpu(dc)) |
|
| 2179 |
goto jmp_insn; |
|
| 2180 | 2289 |
// XXX |
| 2290 |
goto illegal_insn; |
|
| 2291 |
case 0x020: /* VIS I fcmple16 */ |
|
| 2292 |
gen_op_load_fpr_DT0(rs1); |
|
| 2293 |
gen_op_load_fpr_DT1(rs2); |
|
| 2294 |
gen_op_fcmple16(); |
|
| 2295 |
gen_op_store_DT0_fpr(rd); |
|
| 2296 |
break; |
|
| 2297 |
case 0x022: /* VIS I fcmpne16 */ |
|
| 2298 |
gen_op_load_fpr_DT0(rs1); |
|
| 2299 |
gen_op_load_fpr_DT1(rs2); |
|
| 2300 |
gen_op_fcmpne16(); |
|
| 2301 |
gen_op_store_DT0_fpr(rd); |
|
| 2181 | 2302 |
break; |
| 2303 |
case 0x024: /* VIS I fcmple32 */ |
|
| 2304 |
gen_op_load_fpr_DT0(rs1); |
|
| 2305 |
gen_op_load_fpr_DT1(rs2); |
|
| 2306 |
gen_op_fcmple32(); |
|
| 2307 |
gen_op_store_DT0_fpr(rd); |
|
| 2308 |
break; |
|
| 2309 |
case 0x026: /* VIS I fcmpne32 */ |
|
| 2310 |
gen_op_load_fpr_DT0(rs1); |
|
| 2311 |
gen_op_load_fpr_DT1(rs2); |
|
| 2312 |
gen_op_fcmpne32(); |
|
| 2313 |
gen_op_store_DT0_fpr(rd); |
|
| 2314 |
break; |
|
| 2315 |
case 0x028: /* VIS I fcmpgt16 */ |
|
| 2316 |
gen_op_load_fpr_DT0(rs1); |
|
| 2317 |
gen_op_load_fpr_DT1(rs2); |
|
| 2318 |
gen_op_fcmpgt16(); |
|
| 2319 |
gen_op_store_DT0_fpr(rd); |
|
| 2320 |
break; |
|
| 2321 |
case 0x02a: /* VIS I fcmpeq16 */ |
|
| 2322 |
gen_op_load_fpr_DT0(rs1); |
|
| 2323 |
gen_op_load_fpr_DT1(rs2); |
|
| 2324 |
gen_op_fcmpeq16(); |
|
| 2325 |
gen_op_store_DT0_fpr(rd); |
|
| 2326 |
break; |
|
| 2327 |
case 0x02c: /* VIS I fcmpgt32 */ |
|
| 2328 |
gen_op_load_fpr_DT0(rs1); |
|
| 2329 |
gen_op_load_fpr_DT1(rs2); |
|
| 2330 |
gen_op_fcmpgt32(); |
|
| 2331 |
gen_op_store_DT0_fpr(rd); |
|
| 2332 |
break; |
|
| 2333 |
case 0x02e: /* VIS I fcmpeq32 */ |
|
| 2334 |
gen_op_load_fpr_DT0(rs1); |
|
| 2335 |
gen_op_load_fpr_DT1(rs2); |
|
| 2336 |
gen_op_fcmpeq32(); |
|
| 2337 |
gen_op_store_DT0_fpr(rd); |
|
| 2338 |
break; |
|
| 2339 |
case 0x031: /* VIS I fmul8x16 */ |
|
| 2340 |
gen_op_load_fpr_DT0(rs1); |
|
| 2341 |
gen_op_load_fpr_DT1(rs2); |
|
| 2342 |
gen_op_fmul8x16(); |
|
| 2343 |
gen_op_store_DT0_fpr(rd); |
|
| 2344 |
break; |
|
| 2345 |
case 0x033: /* VIS I fmul8x16au */ |
|
| 2346 |
gen_op_load_fpr_DT0(rs1); |
|
| 2347 |
gen_op_load_fpr_DT1(rs2); |
|
| 2348 |
gen_op_fmul8x16au(); |
|
| 2349 |
gen_op_store_DT0_fpr(rd); |
|
| 2350 |
break; |
|
| 2351 |
case 0x035: /* VIS I fmul8x16al */ |
|
| 2352 |
gen_op_load_fpr_DT0(rs1); |
|
| 2353 |
gen_op_load_fpr_DT1(rs2); |
|
| 2354 |
gen_op_fmul8x16al(); |
|
| 2355 |
gen_op_store_DT0_fpr(rd); |
|
| 2356 |
break; |
|
| 2357 |
case 0x036: /* VIS I fmul8sux16 */ |
|
| 2358 |
gen_op_load_fpr_DT0(rs1); |
|
| 2359 |
gen_op_load_fpr_DT1(rs2); |
|
| 2360 |
gen_op_fmul8sux16(); |
|
| 2361 |
gen_op_store_DT0_fpr(rd); |
|
| 2362 |
break; |
|
| 2363 |
case 0x037: /* VIS I fmul8ulx16 */ |
|
| 2364 |
gen_op_load_fpr_DT0(rs1); |
|
| 2365 |
gen_op_load_fpr_DT1(rs2); |
|
| 2366 |
gen_op_fmul8ulx16(); |
|
| 2367 |
gen_op_store_DT0_fpr(rd); |
|
| 2368 |
break; |
|
| 2369 |
case 0x038: /* VIS I fmuld8sux16 */ |
|
| 2370 |
gen_op_load_fpr_DT0(rs1); |
|
| 2371 |
gen_op_load_fpr_DT1(rs2); |
|
| 2372 |
gen_op_fmuld8sux16(); |
|
| 2373 |
gen_op_store_DT0_fpr(rd); |
|
| 2374 |
break; |
|
| 2375 |
case 0x039: /* VIS I fmuld8ulx16 */ |
|
| 2376 |
gen_op_load_fpr_DT0(rs1); |
|
| 2377 |
gen_op_load_fpr_DT1(rs2); |
|
| 2378 |
gen_op_fmuld8ulx16(); |
|
| 2379 |
gen_op_store_DT0_fpr(rd); |
|
| 2380 |
break; |
|
| 2381 |
case 0x03a: /* VIS I fpack32 */ |
|
| 2382 |
case 0x03b: /* VIS I fpack16 */ |
|
| 2383 |
case 0x03d: /* VIS I fpackfix */ |
|
| 2384 |
case 0x03e: /* VIS I pdist */ |
|
| 2385 |
// XXX |
|
| 2386 |
goto illegal_insn; |
|
| 2182 | 2387 |
case 0x048: /* VIS I faligndata */ |
| 2183 |
if (gen_trap_ifnofpu(dc)) |
|
| 2184 |
goto jmp_insn; |
|
| 2185 | 2388 |
gen_op_load_fpr_DT0(rs1); |
| 2186 | 2389 |
gen_op_load_fpr_DT1(rs2); |
| 2187 | 2390 |
gen_op_faligndata(); |
| 2188 | 2391 |
gen_op_store_DT0_fpr(rd); |
| 2189 | 2392 |
break; |
| 2393 |
case 0x04b: /* VIS I fpmerge */ |
|
| 2394 |
gen_op_load_fpr_DT0(rs1); |
|
| 2395 |
gen_op_load_fpr_DT1(rs2); |
|
| 2396 |
gen_op_fpmerge(); |
|
| 2397 |
gen_op_store_DT0_fpr(rd); |
|
| 2398 |
break; |
|
| 2399 |
case 0x04c: /* VIS II bshuffle */ |
|
| 2400 |
// XXX |
|
| 2401 |
goto illegal_insn; |
|
| 2402 |
case 0x04d: /* VIS I fexpand */ |
|
| 2403 |
gen_op_load_fpr_DT0(rs1); |
|
| 2404 |
gen_op_load_fpr_DT1(rs2); |
|
| 2405 |
gen_op_fexpand(); |
|
| 2406 |
gen_op_store_DT0_fpr(rd); |
|
| 2407 |
break; |
|
| 2408 |
case 0x050: /* VIS I fpadd16 */ |
|
| 2409 |
gen_op_load_fpr_DT0(rs1); |
|
| 2410 |
gen_op_load_fpr_DT1(rs2); |
|
| 2411 |
gen_op_fpadd16(); |
|
| 2412 |
gen_op_store_DT0_fpr(rd); |
|
| 2413 |
break; |
|
| 2414 |
case 0x051: /* VIS I fpadd16s */ |
|
| 2415 |
gen_op_load_fpr_FT0(rs1); |
|
| 2416 |
gen_op_load_fpr_FT1(rs2); |
|
| 2417 |
gen_op_fpadd16s(); |
|
| 2418 |
gen_op_store_FT0_fpr(rd); |
|
| 2419 |
break; |
|
| 2420 |
case 0x052: /* VIS I fpadd32 */ |
|
| 2421 |
gen_op_load_fpr_DT0(rs1); |
|
| 2422 |
gen_op_load_fpr_DT1(rs2); |
|
| 2423 |
gen_op_fpadd32(); |
|
| 2424 |
gen_op_store_DT0_fpr(rd); |
|
| 2425 |
break; |
|
| 2426 |
case 0x053: /* VIS I fpadd32s */ |
|
| 2427 |
gen_op_load_fpr_FT0(rs1); |
|
| 2428 |
gen_op_load_fpr_FT1(rs2); |
|
| 2429 |
gen_op_fpadd32s(); |
|
| 2430 |
gen_op_store_FT0_fpr(rd); |
|
| 2431 |
break; |
|
| 2432 |
case 0x054: /* VIS I fpsub16 */ |
|
| 2433 |
gen_op_load_fpr_DT0(rs1); |
|
| 2434 |
gen_op_load_fpr_DT1(rs2); |
|
| 2435 |
gen_op_fpsub16(); |
|
| 2436 |
gen_op_store_DT0_fpr(rd); |
|
| 2437 |
break; |
|
| 2438 |
case 0x055: /* VIS I fpsub16s */ |
|
| 2439 |
gen_op_load_fpr_FT0(rs1); |
|
| 2440 |
gen_op_load_fpr_FT1(rs2); |
|
| 2441 |
gen_op_fpsub16s(); |
|
| 2442 |
gen_op_store_FT0_fpr(rd); |
|
| 2443 |
break; |
|
| 2444 |
case 0x056: /* VIS I fpsub32 */ |
|
| 2445 |
gen_op_load_fpr_DT0(rs1); |
|
| 2446 |
gen_op_load_fpr_DT1(rs2); |
|
| 2447 |
gen_op_fpadd32(); |
|
| 2448 |
gen_op_store_DT0_fpr(rd); |
|
| 2449 |
break; |
|
| 2450 |
case 0x057: /* VIS I fpsub32s */ |
|
| 2451 |
gen_op_load_fpr_FT0(rs1); |
|
| 2452 |
gen_op_load_fpr_FT1(rs2); |
|
| 2453 |
gen_op_fpsub32s(); |
|
| 2454 |
gen_op_store_FT0_fpr(rd); |
|
| 2455 |
break; |
|
| 2190 | 2456 |
case 0x060: /* VIS I fzero */ |
| 2191 |
if (gen_trap_ifnofpu(dc)) |
|
| 2192 |
goto jmp_insn; |
|
| 2193 | 2457 |
gen_op_movl_DT0_0(); |
| 2194 | 2458 |
gen_op_store_DT0_fpr(rd); |
| 2195 | 2459 |
break; |
| 2196 | 2460 |
case 0x061: /* VIS I fzeros */ |
| 2197 |
if (gen_trap_ifnofpu(dc)) |
|
| 2198 |
goto jmp_insn; |
|
| 2199 | 2461 |
gen_op_movl_FT0_0(); |
| 2200 | 2462 |
gen_op_store_FT0_fpr(rd); |
| 2201 | 2463 |
break; |
| 2464 |
case 0x062: /* VIS I fnor */ |
|
| 2465 |
gen_op_load_fpr_DT0(rs1); |
|
| 2466 |
gen_op_load_fpr_DT1(rs2); |
|
| 2467 |
gen_op_fnor(); |
|
| 2468 |
gen_op_store_DT0_fpr(rd); |
|
| 2469 |
break; |
|
| 2470 |
case 0x063: /* VIS I fnors */ |
|
| 2471 |
gen_op_load_fpr_FT0(rs1); |
|
| 2472 |
gen_op_load_fpr_FT1(rs2); |
|
| 2473 |
gen_op_fnors(); |
|
| 2474 |
gen_op_store_FT0_fpr(rd); |
|
| 2475 |
break; |
|
| 2476 |
case 0x064: /* VIS I fandnot2 */ |
|
| 2477 |
gen_op_load_fpr_DT1(rs1); |
|
| 2478 |
gen_op_load_fpr_DT0(rs2); |
|
| 2479 |
gen_op_fandnot(); |
|
| 2480 |
gen_op_store_DT0_fpr(rd); |
|
| 2481 |
break; |
|
| 2482 |
case 0x065: /* VIS I fandnot2s */ |
|
| 2483 |
gen_op_load_fpr_FT1(rs1); |
|
| 2484 |
gen_op_load_fpr_FT0(rs2); |
|
| 2485 |
gen_op_fandnots(); |
|
| 2486 |
gen_op_store_FT0_fpr(rd); |
|
| 2487 |
break; |
|
| 2488 |
case 0x066: /* VIS I fnot2 */ |
|
| 2489 |
gen_op_load_fpr_DT1(rs2); |
|
| 2490 |
gen_op_fnot(); |
|
| 2491 |
gen_op_store_DT0_fpr(rd); |
|
| 2492 |
break; |
|
| 2493 |
case 0x067: /* VIS I fnot2s */ |
|
| 2494 |
gen_op_load_fpr_FT1(rs2); |
|
| 2495 |
gen_op_fnot(); |
|
| 2496 |
gen_op_store_FT0_fpr(rd); |
|
| 2497 |
break; |
|
| 2498 |
case 0x068: /* VIS I fandnot1 */ |
|
| 2499 |
gen_op_load_fpr_DT0(rs1); |
|
| 2500 |
gen_op_load_fpr_DT1(rs2); |
|
| 2501 |
gen_op_fandnot(); |
|
| 2502 |
gen_op_store_DT0_fpr(rd); |
|
| 2503 |
break; |
|
| 2504 |
case 0x069: /* VIS I fandnot1s */ |
|
| 2505 |
gen_op_load_fpr_FT0(rs1); |
|
| 2506 |
gen_op_load_fpr_FT1(rs2); |
|
| 2507 |
gen_op_fandnots(); |
|
| 2508 |
gen_op_store_FT0_fpr(rd); |
|
| 2509 |
break; |
|
| 2510 |
case 0x06a: /* VIS I fnot1 */ |
|
| 2511 |
gen_op_load_fpr_DT1(rs1); |
|
| 2512 |
gen_op_fnot(); |
|
| 2513 |
gen_op_store_DT0_fpr(rd); |
|
| 2514 |
break; |
|
| 2515 |
case 0x06b: /* VIS I fnot1s */ |
|
| 2516 |
gen_op_load_fpr_FT1(rs1); |
|
| 2517 |
gen_op_fnot(); |
|
| 2518 |
gen_op_store_FT0_fpr(rd); |
|
| 2519 |
break; |
|
| 2520 |
case 0x06c: /* VIS I fxor */ |
|
| 2521 |
gen_op_load_fpr_DT0(rs1); |
|
| 2522 |
gen_op_load_fpr_DT1(rs2); |
|
| 2523 |
gen_op_fxor(); |
|
| 2524 |
gen_op_store_DT0_fpr(rd); |
|
| 2525 |
break; |
|
| 2526 |
case 0x06d: /* VIS I fxors */ |
|
| 2527 |
gen_op_load_fpr_FT0(rs1); |
|
| 2528 |
gen_op_load_fpr_FT1(rs2); |
|
| 2529 |
gen_op_fxors(); |
|
| 2530 |
gen_op_store_FT0_fpr(rd); |
|
| 2531 |
break; |
|
| 2532 |
case 0x06e: /* VIS I fnand */ |
|
| 2533 |
gen_op_load_fpr_DT0(rs1); |
|
| 2534 |
gen_op_load_fpr_DT1(rs2); |
|
| 2535 |
gen_op_fnand(); |
|
| 2536 |
gen_op_store_DT0_fpr(rd); |
|
| 2537 |
break; |
|
| 2538 |
case 0x06f: /* VIS I fnands */ |
|
| 2539 |
gen_op_load_fpr_FT0(rs1); |
|
| 2540 |
gen_op_load_fpr_FT1(rs2); |
|
| 2541 |
gen_op_fnands(); |
|
| 2542 |
gen_op_store_FT0_fpr(rd); |
|
| 2543 |
break; |
|
| 2544 |
case 0x070: /* VIS I fand */ |
|
| 2545 |
gen_op_load_fpr_DT0(rs1); |
|
| 2546 |
gen_op_load_fpr_DT1(rs2); |
|
| 2547 |
gen_op_fand(); |
|
| 2548 |
gen_op_store_DT0_fpr(rd); |
|
| 2549 |
break; |
|
| 2550 |
case 0x071: /* VIS I fands */ |
|
| 2551 |
gen_op_load_fpr_FT0(rs1); |
|
| 2552 |
gen_op_load_fpr_FT1(rs2); |
|
| 2553 |
gen_op_fands(); |
|
| 2554 |
gen_op_store_FT0_fpr(rd); |
|
| 2555 |
break; |
|
| 2556 |
case 0x072: /* VIS I fxnor */ |
|
| 2557 |
gen_op_load_fpr_DT0(rs1); |
|
| 2558 |
gen_op_load_fpr_DT1(rs2); |
|
| 2559 |
gen_op_fxnor(); |
|
| 2560 |
gen_op_store_DT0_fpr(rd); |
|
| 2561 |
break; |
|
| 2562 |
case 0x073: /* VIS I fxnors */ |
|
| 2563 |
gen_op_load_fpr_FT0(rs1); |
|
| 2564 |
gen_op_load_fpr_FT1(rs2); |
|
| 2565 |
gen_op_fxnors(); |
|
| 2566 |
gen_op_store_FT0_fpr(rd); |
|
| 2567 |
break; |
|
| 2202 | 2568 |
case 0x074: /* VIS I fsrc1 */ |
| 2203 |
if (gen_trap_ifnofpu(dc)) |
|
| 2204 |
goto jmp_insn; |
|
| 2205 | 2569 |
gen_op_load_fpr_DT0(rs1); |
| 2206 | 2570 |
gen_op_store_DT0_fpr(rd); |
| 2207 | 2571 |
break; |
| 2208 | 2572 |
case 0x075: /* VIS I fsrc1s */ |
| 2209 |
if (gen_trap_ifnofpu(dc)) |
|
| 2210 |
goto jmp_insn; |
|
| 2211 | 2573 |
gen_op_load_fpr_FT0(rs1); |
| 2212 | 2574 |
gen_op_store_FT0_fpr(rd); |
| 2213 | 2575 |
break; |
| 2576 |
case 0x076: /* VIS I fornot2 */ |
|
| 2577 |
gen_op_load_fpr_DT1(rs1); |
|
| 2578 |
gen_op_load_fpr_DT0(rs2); |
|
| 2579 |
gen_op_fornot(); |
|
| 2580 |
gen_op_store_DT0_fpr(rd); |
|
| 2581 |
break; |
|
| 2582 |
case 0x077: /* VIS I fornot2s */ |
|
| 2583 |
gen_op_load_fpr_FT1(rs1); |
|
| 2584 |
gen_op_load_fpr_FT0(rs2); |
|
| 2585 |
gen_op_fornots(); |
|
| 2586 |
gen_op_store_FT0_fpr(rd); |
|
| 2587 |
break; |
|
| 2214 | 2588 |
case 0x078: /* VIS I fsrc2 */ |
| 2215 |
if (gen_trap_ifnofpu(dc)) |
|
| 2216 |
goto jmp_insn; |
|
| 2217 | 2589 |
gen_op_load_fpr_DT0(rs2); |
| 2218 | 2590 |
gen_op_store_DT0_fpr(rd); |
| 2219 | 2591 |
break; |
| 2220 | 2592 |
case 0x079: /* VIS I fsrc2s */ |
| 2221 |
if (gen_trap_ifnofpu(dc)) |
|
| 2222 |
goto jmp_insn; |
|
| 2223 | 2593 |
gen_op_load_fpr_FT0(rs2); |
| 2224 | 2594 |
gen_op_store_FT0_fpr(rd); |
| 2225 | 2595 |
break; |
| 2596 |
case 0x07a: /* VIS I fornot1 */ |
|
| 2597 |
gen_op_load_fpr_DT0(rs1); |
|
| 2598 |
gen_op_load_fpr_DT1(rs2); |
|
| 2599 |
gen_op_fornot(); |
|
| 2600 |
gen_op_store_DT0_fpr(rd); |
|
| 2601 |
break; |
|
| 2602 |
case 0x07b: /* VIS I fornot1s */ |
|
| 2603 |
gen_op_load_fpr_FT0(rs1); |
|
| 2604 |
gen_op_load_fpr_FT1(rs2); |
|
| 2605 |
gen_op_fornots(); |
|
| 2606 |
gen_op_store_FT0_fpr(rd); |
|
| 2607 |
break; |
|
| 2608 |
case 0x07c: /* VIS I for */ |
|
| 2609 |
gen_op_load_fpr_DT0(rs1); |
|
| 2610 |
gen_op_load_fpr_DT1(rs2); |
|
| 2611 |
gen_op_for(); |
|
| 2612 |
gen_op_store_DT0_fpr(rd); |
|
| 2613 |
break; |
|
| 2614 |
case 0x07d: /* VIS I fors */ |
|
| 2615 |
gen_op_load_fpr_FT0(rs1); |
|
| 2616 |
gen_op_load_fpr_FT1(rs2); |
|
| 2617 |
gen_op_fors(); |
|
| 2618 |
gen_op_store_FT0_fpr(rd); |
|
| 2619 |
break; |
|
| 2226 | 2620 |
case 0x07e: /* VIS I fone */ |
| 2227 |
if (gen_trap_ifnofpu(dc)) |
|
| 2228 |
goto jmp_insn; |
|
| 2229 | 2621 |
gen_op_movl_DT0_1(); |
| 2230 | 2622 |
gen_op_store_DT0_fpr(rd); |
| 2231 | 2623 |
break; |
| 2232 | 2624 |
case 0x07f: /* VIS I fones */ |
| 2233 |
if (gen_trap_ifnofpu(dc)) |
|
| 2234 |
goto jmp_insn; |
|
| 2235 | 2625 |
gen_op_movl_FT0_1(); |
| 2236 | 2626 |
gen_op_store_FT0_fpr(rd); |
| 2237 | 2627 |
break; |
| 2628 |
case 0x080: /* VIS I shutdown */ |
|
| 2629 |
case 0x081: /* VIS II siam */ |
|
| 2630 |
// XXX |
|
| 2631 |
goto illegal_insn; |
|
| 2238 | 2632 |
default: |
| 2239 | 2633 |
goto illegal_insn; |
| 2240 | 2634 |
} |
Also available in: Unified diff