Revision ea6cf6be target-sh4/translate.c
| b/target-sh4/translate.c | ||
|---|---|---|
| 131 | 131 |
#endif |
| 132 | 132 |
env->vbr = 0; |
| 133 | 133 |
env->pc = 0xA0000000; |
| 134 |
env->fpscr = 0x00040001; |
|
| 134 |
#if defined(CONFIG_USER_ONLY) |
|
| 135 |
env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ |
|
| 136 |
env->fp_status.float_rounding_mode = float_round_nearest_even; /* ?! */ |
|
| 137 |
#else |
|
| 138 |
env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ |
|
| 139 |
env->fp_status.float_rounding_mode = float_round_to_zero; |
|
| 140 |
#endif |
|
| 135 | 141 |
env->mmucr = 0; |
| 136 | 142 |
} |
| 137 | 143 |
|
| ... | ... | |
| 238 | 244 |
#define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
| 239 | 245 |
#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
| 240 | 246 |
#define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
| 247 |
#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ |
|
| 241 | 248 |
|
| 242 | 249 |
#define CHECK_NOT_DELAY_SLOT \ |
| 243 | 250 |
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \ |
| ... | ... | |
| 768 | 775 |
gen_op_stfl_FT0_T1(ctx); |
| 769 | 776 |
} |
| 770 | 777 |
return; |
| 778 |
case 0xf000: /* fadd Rm,Rn */ |
|
| 779 |
case 0xf001: /* fsub Rm,Rn */ |
|
| 780 |
case 0xf002: /* fmul Rm,Rn */ |
|
| 781 |
case 0xf003: /* fdiv Rm,Rn */ |
|
| 782 |
case 0xf004: /* fcmp/eq Rm,Rn */ |
|
| 783 |
case 0xf005: /* fcmp/gt Rm,Rn */ |
|
| 784 |
if (ctx->fpscr & FPSCR_PR) {
|
|
| 785 |
if (ctx->opcode & 0x0110) |
|
| 786 |
break; /* illegal instruction */ |
|
| 787 |
gen_op_fmov_drN_DT1(DREG(B7_4)); |
|
| 788 |
gen_op_fmov_drN_DT0(DREG(B11_8)); |
|
| 789 |
} |
|
| 790 |
else {
|
|
| 791 |
gen_op_fmov_frN_FT1(FREG(B7_4)); |
|
| 792 |
gen_op_fmov_frN_FT0(FREG(B11_8)); |
|
| 793 |
} |
|
| 794 |
|
|
| 795 |
switch (ctx->opcode & 0xf00f) {
|
|
| 796 |
case 0xf000: /* fadd Rm,Rn */ |
|
| 797 |
ctx->fpscr & FPSCR_PR ? gen_op_fadd_DT() : gen_op_fadd_FT(); |
|
| 798 |
break; |
|
| 799 |
case 0xf001: /* fsub Rm,Rn */ |
|
| 800 |
ctx->fpscr & FPSCR_PR ? gen_op_fsub_DT() : gen_op_fsub_FT(); |
|
| 801 |
break; |
|
| 802 |
case 0xf002: /* fmul Rm,Rn */ |
|
| 803 |
ctx->fpscr & FPSCR_PR ? gen_op_fmul_DT() : gen_op_fmul_FT(); |
|
| 804 |
break; |
|
| 805 |
case 0xf003: /* fdiv Rm,Rn */ |
|
| 806 |
ctx->fpscr & FPSCR_PR ? gen_op_fdiv_DT() : gen_op_fdiv_FT(); |
|
| 807 |
break; |
|
| 808 |
case 0xf004: /* fcmp/eq Rm,Rn */ |
|
| 809 |
return; |
|
| 810 |
case 0xf005: /* fcmp/gt Rm,Rn */ |
|
| 811 |
return; |
|
| 812 |
} |
|
| 813 |
|
|
| 814 |
if (ctx->fpscr & FPSCR_PR) {
|
|
| 815 |
gen_op_fmov_DT0_drN(DREG(B11_8)); |
|
| 816 |
} |
|
| 817 |
else {
|
|
| 818 |
gen_op_fmov_FT0_frN(FREG(B11_8)); |
|
| 819 |
} |
|
| 820 |
return; |
|
| 771 | 821 |
} |
| 772 | 822 |
|
| 773 | 823 |
switch (ctx->opcode & 0xff00) {
|
| ... | ... | |
| 1079 | 1129 |
gen_op_fmov_frN_FT0(FREG(B11_8)); |
| 1080 | 1130 |
gen_op_movl_FT0_fpul(); |
| 1081 | 1131 |
return; |
| 1132 |
case 0xf02d: /* float FPUL,FRn/DRn */ |
|
| 1133 |
if (ctx->fpscr & FPSCR_PR) {
|
|
| 1134 |
if (ctx->opcode & 0x0100) |
|
| 1135 |
break; /* illegal instruction */ |
|
| 1136 |
gen_op_float_DT(); |
|
| 1137 |
gen_op_fmov_DT0_drN(DREG(B11_8)); |
|
| 1138 |
} |
|
| 1139 |
else {
|
|
| 1140 |
gen_op_float_FT(); |
|
| 1141 |
gen_op_fmov_FT0_frN(FREG(B11_8)); |
|
| 1142 |
} |
|
| 1143 |
return; |
|
| 1144 |
case 0xf03d: /* ftrc FRm/DRm,FPUL */ |
|
| 1145 |
if (ctx->fpscr & FPSCR_PR) {
|
|
| 1146 |
if (ctx->opcode & 0x0100) |
|
| 1147 |
break; /* illegal instruction */ |
|
| 1148 |
gen_op_fmov_drN_DT0(DREG(B11_8)); |
|
| 1149 |
gen_op_ftrc_DT(); |
|
| 1150 |
} |
|
| 1151 |
else {
|
|
| 1152 |
gen_op_fmov_frN_FT0(FREG(B11_8)); |
|
| 1153 |
gen_op_ftrc_FT(); |
|
| 1154 |
} |
|
| 1155 |
return; |
|
| 1156 |
case 0xf08d: /* fldi0 FRn */ |
|
| 1157 |
if (!(ctx->fpscr & FPSCR_PR)) {
|
|
| 1158 |
gen_op_movl_imm_T0(0); |
|
| 1159 |
gen_op_fmov_T0_frN(FREG(B11_8)); |
|
| 1160 |
return; |
|
| 1161 |
} |
|
| 1162 |
break; |
|
| 1163 |
case 0xf09d: /* fldi1 FRn */ |
|
| 1164 |
if (!(ctx->fpscr & FPSCR_PR)) {
|
|
| 1165 |
gen_op_movl_imm_T0(0x3f800000); |
|
| 1166 |
gen_op_fmov_T0_frN(FREG(B11_8)); |
|
| 1167 |
return; |
|
| 1168 |
} |
|
| 1169 |
break; |
|
| 1082 | 1170 |
} |
| 1083 | 1171 |
|
| 1084 | 1172 |
fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", |
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