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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 6af0bf9c | bellard | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | e37e863f | bellard | #include <stdarg.h> |
21 | e37e863f | bellard | #include <stdlib.h> |
22 | e37e863f | bellard | #include <stdio.h> |
23 | e37e863f | bellard | #include <string.h> |
24 | e37e863f | bellard | #include <inttypes.h> |
25 | e37e863f | bellard | #include <signal.h> |
26 | e37e863f | bellard | #include <assert.h> |
27 | e37e863f | bellard | |
28 | e37e863f | bellard | #include "cpu.h" |
29 | e37e863f | bellard | #include "exec-all.h" |
30 | 6af0bf9c | bellard | |
31 | 43057ab1 | bellard | enum {
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32 | 43057ab1 | bellard | TLBRET_DIRTY = -4,
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33 | 43057ab1 | bellard | TLBRET_INVALID = -3,
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34 | 43057ab1 | bellard | TLBRET_NOMATCH = -2,
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35 | 43057ab1 | bellard | TLBRET_BADADDR = -1,
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36 | 43057ab1 | bellard | TLBRET_MATCH = 0
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37 | 43057ab1 | bellard | }; |
38 | 43057ab1 | bellard | |
39 | 6af0bf9c | bellard | /* MIPS32 4K MMU emulation */
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40 | 9fb63ac2 | bellard | #ifdef MIPS_USES_R4K_TLB
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41 | 6af0bf9c | bellard | static int map_address (CPUState *env, target_ulong *physical, int *prot, |
42 | 6af0bf9c | bellard | target_ulong address, int rw, int access_type) |
43 | 6af0bf9c | bellard | { |
44 | 3b1c8be4 | ths | int i;
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45 | 6af0bf9c | bellard | |
46 | 814b9a47 | ths | for (i = 0; i < env->tlb_in_use; i++) { |
47 | 3b1c8be4 | ths | tlb_t *tlb = &env->tlb[i]; |
48 | 3b1c8be4 | ths | /* 1k pages are not supported. */
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49 | 3b1c8be4 | ths | uint8_t ASID = env->CP0_EntryHi & 0xFF;
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50 | 3b1c8be4 | ths | target_ulong mask = tlb->PageMask | 0x1FFF;
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51 | 3b1c8be4 | ths | target_ulong tag = address & ~mask; |
52 | 3b1c8be4 | ths | int n;
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53 | 3b1c8be4 | ths | |
54 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
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55 | 6af0bf9c | bellard | if ((tlb->G == 1 || tlb->ASID == ASID) && |
56 | bc814401 | ths | tlb->VPN == tag) { |
57 | 6af0bf9c | bellard | /* TLB match */
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58 | 3b1c8be4 | ths | n = !!(address & mask & ~(mask >> 1));
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59 | 6af0bf9c | bellard | /* Check access rights */
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60 | 43057ab1 | bellard | if (!(n ? tlb->V1 : tlb->V0))
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61 | 43057ab1 | bellard | return TLBRET_INVALID;
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62 | 43057ab1 | bellard | if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
63 | 3b1c8be4 | ths | *physical = tlb->PFN[n] | (address & (mask >> 1));
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64 | 9fb63ac2 | bellard | *prot = PAGE_READ; |
65 | 98c1b82b | pbrook | if (n ? tlb->D1 : tlb->D0)
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66 | 9fb63ac2 | bellard | *prot |= PAGE_WRITE; |
67 | 43057ab1 | bellard | return TLBRET_MATCH;
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68 | 6af0bf9c | bellard | } |
69 | 43057ab1 | bellard | return TLBRET_DIRTY;
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70 | 6af0bf9c | bellard | } |
71 | 6af0bf9c | bellard | } |
72 | 43057ab1 | bellard | return TLBRET_NOMATCH;
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73 | 6af0bf9c | bellard | } |
74 | 6af0bf9c | bellard | #endif
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75 | 6af0bf9c | bellard | |
76 | 43057ab1 | bellard | static int get_physical_address (CPUState *env, target_ulong *physical, |
77 | 43057ab1 | bellard | int *prot, target_ulong address,
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78 | 43057ab1 | bellard | int rw, int access_type) |
79 | 6af0bf9c | bellard | { |
80 | 6af0bf9c | bellard | /* User mode can only access useg */
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81 | 43057ab1 | bellard | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
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82 | 43057ab1 | bellard | int ret = TLBRET_MATCH;
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83 | 43057ab1 | bellard | |
84 | 6af0bf9c | bellard | #if 0
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85 | 6af0bf9c | bellard | if (logfile) {
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86 | 6af0bf9c | bellard | fprintf(logfile, "user mode %d h %08x\n",
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87 | 6af0bf9c | bellard | user_mode, env->hflags);
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88 | 6af0bf9c | bellard | }
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89 | 6af0bf9c | bellard | #endif
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90 | 6af0bf9c | bellard | if (user_mode && address > 0x7FFFFFFFUL) |
91 | 43057ab1 | bellard | return TLBRET_BADADDR;
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92 | 5dc4b744 | ths | if (address < (int32_t)0x80000000UL) { |
93 | 9fb63ac2 | bellard | if (!(env->hflags & MIPS_HFLAG_ERL)) {
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94 | 9fb63ac2 | bellard | #ifdef MIPS_USES_R4K_TLB
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95 | 9fb63ac2 | bellard | ret = map_address(env, physical, prot, address, rw, access_type); |
96 | 6af0bf9c | bellard | #else
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97 | 6af0bf9c | bellard | *physical = address + 0x40000000UL;
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98 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
99 | 6af0bf9c | bellard | #endif
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100 | 6af0bf9c | bellard | } else {
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101 | 6af0bf9c | bellard | *physical = address; |
102 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
103 | 6af0bf9c | bellard | } |
104 | 5dc4b744 | ths | } else if (address < (int32_t)0xA0000000UL) { |
105 | 6af0bf9c | bellard | /* kseg0 */
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106 | 6af0bf9c | bellard | /* XXX: check supervisor mode */
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107 | 5dc4b744 | ths | *physical = address - (int32_t)0x80000000UL;
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108 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
109 | 5dc4b744 | ths | } else if (address < (int32_t)0xC0000000UL) { |
110 | 6af0bf9c | bellard | /* kseg1 */
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111 | 6af0bf9c | bellard | /* XXX: check supervisor mode */
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112 | 5dc4b744 | ths | *physical = address - (int32_t)0xA0000000UL;
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113 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
114 | 5dc4b744 | ths | } else if (address < (int32_t)0xE0000000UL) { |
115 | 6af0bf9c | bellard | /* kseg2 */
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116 | 9fb63ac2 | bellard | #ifdef MIPS_USES_R4K_TLB
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117 | 9fb63ac2 | bellard | ret = map_address(env, physical, prot, address, rw, access_type); |
118 | 6af0bf9c | bellard | #else
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119 | 6af0bf9c | bellard | *physical = address; |
120 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
121 | 6af0bf9c | bellard | #endif
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122 | 6af0bf9c | bellard | } else {
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123 | 6af0bf9c | bellard | /* kseg3 */
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124 | 6af0bf9c | bellard | /* XXX: check supervisor mode */
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125 | 6af0bf9c | bellard | /* XXX: debug segment is not emulated */
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126 | 9fb63ac2 | bellard | #ifdef MIPS_USES_R4K_TLB
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127 | 9fb63ac2 | bellard | ret = map_address(env, physical, prot, address, rw, access_type); |
128 | 6af0bf9c | bellard | #else
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129 | 6af0bf9c | bellard | *physical = address; |
130 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
131 | 6af0bf9c | bellard | #endif
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132 | 6af0bf9c | bellard | } |
133 | 6af0bf9c | bellard | #if 0
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134 | 6af0bf9c | bellard | if (logfile) {
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135 | c570fd16 | ths | fprintf(logfile, TLSZ " %d %d => " TLSZ " %d (%d)\n",
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136 | c570fd16 | ths | address, rw, access_type, *physical, *prot, ret);
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137 | 6af0bf9c | bellard | }
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138 | 6af0bf9c | bellard | #endif
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139 | 6af0bf9c | bellard | |
140 | 6af0bf9c | bellard | return ret;
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141 | 6af0bf9c | bellard | } |
142 | 6af0bf9c | bellard | |
143 | 6af0bf9c | bellard | #if defined(CONFIG_USER_ONLY)
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144 | 6af0bf9c | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
145 | 6af0bf9c | bellard | { |
146 | 6af0bf9c | bellard | return addr;
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147 | 6af0bf9c | bellard | } |
148 | 6af0bf9c | bellard | #else
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149 | 6af0bf9c | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
150 | 6af0bf9c | bellard | { |
151 | 6af0bf9c | bellard | target_ulong phys_addr; |
152 | 6af0bf9c | bellard | int prot;
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153 | 6af0bf9c | bellard | |
154 | 6af0bf9c | bellard | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
155 | 6af0bf9c | bellard | return -1; |
156 | 6af0bf9c | bellard | return phys_addr;
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157 | 6af0bf9c | bellard | } |
158 | 6af0bf9c | bellard | |
159 | 6af0bf9c | bellard | void cpu_mips_init_mmu (CPUState *env)
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160 | 6af0bf9c | bellard | { |
161 | 6af0bf9c | bellard | } |
162 | 6af0bf9c | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
163 | 6af0bf9c | bellard | |
164 | 6af0bf9c | bellard | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
165 | 6af0bf9c | bellard | int is_user, int is_softmmu) |
166 | 6af0bf9c | bellard | { |
167 | 6af0bf9c | bellard | target_ulong physical; |
168 | 6af0bf9c | bellard | int prot;
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169 | 6af0bf9c | bellard | int exception = 0, error_code = 0; |
170 | 6af0bf9c | bellard | int access_type;
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171 | 6af0bf9c | bellard | int ret = 0; |
172 | 6af0bf9c | bellard | |
173 | 6af0bf9c | bellard | if (logfile) {
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174 | 4ad40f36 | bellard | #if 0
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175 | 6af0bf9c | bellard | cpu_dump_state(env, logfile, fprintf, 0);
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176 | 4ad40f36 | bellard | #endif
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177 | c570fd16 | ths | fprintf(logfile, "%s pc " TLSZ " ad " TLSZ " rw %d is_user %d smmu %d\n", |
178 | 6af0bf9c | bellard | __func__, env->PC, address, rw, is_user, is_softmmu); |
179 | 6af0bf9c | bellard | } |
180 | 4ad40f36 | bellard | |
181 | 4ad40f36 | bellard | rw &= 1;
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182 | 4ad40f36 | bellard | |
183 | 6af0bf9c | bellard | /* data access */
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184 | 6af0bf9c | bellard | /* XXX: put correct access by using cpu_restore_state()
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185 | 6af0bf9c | bellard | correctly */
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186 | 6af0bf9c | bellard | access_type = ACCESS_INT; |
187 | 6af0bf9c | bellard | if (env->user_mode_only) {
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188 | 6af0bf9c | bellard | /* user mode only emulation */
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189 | 43057ab1 | bellard | ret = TLBRET_NOMATCH; |
190 | 6af0bf9c | bellard | goto do_fault;
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191 | 6af0bf9c | bellard | } |
192 | 6af0bf9c | bellard | ret = get_physical_address(env, &physical, &prot, |
193 | 6af0bf9c | bellard | address, rw, access_type); |
194 | 6af0bf9c | bellard | if (logfile) {
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195 | c570fd16 | ths | fprintf(logfile, "%s address=" TLSZ " ret %d physical " TLSZ " prot %d\n", |
196 | 6af0bf9c | bellard | __func__, address, ret, physical, prot); |
197 | 6af0bf9c | bellard | } |
198 | 43057ab1 | bellard | if (ret == TLBRET_MATCH) {
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199 | 43057ab1 | bellard | ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
200 | 43057ab1 | bellard | physical & TARGET_PAGE_MASK, prot, |
201 | 43057ab1 | bellard | is_user, is_softmmu); |
202 | 6af0bf9c | bellard | } else if (ret < 0) { |
203 | 6af0bf9c | bellard | do_fault:
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204 | 6af0bf9c | bellard | switch (ret) {
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205 | 6af0bf9c | bellard | default:
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206 | 43057ab1 | bellard | case TLBRET_BADADDR:
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207 | 6af0bf9c | bellard | /* Reference to kernel address from user mode or supervisor mode */
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208 | 6af0bf9c | bellard | /* Reference to supervisor address from user mode */
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209 | 6af0bf9c | bellard | if (rw)
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210 | 6af0bf9c | bellard | exception = EXCP_AdES; |
211 | 6af0bf9c | bellard | else
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212 | 6af0bf9c | bellard | exception = EXCP_AdEL; |
213 | 6af0bf9c | bellard | break;
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214 | 43057ab1 | bellard | case TLBRET_NOMATCH:
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215 | 6af0bf9c | bellard | /* No TLB match for a mapped address */
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216 | 6af0bf9c | bellard | if (rw)
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217 | 6af0bf9c | bellard | exception = EXCP_TLBS; |
218 | 6af0bf9c | bellard | else
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219 | 6af0bf9c | bellard | exception = EXCP_TLBL; |
220 | 6af0bf9c | bellard | error_code = 1;
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221 | 6af0bf9c | bellard | break;
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222 | 43057ab1 | bellard | case TLBRET_INVALID:
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223 | 6af0bf9c | bellard | /* TLB match with no valid bit */
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224 | 6af0bf9c | bellard | if (rw)
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225 | 6af0bf9c | bellard | exception = EXCP_TLBS; |
226 | 6af0bf9c | bellard | else
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227 | 6af0bf9c | bellard | exception = EXCP_TLBL; |
228 | 6af0bf9c | bellard | break;
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229 | 43057ab1 | bellard | case TLBRET_DIRTY:
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230 | 6af0bf9c | bellard | /* TLB match but 'D' bit is cleared */
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231 | 6af0bf9c | bellard | exception = EXCP_LTLBL; |
232 | 6af0bf9c | bellard | break;
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233 | 6af0bf9c | bellard | |
234 | 6af0bf9c | bellard | } |
235 | 6af0bf9c | bellard | /* Raise exception */
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236 | 6af0bf9c | bellard | env->CP0_BadVAddr = address; |
237 | 85498508 | bellard | env->CP0_Context = (env->CP0_Context & 0xff800000) |
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238 | 4ad40f36 | bellard | ((address >> 9) & 0x007ffff0); |
239 | 6af0bf9c | bellard | env->CP0_EntryHi = |
240 | 43057ab1 | bellard | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
241 | 6af0bf9c | bellard | env->exception_index = exception; |
242 | 6af0bf9c | bellard | env->error_code = error_code; |
243 | 6af0bf9c | bellard | ret = 1;
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244 | 6af0bf9c | bellard | } |
245 | 6af0bf9c | bellard | |
246 | 6af0bf9c | bellard | return ret;
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247 | 6af0bf9c | bellard | } |
248 | 6af0bf9c | bellard | |
249 | ca7c2b1b | ths | #if defined(CONFIG_USER_ONLY)
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250 | ca7c2b1b | ths | void do_interrupt (CPUState *env)
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251 | ca7c2b1b | ths | { |
252 | ca7c2b1b | ths | env->exception_index = EXCP_NONE; |
253 | ca7c2b1b | ths | } |
254 | ca7c2b1b | ths | #else
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255 | 6af0bf9c | bellard | void do_interrupt (CPUState *env)
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256 | 6af0bf9c | bellard | { |
257 | aa328add | ths | target_ulong offset; |
258 | 6af0bf9c | bellard | int cause = -1; |
259 | 6af0bf9c | bellard | |
260 | 6af0bf9c | bellard | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
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261 | c570fd16 | ths | fprintf(logfile, "%s enter: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n", |
262 | 6af0bf9c | bellard | __func__, env->PC, env->CP0_EPC, cause, env->exception_index); |
263 | 6af0bf9c | bellard | } |
264 | 6af0bf9c | bellard | if (env->exception_index == EXCP_EXT_INTERRUPT &&
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265 | 6af0bf9c | bellard | (env->hflags & MIPS_HFLAG_DM)) |
266 | 6af0bf9c | bellard | env->exception_index = EXCP_DINT; |
267 | 6af0bf9c | bellard | offset = 0x180;
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268 | 6af0bf9c | bellard | switch (env->exception_index) {
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269 | 6af0bf9c | bellard | case EXCP_DSS:
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270 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DSS;
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271 | 6af0bf9c | bellard | /* Debug single step cannot be raised inside a delay slot and
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272 | 6af0bf9c | bellard | * resume will always occur on the next instruction
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273 | 6af0bf9c | bellard | * (but we assume the pc has always been updated during
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274 | 6af0bf9c | bellard | * code translation).
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275 | 6af0bf9c | bellard | */
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276 | 6af0bf9c | bellard | env->CP0_DEPC = env->PC; |
277 | 6af0bf9c | bellard | goto enter_debug_mode;
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278 | 6af0bf9c | bellard | case EXCP_DINT:
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279 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DINT;
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280 | 6af0bf9c | bellard | goto set_DEPC;
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281 | 6af0bf9c | bellard | case EXCP_DIB:
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282 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DIB;
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283 | 6af0bf9c | bellard | goto set_DEPC;
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284 | 6af0bf9c | bellard | case EXCP_DBp:
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285 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DBp;
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286 | 6af0bf9c | bellard | goto set_DEPC;
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287 | 6af0bf9c | bellard | case EXCP_DDBS:
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288 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DDBS;
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289 | 6af0bf9c | bellard | goto set_DEPC;
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290 | 6af0bf9c | bellard | case EXCP_DDBL:
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291 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DDBL;
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292 | 6af0bf9c | bellard | goto set_DEPC;
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293 | 6af0bf9c | bellard | set_DEPC:
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294 | 4ad40f36 | bellard | if (env->hflags & MIPS_HFLAG_BMASK) {
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295 | 6af0bf9c | bellard | /* If the exception was raised from a delay slot,
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296 | aa328add | ths | come back to the jump. */
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297 | 6af0bf9c | bellard | env->CP0_DEPC = env->PC - 4;
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298 | 4ad40f36 | bellard | env->hflags &= ~MIPS_HFLAG_BMASK; |
299 | 6af0bf9c | bellard | } else {
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300 | 6af0bf9c | bellard | env->CP0_DEPC = env->PC; |
301 | 6af0bf9c | bellard | } |
302 | 6af0bf9c | bellard | enter_debug_mode:
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303 | 6af0bf9c | bellard | env->hflags |= MIPS_HFLAG_DM; |
304 | 6af0bf9c | bellard | /* EJTAG probe trap enable is not implemented... */
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305 | 5dc4b744 | ths | env->PC = (int32_t)0xBFC00480;
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306 | 6af0bf9c | bellard | break;
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307 | 6af0bf9c | bellard | case EXCP_RESET:
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308 | aa328add | ths | cpu_reset(env); |
309 | aa328add | ths | break;
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310 | 6af0bf9c | bellard | case EXCP_SRESET:
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311 | aa328add | ths | env->CP0_Status = (1 << CP0St_SR);
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312 | 6af0bf9c | bellard | env->CP0_WatchLo = 0;
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313 | 6af0bf9c | bellard | goto set_error_EPC;
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314 | 6af0bf9c | bellard | case EXCP_NMI:
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315 | aa328add | ths | env->CP0_Status = (1 << CP0St_NMI);
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316 | 6af0bf9c | bellard | set_error_EPC:
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317 | 4ad40f36 | bellard | if (env->hflags & MIPS_HFLAG_BMASK) {
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318 | 6af0bf9c | bellard | /* If the exception was raised from a delay slot,
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319 | aa328add | ths | come back to the jump. */
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320 | 6af0bf9c | bellard | env->CP0_ErrorEPC = env->PC - 4;
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321 | ecd78a0a | pbrook | env->hflags &= ~MIPS_HFLAG_BMASK; |
322 | 6af0bf9c | bellard | } else {
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323 | 6af0bf9c | bellard | env->CP0_ErrorEPC = env->PC; |
324 | 6af0bf9c | bellard | } |
325 | 3e382bc8 | bellard | env->hflags |= MIPS_HFLAG_ERL; |
326 | aa328add | ths | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
327 | 5dc4b744 | ths | env->PC = (int32_t)0xBFC00000;
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328 | 6af0bf9c | bellard | break;
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329 | 6af0bf9c | bellard | case EXCP_MCHECK:
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330 | 6af0bf9c | bellard | cause = 24;
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331 | 6af0bf9c | bellard | goto set_EPC;
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332 | 6af0bf9c | bellard | case EXCP_EXT_INTERRUPT:
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333 | 6af0bf9c | bellard | cause = 0;
|
334 | 6af0bf9c | bellard | if (env->CP0_Cause & (1 << CP0Ca_IV)) |
335 | 6af0bf9c | bellard | offset = 0x200;
|
336 | 6af0bf9c | bellard | goto set_EPC;
|
337 | 6af0bf9c | bellard | case EXCP_DWATCH:
|
338 | 6af0bf9c | bellard | cause = 23;
|
339 | 6af0bf9c | bellard | /* XXX: TODO: manage defered watch exceptions */
|
340 | 6af0bf9c | bellard | goto set_EPC;
|
341 | 6af0bf9c | bellard | case EXCP_AdEL:
|
342 | 6af0bf9c | bellard | case EXCP_AdES:
|
343 | 6af0bf9c | bellard | cause = 4;
|
344 | 6af0bf9c | bellard | goto set_EPC;
|
345 | 6af0bf9c | bellard | case EXCP_TLBL:
|
346 | 6af0bf9c | bellard | cause = 2;
|
347 | 6af0bf9c | bellard | if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL)) |
348 | 6af0bf9c | bellard | offset = 0x000;
|
349 | 6af0bf9c | bellard | goto set_EPC;
|
350 | 6af0bf9c | bellard | case EXCP_IBE:
|
351 | 6af0bf9c | bellard | cause = 6;
|
352 | 6af0bf9c | bellard | goto set_EPC;
|
353 | 6af0bf9c | bellard | case EXCP_DBE:
|
354 | 6af0bf9c | bellard | cause = 7;
|
355 | 6af0bf9c | bellard | goto set_EPC;
|
356 | 6af0bf9c | bellard | case EXCP_SYSCALL:
|
357 | 6af0bf9c | bellard | cause = 8;
|
358 | 6af0bf9c | bellard | goto set_EPC;
|
359 | 6af0bf9c | bellard | case EXCP_BREAK:
|
360 | 6af0bf9c | bellard | cause = 9;
|
361 | 6af0bf9c | bellard | goto set_EPC;
|
362 | 6af0bf9c | bellard | case EXCP_RI:
|
363 | 6af0bf9c | bellard | cause = 10;
|
364 | 6af0bf9c | bellard | goto set_EPC;
|
365 | 6af0bf9c | bellard | case EXCP_CpU:
|
366 | 6af0bf9c | bellard | cause = 11;
|
367 | 4ad40f36 | bellard | env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28); |
368 | 6af0bf9c | bellard | goto set_EPC;
|
369 | 6af0bf9c | bellard | case EXCP_OVERFLOW:
|
370 | 6af0bf9c | bellard | cause = 12;
|
371 | 6af0bf9c | bellard | goto set_EPC;
|
372 | 6af0bf9c | bellard | case EXCP_TRAP:
|
373 | 6af0bf9c | bellard | cause = 13;
|
374 | 6af0bf9c | bellard | goto set_EPC;
|
375 | 6af0bf9c | bellard | case EXCP_LTLBL:
|
376 | 6af0bf9c | bellard | cause = 1;
|
377 | 6af0bf9c | bellard | goto set_EPC;
|
378 | 6af0bf9c | bellard | case EXCP_TLBS:
|
379 | 6af0bf9c | bellard | cause = 3;
|
380 | 0d8aca8c | bellard | if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL)) |
381 | 0d8aca8c | bellard | offset = 0x000;
|
382 | 0d8aca8c | bellard | goto set_EPC;
|
383 | 6af0bf9c | bellard | set_EPC:
|
384 | 4ad40f36 | bellard | if (env->hflags & MIPS_HFLAG_BMASK) {
|
385 | 6af0bf9c | bellard | /* If the exception was raised from a delay slot,
|
386 | aa328add | ths | come back to the jump. */
|
387 | 6af0bf9c | bellard | env->CP0_EPC = env->PC - 4;
|
388 | 6af0bf9c | bellard | env->CP0_Cause |= 0x80000000;
|
389 | 4ad40f36 | bellard | env->hflags &= ~MIPS_HFLAG_BMASK; |
390 | 6af0bf9c | bellard | } else {
|
391 | 6af0bf9c | bellard | env->CP0_EPC = env->PC; |
392 | 6af0bf9c | bellard | env->CP0_Cause &= ~0x80000000;
|
393 | 6af0bf9c | bellard | } |
394 | aa328add | ths | if (env->CP0_Status & (1 << CP0St_BEV)) { |
395 | 5dc4b744 | ths | env->PC = (int32_t)0xBFC00200;
|
396 | aa328add | ths | } else {
|
397 | 5dc4b744 | ths | env->PC = (int32_t)0x80000000;
|
398 | aa328add | ths | } |
399 | aa328add | ths | env->hflags |= MIPS_HFLAG_EXL; |
400 | aa328add | ths | env->CP0_Status |= (1 << CP0St_EXL);
|
401 | aa328add | ths | env->PC += offset; |
402 | aa328add | ths | env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2); |
403 | 6af0bf9c | bellard | break;
|
404 | 6af0bf9c | bellard | default:
|
405 | 6af0bf9c | bellard | if (logfile) {
|
406 | 6af0bf9c | bellard | fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
|
407 | 6af0bf9c | bellard | env->exception_index); |
408 | 6af0bf9c | bellard | } |
409 | 6af0bf9c | bellard | printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
410 | 6af0bf9c | bellard | exit(1);
|
411 | 6af0bf9c | bellard | } |
412 | 6af0bf9c | bellard | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
413 | c570fd16 | ths | fprintf(logfile, "%s: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n" |
414 | c570fd16 | ths | " S %08x C %08x A " TLSZ " D " TLSZ "\n", |
415 | 6af0bf9c | bellard | __func__, env->PC, env->CP0_EPC, cause, env->exception_index, |
416 | 6af0bf9c | bellard | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
417 | 6af0bf9c | bellard | env->CP0_DEPC); |
418 | 6af0bf9c | bellard | } |
419 | 6af0bf9c | bellard | env->exception_index = EXCP_NONE; |
420 | 6af0bf9c | bellard | } |
421 | ca7c2b1b | ths | #endif /* !defined(CONFIG_USER_ONLY) */ |
422 | 2ee4aed8 | bellard | |
423 | 2ee4aed8 | bellard | void invalidate_tlb (CPUState *env, int idx, int use_extra) |
424 | 2ee4aed8 | bellard | { |
425 | 2ee4aed8 | bellard | tlb_t *tlb; |
426 | 3b1c8be4 | ths | target_ulong addr; |
427 | 3b1c8be4 | ths | target_ulong end; |
428 | 3b1c8be4 | ths | uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
429 | 3b1c8be4 | ths | target_ulong mask; |
430 | 2ee4aed8 | bellard | |
431 | 2ee4aed8 | bellard | tlb = &env->tlb[idx]; |
432 | 2ee4aed8 | bellard | /* The qemu TLB is flushed then the ASID changes, so no need to
|
433 | 2ee4aed8 | bellard | flush these entries again. */
|
434 | 2ee4aed8 | bellard | if (tlb->G == 0 && tlb->ASID != ASID) { |
435 | 2ee4aed8 | bellard | return;
|
436 | 2ee4aed8 | bellard | } |
437 | 2ee4aed8 | bellard | |
438 | 2ee4aed8 | bellard | if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
|
439 | 2ee4aed8 | bellard | /* For tlbwr, we can shadow the discarded entry into
|
440 | 2ee4aed8 | bellard | a new (fake) TLB entry, as long as the guest can not
|
441 | 2ee4aed8 | bellard | tell that it's there. */
|
442 | 2ee4aed8 | bellard | env->tlb[env->tlb_in_use] = *tlb; |
443 | 2ee4aed8 | bellard | env->tlb_in_use++; |
444 | 2ee4aed8 | bellard | return;
|
445 | 2ee4aed8 | bellard | } |
446 | 2ee4aed8 | bellard | |
447 | 3b1c8be4 | ths | /* 1k pages are not supported. */
|
448 | 3b1c8be4 | ths | mask = tlb->PageMask | 0x1FFF;
|
449 | 3b1c8be4 | ths | if (tlb->V0) {
|
450 | 3b1c8be4 | ths | addr = tlb->VPN; |
451 | 3b1c8be4 | ths | end = addr | (mask >> 1);
|
452 | 3b1c8be4 | ths | while (addr < end) {
|
453 | 3b1c8be4 | ths | tlb_flush_page (env, addr); |
454 | 3b1c8be4 | ths | addr += TARGET_PAGE_SIZE; |
455 | 3b1c8be4 | ths | } |
456 | 3b1c8be4 | ths | } |
457 | 3b1c8be4 | ths | if (tlb->V1) {
|
458 | 3b1c8be4 | ths | addr = tlb->VPN | ((mask >> 1) + 1); |
459 | 3b1c8be4 | ths | addr = tlb->VPN + TARGET_PAGE_SIZE; |
460 | 3b1c8be4 | ths | end = addr | mask; |
461 | 3b1c8be4 | ths | while (addr < end) {
|
462 | 3b1c8be4 | ths | tlb_flush_page (env, addr); |
463 | 3b1c8be4 | ths | addr += TARGET_PAGE_SIZE; |
464 | 3b1c8be4 | ths | } |
465 | 3b1c8be4 | ths | } |
466 | 2ee4aed8 | bellard | } |