root / target-mips / mips-defs.h @ ea785922
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1 | 6af0bf9c | bellard | #if !defined (__QEMU_MIPS_DEFS_H__)
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2 | 6af0bf9c | bellard | #define __QEMU_MIPS_DEFS_H__
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3 | 6af0bf9c | bellard | |
4 | 6af0bf9c | bellard | /* If we want to use 64 bits host regs... */
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5 | 6af0bf9c | bellard | //#define USE_64BITS_REGS
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6 | 6af0bf9c | bellard | /* If we want to use host float regs... */
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7 | 6af0bf9c | bellard | //#define USE_HOST_FLOAT_REGS
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8 | 6af0bf9c | bellard | |
9 | c5d6edc3 | bellard | #define MIPS_R4Kc 0x00018000 |
10 | c5d6edc3 | bellard | #define MIPS_R4Kp 0x00018300 |
11 | 6af0bf9c | bellard | |
12 | 6af0bf9c | bellard | /* Emulate MIPS R4Kc for now */
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13 | 6af0bf9c | bellard | #define MIPS_CPU MIPS_R4Kc
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14 | 6af0bf9c | bellard | |
15 | 6af0bf9c | bellard | #if (MIPS_CPU == MIPS_R4Kc)
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16 | 6af0bf9c | bellard | /* 32 bits target */
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17 | c570fd16 | ths | #undef MIPS_HAS_MIPS64
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18 | c570fd16 | ths | //#define MIPS_HAS_MIPS64 1
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19 | 6af0bf9c | bellard | /* real pages are variable size... */
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20 | 6af0bf9c | bellard | #define TARGET_PAGE_BITS 12 |
21 | c5d6edc3 | bellard | /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
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22 | 6af0bf9c | bellard | #define MIPS_USES_R4K_EXT
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23 | 6af0bf9c | bellard | /* Uses MIPS R4Kc TLB model */
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24 | 6af0bf9c | bellard | #define MIPS_USES_R4K_TLB
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25 | 6af0bf9c | bellard | #define MIPS_TLB_NB 16 |
26 | 814b9a47 | ths | #define MIPS_TLB_MAX 128 |
27 | 6ea83fed | bellard | /* basic FPU register support */
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28 | 6ea83fed | bellard | #define MIPS_USES_FPU 1 |
29 | 6ea83fed | bellard | /* Define a implementation number of 1.
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30 | 6ea83fed | bellard | * Define a major version 1, minor version 0.
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31 | 6ea83fed | bellard | */
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32 | 6ea83fed | bellard | #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0) |
33 | 7a387fff | ths | /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
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34 | 7a387fff | ths | uncached coherency */
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35 | 7a387fff | ths | #define MIPS_CONFIG0_1 \
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36 | 7a387fff | ths | ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \ |
37 | 7a387fff | ths | (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \ |
38 | 7a387fff | ths | (0x2 << CP0C0_K0))
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39 | c5d6edc3 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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40 | c5d6edc3 | bellard | #define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE)) |
41 | c5d6edc3 | bellard | #else
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42 | c5d6edc3 | bellard | #define MIPS_CONFIG0 MIPS_CONFIG0_1
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43 | c5d6edc3 | bellard | #endif
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44 | 7a387fff | ths | /* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
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45 | 7a387fff | ths | 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
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46 | 7a387fff | ths | no coprocessor2 attached, no MDMX support attached,
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47 | 7a387fff | ths | no performance counters, watch registers present,
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48 | 7a387fff | ths | no code compression, EJTAG present, FPU enable bit depending on
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49 | 7a387fff | ths | MIPS_USES_FPU */
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50 | 7a387fff | ths | #define MIPS_CONFIG1_1 \
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51 | 7a387fff | ths | ((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \ |
52 | 7a387fff | ths | (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \ |
53 | 7a387fff | ths | (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \ |
54 | 7a387fff | ths | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
55 | 7a387fff | ths | (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP)) |
56 | 7a387fff | ths | #ifdef MIPS_USES_FPU
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57 | 7a387fff | ths | #define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (1 << CP0C1_FP)) |
58 | 7a387fff | ths | #else
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59 | 7a387fff | ths | #define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (0 << CP0C1_FP)) |
60 | 7a387fff | ths | #endif
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61 | 7a387fff | ths | /* Have config3, no tertiary/secondary caches implemented */
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62 | 7a387fff | ths | #define MIPS_CONFIG2 \
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63 | 7a387fff | ths | ((1 << CP0C2_M))
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64 | 7a387fff | ths | /* No config4, no DSP ASE, no large physaddr,
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65 | 7a387fff | ths | no external interrupt controller, no vectored interupts,
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66 | 7a387fff | ths | no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
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67 | 7a387fff | ths | #define MIPS_CONFIG3 \
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68 | 7a387fff | ths | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
69 | 7a387fff | ths | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
70 | 7a387fff | ths | (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
71 | c5d6edc3 | bellard | #elif (MIPS_CPU == MIPS_R4Kp)
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72 | 6af0bf9c | bellard | /* 32 bits target */
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73 | c570fd16 | ths | #undef MIPS_HAS_MIPS64
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74 | 6af0bf9c | bellard | /* real pages are variable size... */
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75 | 6af0bf9c | bellard | #define TARGET_PAGE_BITS 12 |
76 | c5d6edc3 | bellard | /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
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77 | 6af0bf9c | bellard | #define MIPS_USES_R4K_EXT
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78 | 6af0bf9c | bellard | /* Uses MIPS R4Km FPM MMU model */
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79 | 6af0bf9c | bellard | #define MIPS_USES_R4K_FPM
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80 | 6af0bf9c | bellard | #else
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81 | 6af0bf9c | bellard | #error "MIPS CPU not defined" |
82 | 7a387fff | ths | /* Reminder for other flags */
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83 | c570fd16 | ths | //#undef MIPS_HAS_MIPS64
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84 | 6ea83fed | bellard | //#define MIPS_USES_FPU
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85 | 6af0bf9c | bellard | #endif
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86 | 6af0bf9c | bellard | |
87 | c570fd16 | ths | #ifdef MIPS_HAS_MIPS64
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88 | c570fd16 | ths | #define TARGET_LONG_BITS 64 |
89 | c570fd16 | ths | #else
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90 | c570fd16 | ths | #define TARGET_LONG_BITS 32 |
91 | c570fd16 | ths | #endif
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92 | c570fd16 | ths | |
93 | 6af0bf9c | bellard | #endif /* !defined (__QEMU_MIPS_DEFS_H__) */ |